[linux-block.git] / drivers / gpio / gpio-timberdale.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Timberdale FPGA GPIO driver
 * Author: Mocean Laboratories
 * Copyright (c) 2009 Intel Corporation
 */

/* Supports:
 * Timberdale FPGA GPIO
 */

#include <linux/init.h>
#include <linux/gpio/driver.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/timb_gpio.h>
#include <linux/interrupt.h>
#include <linux/slab.h>

#define DRIVER_NAME "timb-gpio"

#define TGPIOVAL	0x00
#define TGPIODIR	0x04
#define TGPIO_IER	0x08
#define TGPIO_ISR	0x0c
#define TGPIO_IPR	0x10
#define TGPIO_ICR	0x14
#define TGPIO_FLR	0x18
#define TGPIO_LVR	0x1c
#define TGPIO_VER	0x20
#define TGPIO_BFLR	0x24

struct timbgpio {
	void __iomem		*membase;
	spinlock_t		lock; /* mutual exclusion */
	struct gpio_chip	gpio;
	int			irq_base;
	unsigned long		last_ier;
};

static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
	unsigned offset, bool enabled)
{
	struct timbgpio *tgpio = gpiochip_get_data(gpio);
	u32 reg;

	spin_lock(&tgpio->lock);
	reg = ioread32(tgpio->membase + offset);

	if (enabled)
		reg |= (1 << index);
	else
		reg &= ~(1 << index);

	iowrite32(reg, tgpio->membase + offset);
	spin_unlock(&tgpio->lock);

	return 0;
}

static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
}

static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
	struct timbgpio *tgpio = gpiochip_get_data(gpio);
	u32 value;

	value = ioread32(tgpio->membase + TGPIOVAL);
	return (value & (1 << nr)) ? 1 : 0;
}

static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
						unsigned nr, int val)
{
	return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
}

static void timbgpio_gpio_set(struct gpio_chip *gpio,
				unsigned nr, int val)
{
	timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
}

static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
	struct timbgpio *tgpio = gpiochip_get_data(gpio);

	if (tgpio->irq_base <= 0)
		return -EINVAL;

	return tgpio->irq_base + offset;
}

/*
 * GPIO IRQ
 */
static void timbgpio_irq_disable(struct irq_data *d)
{
	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - tgpio->irq_base;
	unsigned long flags;

	spin_lock_irqsave(&tgpio->lock, flags);
	tgpio->last_ier &= ~(1UL << offset);
	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
	spin_unlock_irqrestore(&tgpio->lock, flags);
}

static void timbgpio_irq_enable(struct irq_data *d)
{
	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - tgpio->irq_base;
	unsigned long flags;

	spin_lock_irqsave(&tgpio->lock, flags);
	tgpio->last_ier |= 1UL << offset;
	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
	spin_unlock_irqrestore(&tgpio->lock, flags);
}

static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
{
	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
	int offset = d->irq - tgpio->irq_base;
	unsigned long flags;
	u32 lvr, flr, bflr = 0;
	u32 ver;
	int ret = 0;

	if (offset < 0 || offset > tgpio->gpio.ngpio)
		return -EINVAL;

	ver = ioread32(tgpio->membase + TGPIO_VER);

	spin_lock_irqsave(&tgpio->lock, flags);

	lvr = ioread32(tgpio->membase + TGPIO_LVR);
	flr = ioread32(tgpio->membase + TGPIO_FLR);
	if (ver > 2)
		bflr = ioread32(tgpio->membase + TGPIO_BFLR);

	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		bflr &= ~(1 << offset);
		flr &= ~(1 << offset);
		if (trigger & IRQ_TYPE_LEVEL_HIGH)
			lvr |= 1 << offset;
		else
			lvr &= ~(1 << offset);
	}

	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
		if (ver < 3) {
			ret = -EINVAL;
			goto out;
		} else {
			flr |= 1 << offset;
			bflr |= 1 << offset;
		}
	} else {
		bflr &= ~(1 << offset);
		flr |= 1 << offset;
		if (trigger & IRQ_TYPE_EDGE_FALLING)
			lvr &= ~(1 << offset);
		else
			lvr |= 1 << offset;
	}

	iowrite32(lvr, tgpio->membase + TGPIO_LVR);
	iowrite32(flr, tgpio->membase + TGPIO_FLR);
	if (ver > 2)
		iowrite32(bflr, tgpio->membase + TGPIO_BFLR);

	iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);

out:
	spin_unlock_irqrestore(&tgpio->lock, flags);
	return ret;
}

static void timbgpio_irq(struct irq_desc *desc)
{
	struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
	struct irq_data *data = irq_desc_get_irq_data(desc);
	unsigned long ipr;
	int offset;

	data->chip->irq_ack(data);
	ipr = ioread32(tgpio->membase + TGPIO_IPR);
	iowrite32(ipr, tgpio->membase + TGPIO_ICR);

	/*
	 * Some versions of the hardware trash the IER register if more than
	 * one interrupt is received simultaneously.
	 */
	iowrite32(0, tgpio->membase + TGPIO_IER);

	for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
		generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));

	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
}

static struct irq_chip timbgpio_irqchip = {
	.name		= "GPIO",
	.irq_enable	= timbgpio_irq_enable,
	.irq_disable	= timbgpio_irq_disable,
	.irq_set_type	= timbgpio_irq_type,
};

static int timbgpio_probe(struct platform_device *pdev)
{
	int err, i;
	struct device *dev = &pdev->dev;
	struct gpio_chip *gc;
	struct timbgpio *tgpio;
	struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
	int irq = platform_get_irq(pdev, 0);

	if (!pdata || pdata->nr_pins > 32) {
		dev_err(dev, "Invalid platform data\n");
		return -EINVAL;
	}

	tgpio = devm_kzalloc(dev, sizeof(*tgpio), GFP_KERNEL);
	if (!tgpio)
		return -EINVAL;

	tgpio->irq_base = pdata->irq_base;

	spin_lock_init(&tgpio->lock);

	tgpio->membase = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(tgpio->membase))
		return PTR_ERR(tgpio->membase);

	gc = &tgpio->gpio;

	gc->label = dev_name(&pdev->dev);
	gc->owner = THIS_MODULE;
	gc->parent = &pdev->dev;
	gc->direction_input = timbgpio_gpio_direction_input;
	gc->get = timbgpio_gpio_get;
	gc->direction_output = timbgpio_gpio_direction_output;
	gc->set = timbgpio_gpio_set;
	gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
	gc->dbg_show = NULL;
	gc->base = pdata->gpio_base;
	gc->ngpio = pdata->nr_pins;
	gc->can_sleep = false;

	err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
	if (err)
		return err;

	platform_set_drvdata(pdev, tgpio);

	/* make sure to disable interrupts */
	iowrite32(0x0, tgpio->membase + TGPIO_IER);

	if (irq < 0 || tgpio->irq_base <= 0)
		return 0;

	for (i = 0; i < pdata->nr_pins; i++) {
		irq_set_chip_and_handler(tgpio->irq_base + i,
			&timbgpio_irqchip, handle_simple_irq);
		irq_set_chip_data(tgpio->irq_base + i, tgpio);
		irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST | IRQ_NOPROBE);
	}

	irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);

	return 0;
}

static struct platform_driver timbgpio_platform_driver = {
	.driver = {
		.name			= DRIVER_NAME,
		.suppress_bind_attrs	= true,
	},
	.probe		= timbgpio_probe,
};

/*--------------------------------------------------------------------------*/

builtin_platform_driver(timbgpio_platform_driver);
Commit	Line	Data
82c29810	1	// SPDX-License-Identifier: GPL-2.0-only
35570ac6	2	/*
c103de24	3	* Timberdale FPGA GPIO driver
52ad9053	4	* Author: Mocean Laboratories
35570ac6	5	* Copyright (c) 2009 Intel Corporation
35570ac6 RR	6	*/
	7
	8	/* Supports:
	9	* Timberdale FPGA GPIO
	10	*/
	11
52ad9053	12	#include <linux/init.h>
50fe83a3	13	#include <linux/gpio/driver.h>
35570ac6	14	#include <linux/platform_device.h>
e3cb91ce	15	#include <linux/irq.h>
35570ac6 RR	16	#include <linux/io.h>
	17	#include <linux/timb_gpio.h>
	18	#include <linux/interrupt.h>
5a0e3ad6	19	#include <linux/slab.h>
35570ac6 RR	20
	21	#define DRIVER_NAME "timb-gpio"
	22
	23	#define TGPIOVAL 0x00
	24	#define TGPIODIR 0x04
	25	#define TGPIO_IER 0x08
	26	#define TGPIO_ISR 0x0c
	27	#define TGPIO_IPR 0x10
	28	#define TGPIO_ICR 0x14
	29	#define TGPIO_FLR 0x18
	30	#define TGPIO_LVR 0x1c
8c35c89a RR	31	#define TGPIO_VER 0x20
8c35c89a RR	32	#define TGPIO_BFLR 0x24
35570ac6 RR	33
	34	struct timbgpio {
	35	void __iomem *membase;
	36	spinlock_t lock; /* mutual exclusion */
	37	struct gpio_chip gpio;
	38	int irq_base;
76d800a5	39	unsigned long last_ier;
35570ac6 RR	40	};
	41
	42	static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
	43	unsigned offset, bool enabled)
	44	{
92a41e2f	45	struct timbgpio *tgpio = gpiochip_get_data(gpio);
35570ac6 RR	46	u32 reg;
	47
	48	spin_lock(&tgpio->lock);
	49	reg = ioread32(tgpio->membase + offset);
	50
	51	if (enabled)
	52	reg \|= (1 << index);
	53	else
	54	reg &= ~(1 << index);
	55
	56	iowrite32(reg, tgpio->membase + offset);
	57	spin_unlock(&tgpio->lock);
	58
	59	return 0;
	60	}
	61
	62	static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	63	{
	64	return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
	65	}
	66
	67	static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
	68	{
92a41e2f	69	struct timbgpio *tgpio = gpiochip_get_data(gpio);
35570ac6 RR	70	u32 value;
	71
	72	value = ioread32(tgpio->membase + TGPIOVAL);
	73	return (value & (1 << nr)) ? 1 : 0;
	74	}
	75
	76	static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
	77	unsigned nr, int val)
	78	{
	79	return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
	80	}
	81
	82	static void timbgpio_gpio_set(struct gpio_chip *gpio,
	83	unsigned nr, int val)
	84	{
	85	timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
	86	}
	87
	88	static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
	89	{
92a41e2f	90	struct timbgpio *tgpio = gpiochip_get_data(gpio);
35570ac6 RR	91
	92	if (tgpio->irq_base <= 0)
	93	return -EINVAL;
	94
	95	return tgpio->irq_base + offset;
	96	}
	97
	98	/*
	99	* GPIO IRQ
	100	*/
a1f5f22a	101	static void timbgpio_irq_disable(struct irq_data *d)
35570ac6	102	{
a1f5f22a LB	103	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
a1f5f22a LB	104	int offset = d->irq - tgpio->irq_base;
76d800a5	105	unsigned long flags;
35570ac6	106
76d800a5	107	spin_lock_irqsave(&tgpio->lock, flags);
d79550a7	108	tgpio->last_ier &= ~(1UL << offset);
76d800a5 TH	109	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
76d800a5 TH	110	spin_unlock_irqrestore(&tgpio->lock, flags);
35570ac6 RR	111	}
35570ac6 RR	112
a1f5f22a	113	static void timbgpio_irq_enable(struct irq_data *d)
35570ac6	114	{
a1f5f22a LB	115	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
a1f5f22a LB	116	int offset = d->irq - tgpio->irq_base;
76d800a5	117	unsigned long flags;
35570ac6	118
76d800a5	119	spin_lock_irqsave(&tgpio->lock, flags);
d79550a7	120	tgpio->last_ier \|= 1UL << offset;
76d800a5 TH	121	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
76d800a5 TH	122	spin_unlock_irqrestore(&tgpio->lock, flags);
35570ac6 RR	123	}
35570ac6 RR	124
a1f5f22a	125	static int timbgpio_irq_type(struct irq_data *d, unsigned trigger)
35570ac6	126	{
a1f5f22a LB	127	struct timbgpio *tgpio = irq_data_get_irq_chip_data(d);
a1f5f22a LB	128	int offset = d->irq - tgpio->irq_base;
35570ac6	129	unsigned long flags;
8c35c89a RR	130	u32 lvr, flr, bflr = 0;
8c35c89a RR	131	u32 ver;
2a481800	132	int ret = 0;
35570ac6 RR	133
	134	if (offset < 0 \|\| offset > tgpio->gpio.ngpio)
	135	return -EINVAL;
	136
8c35c89a RR	137	ver = ioread32(tgpio->membase + TGPIO_VER);
8c35c89a RR	138
35570ac6 RR	139	spin_lock_irqsave(&tgpio->lock, flags);
	140
	141	lvr = ioread32(tgpio->membase + TGPIO_LVR);
	142	flr = ioread32(tgpio->membase + TGPIO_FLR);
8c35c89a RR	143	if (ver > 2)
8c35c89a RR	144	bflr = ioread32(tgpio->membase + TGPIO_BFLR);
35570ac6 RR	145
35570ac6 RR	146	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
8c35c89a	147	bflr &= ~(1 << offset);
35570ac6 RR	148	flr &= ~(1 << offset);
	149	if (trigger & IRQ_TYPE_LEVEL_HIGH)
	150	lvr \|= 1 << offset;
	151	else
	152	lvr &= ~(1 << offset);
	153	}
	154
8c35c89a	155	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
2a481800 JL	156	if (ver < 3) {
	157	ret = -EINVAL;
	158	goto out;
8a29a409	159	} else {
8c35c89a RR	160	flr \|= 1 << offset;
	161	bflr \|= 1 << offset;
	162	}
	163	} else {
	164	bflr &= ~(1 << offset);
35570ac6	165	flr \|= 1 << offset;
35570ac6	166	if (trigger & IRQ_TYPE_EDGE_FALLING)
35570ac6	167	lvr &= ~(1 << offset);
8c35c89a RR	168	else
8c35c89a RR	169	lvr \|= 1 << offset;
35570ac6 RR	170	}
	171
	172	iowrite32(lvr, tgpio->membase + TGPIO_LVR);
	173	iowrite32(flr, tgpio->membase + TGPIO_FLR);
8c35c89a RR	174	if (ver > 2)
	175	iowrite32(bflr, tgpio->membase + TGPIO_BFLR);
	176
35570ac6	177	iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
35570ac6	178
2a481800 JL	179	out:
	180	spin_unlock_irqrestore(&tgpio->lock, flags);
	181	return ret;
35570ac6 RR	182	}
35570ac6 RR	183
bd0b9ac4	184	static void timbgpio_irq(struct irq_desc *desc)
35570ac6	185	{
476f8b4c JL	186	struct timbgpio *tgpio = irq_desc_get_handler_data(desc);
476f8b4c JL	187	struct irq_data *data = irq_desc_get_irq_data(desc);
35570ac6 RR	188	unsigned long ipr;
	189	int offset;
	190
476f8b4c	191	data->chip->irq_ack(data);
35570ac6 RR	192	ipr = ioread32(tgpio->membase + TGPIO_IPR);
	193	iowrite32(ipr, tgpio->membase + TGPIO_ICR);
	194
76d800a5 TH	195	/*
	196	* Some versions of the hardware trash the IER register if more than
	197	* one interrupt is received simultaneously.
	198	*/
	199	iowrite32(0, tgpio->membase + TGPIO_IER);
	200
984b3f57	201	for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
35570ac6	202	generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
76d800a5 TH	203
76d800a5 TH	204	iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER);
35570ac6 RR	205	}
	206
	207	static struct irq_chip timbgpio_irqchip = {
	208	.name = "GPIO",
a1f5f22a LB	209	.irq_enable = timbgpio_irq_enable,
	210	.irq_disable = timbgpio_irq_disable,
	211	.irq_set_type = timbgpio_irq_type,
35570ac6 RR	212	};
35570ac6 RR	213
3836309d	214	static int timbgpio_probe(struct platform_device *pdev)
35570ac6 RR	215	{
35570ac6 RR	216	int err, i;
0ed3398e	217	struct device *dev = &pdev->dev;
35570ac6 RR	218	struct gpio_chip *gc;
35570ac6 RR	219	struct timbgpio *tgpio;
e56aee18	220	struct timbgpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
35570ac6 RR	221	int irq = platform_get_irq(pdev, 0);
	222
	223	if (!pdata \|\| pdata->nr_pins > 32) {
0ed3398e	224	dev_err(dev, "Invalid platform data\n");
0ed3398e	225	return -EINVAL;
35570ac6 RR	226	}
35570ac6 RR	227
2c3087e1	228	tgpio = devm_kzalloc(dev, sizeof(*tgpio), GFP_KERNEL);
587ca5ed	229	if (!tgpio)
0ed3398e	230	return -EINVAL;
587ca5ed	231
35570ac6 RR	232	tgpio->irq_base = pdata->irq_base;
	233
	234	spin_lock_init(&tgpio->lock);
	235
aa6c9b91	236	tgpio->membase = devm_platform_ioremap_resource(pdev, 0);
fa283db7 AKC	237	if (IS_ERR(tgpio->membase))
fa283db7 AKC	238	return PTR_ERR(tgpio->membase);
35570ac6 RR	239
	240	gc = &tgpio->gpio;
	241
	242	gc->label = dev_name(&pdev->dev);
	243	gc->owner = THIS_MODULE;
58383c78	244	gc->parent = &pdev->dev;
35570ac6 RR	245	gc->direction_input = timbgpio_gpio_direction_input;
	246	gc->get = timbgpio_gpio_get;
	247	gc->direction_output = timbgpio_gpio_direction_output;
	248	gc->set = timbgpio_gpio_set;
	249	gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
	250	gc->dbg_show = NULL;
	251	gc->base = pdata->gpio_base;
	252	gc->ngpio = pdata->nr_pins;
9fb1f39e	253	gc->can_sleep = false;
35570ac6	254
43fad832	255	err = devm_gpiochip_add_data(&pdev->dev, gc, tgpio);
35570ac6	256	if (err)
0ed3398e	257	return err;
35570ac6 RR	258
	259	platform_set_drvdata(pdev, tgpio);
	260
	261	/* make sure to disable interrupts */
	262	iowrite32(0x0, tgpio->membase + TGPIO_IER);
	263
	264	if (irq < 0 \|\| tgpio->irq_base <= 0)
	265	return 0;
	266
	267	for (i = 0; i < pdata->nr_pins; i++) {
e5428a68 LW	268	irq_set_chip_and_handler(tgpio->irq_base + i,
e5428a68 LW	269	&timbgpio_irqchip, handle_simple_irq);
b51804bc	270	irq_set_chip_data(tgpio->irq_base + i, tgpio);
23393d49	271	irq_clear_status_flags(tgpio->irq_base + i, IRQ_NOREQUEST \| IRQ_NOPROBE);
35570ac6 RR	272	}
35570ac6 RR	273
8a52211a	274	irq_set_chained_handler_and_data(irq, timbgpio_irq, tgpio);
35570ac6 RR	275
35570ac6 RR	276	return 0;
35570ac6 RR	277	}
35570ac6 RR	278
35570ac6 RR	279	static struct platform_driver timbgpio_platform_driver = {
35570ac6 RR	280	.driver = {
52ad9053 PG	281	.name = DRIVER_NAME,
52ad9053 PG	282	.suppress_bind_attrs = true,
35570ac6 RR	283	},
35570ac6 RR	284	.probe = timbgpio_probe,
35570ac6 RR	285	};
	286
	287	/--------------------------------------------------------------------------/
	288
52ad9053	289	builtin_platform_driver(timbgpio_platform_driver);