[linux-block.git] / drivers / gpio / gpio-thunderx.c

/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2016, 2017 Cavium Inc.
 */

#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/spinlock.h>

#define GPIO_RX_DAT	0x0
#define GPIO_TX_SET	0x8
#define GPIO_TX_CLR	0x10
#define GPIO_CONST	0x90
#define  GPIO_CONST_GPIOS_MASK 0xff
#define GPIO_BIT_CFG	0x400
#define  GPIO_BIT_CFG_TX_OE		BIT(0)
#define  GPIO_BIT_CFG_PIN_XOR		BIT(1)
#define  GPIO_BIT_CFG_INT_EN		BIT(2)
#define  GPIO_BIT_CFG_INT_TYPE		BIT(3)
#define  GPIO_BIT_CFG_FIL_MASK		GENMASK(11, 4)
#define  GPIO_BIT_CFG_FIL_CNT_SHIFT	4
#define  GPIO_BIT_CFG_FIL_SEL_SHIFT	8
#define  GPIO_BIT_CFG_TX_OD		BIT(12)
#define  GPIO_BIT_CFG_PIN_SEL_MASK	GENMASK(25, 16)
#define GPIO_INTR	0x800
#define  GPIO_INTR_INTR			BIT(0)
#define  GPIO_INTR_INTR_W1S		BIT(1)
#define  GPIO_INTR_ENA_W1C		BIT(2)
#define  GPIO_INTR_ENA_W1S		BIT(3)
#define GPIO_2ND_BANK	0x1400

#define GLITCH_FILTER_400NS ((4u << GPIO_BIT_CFG_FIL_SEL_SHIFT) | \
			     (9u << GPIO_BIT_CFG_FIL_CNT_SHIFT))

struct thunderx_gpio;

struct thunderx_line {
	struct thunderx_gpio	*txgpio;
	unsigned int		line;
	unsigned int		fil_bits;
};

struct thunderx_gpio {
	struct gpio_chip	chip;
	u8 __iomem		*register_base;
	struct msix_entry	*msix_entries;	/* per line MSI-X */
	struct thunderx_line	*line_entries;	/* per line irq info */
	raw_spinlock_t		lock;
	unsigned long		invert_mask[2];
	unsigned long		od_mask[2];
	int			base_msi;
};

static unsigned int bit_cfg_reg(unsigned int line)
{
	return 8 * line + GPIO_BIT_CFG;
}

static unsigned int intr_reg(unsigned int line)
{
	return 8 * line + GPIO_INTR;
}

static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio,
					 unsigned int line)
{
	u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));

	return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0;
}

/*
 * Check (and WARN) that the pin is available for GPIO.  We will not
 * allow modification of the state of non-GPIO pins from this driver.
 */
static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio,
				  unsigned int line)
{
	bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line);

	WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line);

	return rv;
}

static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line)
{
	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);

	return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO;
}

static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line)
{
	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);

	if (!thunderx_gpio_is_gpio(txgpio, line))
		return -EIO;

	raw_spin_lock(&txgpio->lock);
	clear_bit(line, txgpio->invert_mask);
	clear_bit(line, txgpio->od_mask);
	writeq(txgpio->line_entries[line].fil_bits,
	       txgpio->register_base + bit_cfg_reg(line));
	raw_spin_unlock(&txgpio->lock);
	return 0;
}

static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line,
			      int value)
{
	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
	int bank = line / 64;
	int bank_bit = line % 64;

	void __iomem *reg = txgpio->register_base +
		(bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR);

	writeq(BIT_ULL(bank_bit), reg);
}

static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line,
				 int value)
{
	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
	u64 bit_cfg = txgpio->line_entries[line].fil_bits | GPIO_BIT_CFG_TX_OE;

	if (!thunderx_gpio_is_gpio(txgpio, line))
		return -EIO;

	raw_spin_lock(&txgpio->lock);

	thunderx_gpio_set(chip, line, value);

	if (test_bit(line, txgpio->invert_mask))
		bit_cfg |= GPIO_BIT_CFG_PIN_XOR;

	if (test_bit(line, txgpio->od_mask))
		bit_cfg |= GPIO_BIT_CFG_TX_OD;

	writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));

	raw_spin_unlock(&txgpio->lock);
	return 0;
}

static int thunderx_gpio_get_direction(struct gpio_chip *chip, unsigned int line)
{
	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
	u64 bit_cfg;

	if (!thunderx_gpio_is_gpio_nowarn(txgpio, line))
		/*
		 * Say it is input for now to avoid WARNing on
		 * gpiochip_add_data().  We will WARN if someone
		 * requests it or tries to use it.
		 */
		return 1;

	bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));

	if (bit_cfg & GPIO_BIT_CFG_TX_OE)
		return GPIO_LINE_DIRECTION_OUT;

	return GPIO_LINE_DIRECTION_IN;
}

static int thunderx_gpio_set_config(struct gpio_chip *chip,
				    unsigned int line,
				    unsigned long cfg)
{
	bool orig_invert, orig_od, orig_dat, new_invert, new_od;
	u32 arg, sel;
	u64 bit_cfg;
	int bank = line / 64;
	int bank_bit = line % 64;
	int ret = -ENOTSUPP;
	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
	void __iomem *reg = txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET;

	if (!thunderx_gpio_is_gpio(txgpio, line))
		return -EIO;

	raw_spin_lock(&txgpio->lock);
	orig_invert = test_bit(line, txgpio->invert_mask);
	new_invert  = orig_invert;
	orig_od = test_bit(line, txgpio->od_mask);
	new_od = orig_od;
	orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert;
	bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
	switch (pinconf_to_config_param(cfg)) {
	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
		/*
		 * Weird, setting open-drain mode causes signal
		 * inversion.  Note this so we can compensate in the
		 * dir_out function.
		 */
		set_bit(line, txgpio->invert_mask);
		new_invert  = true;
		set_bit(line, txgpio->od_mask);
		new_od = true;
		ret = 0;
		break;
	case PIN_CONFIG_DRIVE_PUSH_PULL:
		clear_bit(line, txgpio->invert_mask);
		new_invert  = false;
		clear_bit(line, txgpio->od_mask);
		new_od  = false;
		ret = 0;
		break;
	case PIN_CONFIG_INPUT_DEBOUNCE:
		arg = pinconf_to_config_argument(cfg);
		if (arg > 1228) { /* 15 * 2^15 * 2.5nS maximum */
			ret = -EINVAL;
			break;
		}
		arg *= 400; /* scale to 2.5nS clocks. */
		sel = 0;
		while (arg > 15) {
			sel++;
			arg++; /* always round up */
			arg >>= 1;
		}
		txgpio->line_entries[line].fil_bits =
			(sel << GPIO_BIT_CFG_FIL_SEL_SHIFT) |
			(arg << GPIO_BIT_CFG_FIL_CNT_SHIFT);
		bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK;
		bit_cfg |= txgpio->line_entries[line].fil_bits;
		writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
		ret = 0;
		break;
	default:
		break;
	}
	raw_spin_unlock(&txgpio->lock);

	/*
	 * If currently output and OPEN_DRAIN changed, install the new
	 * settings
	 */
	if ((new_invert != orig_invert || new_od != orig_od) &&
	    (bit_cfg & GPIO_BIT_CFG_TX_OE))
		ret = thunderx_gpio_dir_out(chip, line, orig_dat ^ new_invert);

	return ret;
}

static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line)
{
	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
	int bank = line / 64;
	int bank_bit = line % 64;
	u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);
	u64 masked_bits = read_bits & BIT_ULL(bank_bit);

	if (test_bit(line, txgpio->invert_mask))
		return masked_bits == 0;
	else
		return masked_bits != 0;
}

static void thunderx_gpio_set_multiple(struct gpio_chip *chip,
				       unsigned long *mask,
				       unsigned long *bits)
{
	int bank;
	u64 set_bits, clear_bits;
	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);

	for (bank = 0; bank <= chip->ngpio / 64; bank++) {
		set_bits = bits[bank] & mask[bank];
		clear_bits = ~bits[bank] & mask[bank];
		writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
		writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);
	}
}

static void thunderx_gpio_irq_ack(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);

	writeq(GPIO_INTR_INTR,
	       txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
}

static void thunderx_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);

	writeq(GPIO_INTR_ENA_W1C,
	       txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
}

static void thunderx_gpio_irq_mask_ack(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);

	writeq(GPIO_INTR_ENA_W1C | GPIO_INTR_INTR,
	       txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
}

static void thunderx_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);

	writeq(GPIO_INTR_ENA_W1S,
	       txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
}

static int thunderx_gpio_irq_set_type(struct irq_data *d,
				      unsigned int flow_type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
	struct thunderx_line *txline =
		&txgpio->line_entries[irqd_to_hwirq(d)];
	u64 bit_cfg;

	irqd_set_trigger_type(d, flow_type);

	bit_cfg = txline->fil_bits | GPIO_BIT_CFG_INT_EN;

	if (flow_type & IRQ_TYPE_EDGE_BOTH) {
		irq_set_handler_locked(d, handle_fasteoi_ack_irq);
		bit_cfg |= GPIO_BIT_CFG_INT_TYPE;
	} else {
		irq_set_handler_locked(d, handle_fasteoi_mask_irq);
	}

	raw_spin_lock(&txgpio->lock);
	if (flow_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)) {
		bit_cfg |= GPIO_BIT_CFG_PIN_XOR;
		set_bit(txline->line, txgpio->invert_mask);
	} else {
		clear_bit(txline->line, txgpio->invert_mask);
	}
	clear_bit(txline->line, txgpio->od_mask);
	writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));
	raw_spin_unlock(&txgpio->lock);

	return IRQ_SET_MASK_OK;
}

static void thunderx_gpio_irq_enable(struct irq_data *data)
{
	irq_chip_enable_parent(data);
	thunderx_gpio_irq_unmask(data);
}

static void thunderx_gpio_irq_disable(struct irq_data *data)
{
	thunderx_gpio_irq_mask(data);
	irq_chip_disable_parent(data);
}

/*
 * Interrupts are chained from underlying MSI-X vectors.  We have
 * these irq_chip functions to be able to handle level triggering
 * semantics and other acknowledgment tasks associated with the GPIO
 * mechanism.
 */
static struct irq_chip thunderx_gpio_irq_chip = {
	.name			= "GPIO",
	.irq_enable		= thunderx_gpio_irq_enable,
	.irq_disable		= thunderx_gpio_irq_disable,
	.irq_ack		= thunderx_gpio_irq_ack,
	.irq_mask		= thunderx_gpio_irq_mask,
	.irq_mask_ack		= thunderx_gpio_irq_mask_ack,
	.irq_unmask		= thunderx_gpio_irq_unmask,
	.irq_eoi		= irq_chip_eoi_parent,
	.irq_set_affinity	= irq_chip_set_affinity_parent,
	.irq_set_type		= thunderx_gpio_irq_set_type,

	.flags			= IRQCHIP_SET_TYPE_MASKED
};

static int thunderx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
					       unsigned int child,
					       unsigned int child_type,
					       unsigned int *parent,
					       unsigned int *parent_type)
{
	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
	struct irq_data *irqd;
	unsigned int irq;

	irq = txgpio->msix_entries[child].vector;
	irqd = irq_domain_get_irq_data(gc->irq.parent_domain, irq);
	if (!irqd)
		return -EINVAL;
	*parent = irqd_to_hwirq(irqd);
	*parent_type = IRQ_TYPE_LEVEL_HIGH;
	return 0;
}

static int thunderx_gpio_populate_parent_alloc_info(struct gpio_chip *chip,
						    union gpio_irq_fwspec *gfwspec,
						    unsigned int parent_hwirq,
						    unsigned int parent_type)
{
	msi_alloc_info_t *info = &gfwspec->msiinfo;

	info->hwirq = parent_hwirq;
	return 0;
}

static int thunderx_gpio_probe(struct pci_dev *pdev,
			       const struct pci_device_id *id)
{
	void __iomem * const *tbl;
	struct device *dev = &pdev->dev;
	struct thunderx_gpio *txgpio;
	struct gpio_chip *chip;
	struct gpio_irq_chip *girq;
	int ngpio, i;
	int err = 0;

	txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL);
	if (!txgpio)
		return -ENOMEM;

	raw_spin_lock_init(&txgpio->lock);
	chip = &txgpio->chip;

	pci_set_drvdata(pdev, txgpio);

	err = pcim_enable_device(pdev);
	if (err) {
		dev_err(dev, "Failed to enable PCI device: err %d\n", err);
		goto out;
	}

	err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME);
	if (err) {
		dev_err(dev, "Failed to iomap PCI device: err %d\n", err);
		goto out;
	}

	tbl = pcim_iomap_table(pdev);
	txgpio->register_base = tbl[0];
	if (!txgpio->register_base) {
		dev_err(dev, "Cannot map PCI resource\n");
		err = -ENOMEM;
		goto out;
	}

	if (pdev->subsystem_device == 0xa10a) {
		/* CN88XX has no GPIO_CONST register*/
		ngpio = 50;
		txgpio->base_msi = 48;
	} else {
		u64 c = readq(txgpio->register_base + GPIO_CONST);

		ngpio = c & GPIO_CONST_GPIOS_MASK;
		txgpio->base_msi = (c >> 8) & 0xff;
	}

	txgpio->msix_entries = devm_kcalloc(dev,
					    ngpio, sizeof(struct msix_entry),
					    GFP_KERNEL);
	if (!txgpio->msix_entries) {
		err = -ENOMEM;
		goto out;
	}

	txgpio->line_entries = devm_kcalloc(dev,
					    ngpio,
					    sizeof(struct thunderx_line),
					    GFP_KERNEL);
	if (!txgpio->line_entries) {
		err = -ENOMEM;
		goto out;
	}

	for (i = 0; i < ngpio; i++) {
		u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));

		txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i);
		txgpio->line_entries[i].line = i;
		txgpio->line_entries[i].txgpio = txgpio;
		/*
		 * If something has already programmed the pin, use
		 * the existing glitch filter settings, otherwise go
		 * to 400nS.
		 */
		txgpio->line_entries[i].fil_bits = bit_cfg ?
			(bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS;

		if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD))
			set_bit(i, txgpio->od_mask);
		if (bit_cfg & GPIO_BIT_CFG_PIN_XOR)
			set_bit(i, txgpio->invert_mask);
	}


	/* Enable all MSI-X for interrupts on all possible lines. */
	err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio);
	if (err < 0)
		goto out;

	chip->label = KBUILD_MODNAME;
	chip->parent = dev;
	chip->owner = THIS_MODULE;
	chip->request = thunderx_gpio_request;
	chip->base = -1; /* System allocated */
	chip->can_sleep = false;
	chip->ngpio = ngpio;
	chip->get_direction = thunderx_gpio_get_direction;
	chip->direction_input = thunderx_gpio_dir_in;
	chip->get = thunderx_gpio_get;
	chip->direction_output = thunderx_gpio_dir_out;
	chip->set = thunderx_gpio_set;
	chip->set_multiple = thunderx_gpio_set_multiple;
	chip->set_config = thunderx_gpio_set_config;
	girq = &chip->irq;
	girq->chip = &thunderx_gpio_irq_chip;
	girq->fwnode = of_node_to_fwnode(dev->of_node);
	girq->parent_domain =
		irq_get_irq_data(txgpio->msix_entries[0].vector)->domain;
	girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq;
	girq->populate_parent_alloc_arg = thunderx_gpio_populate_parent_alloc_info;
	girq->handler = handle_bad_irq;
	girq->default_type = IRQ_TYPE_NONE;

	err = devm_gpiochip_add_data(dev, chip, txgpio);
	if (err)
		goto out;

	/* Push on irq_data and the domain for each line. */
	for (i = 0; i < ngpio; i++) {
		struct irq_fwspec fwspec;

		fwspec.fwnode = of_node_to_fwnode(dev->of_node);
		fwspec.param_count = 2;
		fwspec.param[0] = i;
		fwspec.param[1] = IRQ_TYPE_NONE;
		err = irq_domain_push_irq(girq->domain,
					  txgpio->msix_entries[i].vector,
					  &fwspec);
		if (err < 0)
			dev_err(dev, "irq_domain_push_irq: %d\n", err);
	}

	dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n",
		 ngpio, chip->base);
	return 0;
out:
	pci_set_drvdata(pdev, NULL);
	return err;
}

static void thunderx_gpio_remove(struct pci_dev *pdev)
{
	int i;
	struct thunderx_gpio *txgpio = pci_get_drvdata(pdev);

	for (i = 0; i < txgpio->chip.ngpio; i++)
		irq_domain_pop_irq(txgpio->chip.irq.domain,
				   txgpio->msix_entries[i].vector);

	irq_domain_remove(txgpio->chip.irq.domain);

	pci_set_drvdata(pdev, NULL);
}

static const struct pci_device_id thunderx_gpio_id_table[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) },
	{ 0, }	/* end of table */
};

MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table);

static struct pci_driver thunderx_gpio_driver = {
	.name = KBUILD_MODNAME,
	.id_table = thunderx_gpio_id_table,
	.probe = thunderx_gpio_probe,
	.remove = thunderx_gpio_remove,
};

module_pci_driver(thunderx_gpio_driver);

MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
5a2a3002 DD	1	/*
	2	* This file is subject to the terms and conditions of the GNU General Public
	3	* License. See the file "COPYING" in the main directory of this archive
	4	* for more details.
	5	*
	6	* Copyright (C) 2016, 2017 Cavium Inc.
	7	*/
	8
	9	#include <linux/bitops.h>
	10	#include <linux/gpio/driver.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/io.h>
	13	#include <linux/irq.h>
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/pci.h>
	17	#include <linux/spinlock.h>
5a2a3002 DD	18
	19	#define GPIO_RX_DAT 0x0
	20	#define GPIO_TX_SET 0x8
	21	#define GPIO_TX_CLR 0x10
	22	#define GPIO_CONST 0x90
	23	#define GPIO_CONST_GPIOS_MASK 0xff
	24	#define GPIO_BIT_CFG 0x400
	25	#define GPIO_BIT_CFG_TX_OE BIT(0)
	26	#define GPIO_BIT_CFG_PIN_XOR BIT(1)
	27	#define GPIO_BIT_CFG_INT_EN BIT(2)
	28	#define GPIO_BIT_CFG_INT_TYPE BIT(3)
	29	#define GPIO_BIT_CFG_FIL_MASK GENMASK(11, 4)
	30	#define GPIO_BIT_CFG_FIL_CNT_SHIFT 4
	31	#define GPIO_BIT_CFG_FIL_SEL_SHIFT 8
	32	#define GPIO_BIT_CFG_TX_OD BIT(12)
	33	#define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK(25, 16)
	34	#define GPIO_INTR 0x800
	35	#define GPIO_INTR_INTR BIT(0)
	36	#define GPIO_INTR_INTR_W1S BIT(1)
	37	#define GPIO_INTR_ENA_W1C BIT(2)
	38	#define GPIO_INTR_ENA_W1S BIT(3)
	39	#define GPIO_2ND_BANK 0x1400
	40
	41	#define GLITCH_FILTER_400NS ((4u << GPIO_BIT_CFG_FIL_SEL_SHIFT) \| \
	42	(9u << GPIO_BIT_CFG_FIL_CNT_SHIFT))
	43
	44	struct thunderx_gpio;
	45
	46	struct thunderx_line {
	47	struct thunderx_gpio *txgpio;
	48	unsigned int line;
	49	unsigned int fil_bits;
	50	};
	51
	52	struct thunderx_gpio {
	53	struct gpio_chip chip;
	54	u8 __iomem *register_base;
5a2a3002 DD	55	struct msix_entry msix_entries; / per line MSI-X */
	56	struct thunderx_line line_entries; / per line irq info */
	57	raw_spinlock_t lock;
	58	unsigned long invert_mask[2];
	59	unsigned long od_mask[2];
	60	int base_msi;
	61	};
	62
	63	static unsigned int bit_cfg_reg(unsigned int line)
	64	{
	65	return 8 * line + GPIO_BIT_CFG;
	66	}
	67
	68	static unsigned int intr_reg(unsigned int line)
	69	{
	70	return 8 * line + GPIO_INTR;
	71	}
	72
	73	static bool thunderx_gpio_is_gpio_nowarn(struct thunderx_gpio *txgpio,
	74	unsigned int line)
	75	{
	76	u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
	77
	78	return (bit_cfg & GPIO_BIT_CFG_PIN_SEL_MASK) == 0;
	79	}
	80
	81	/*
	82	* Check (and WARN) that the pin is available for GPIO. We will not
	83	* allow modification of the state of non-GPIO pins from this driver.
	84	*/
	85	static bool thunderx_gpio_is_gpio(struct thunderx_gpio *txgpio,
	86	unsigned int line)
	87	{
	88	bool rv = thunderx_gpio_is_gpio_nowarn(txgpio, line);
	89
	90	WARN_RATELIMIT(!rv, "Pin %d not available for GPIO\n", line);
	91
	92	return rv;
	93	}
	94
	95	static int thunderx_gpio_request(struct gpio_chip *chip, unsigned int line)
	96	{
	97	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
	98
	99	return thunderx_gpio_is_gpio(txgpio, line) ? 0 : -EIO;
	100	}
	101
	102	static int thunderx_gpio_dir_in(struct gpio_chip *chip, unsigned int line)
	103	{
	104	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
	105
	106	if (!thunderx_gpio_is_gpio(txgpio, line))
	107	return -EIO;
	108
	109	raw_spin_lock(&txgpio->lock);
	110	clear_bit(line, txgpio->invert_mask);
	111	clear_bit(line, txgpio->od_mask);
	112	writeq(txgpio->line_entries[line].fil_bits,
	113	txgpio->register_base + bit_cfg_reg(line));
	114	raw_spin_unlock(&txgpio->lock);
	115	return 0;
	116	}
	117
	118	static void thunderx_gpio_set(struct gpio_chip *chip, unsigned int line,
119	int value)
120	{
121	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
122	int bank = line / 64;
123	int bank_bit = line % 64;
124
125	void __iomem *reg = txgpio->register_base +
126	(bank * GPIO_2ND_BANK) + (value ? GPIO_TX_SET : GPIO_TX_CLR);
127
128	writeq(BIT_ULL(bank_bit), reg);
129	}
130
131	static int thunderx_gpio_dir_out(struct gpio_chip *chip, unsigned int line,
132	int value)
133	{
134	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
135	u64 bit_cfg = txgpio->line_entries[line].fil_bits \| GPIO_BIT_CFG_TX_OE;
136
137	if (!thunderx_gpio_is_gpio(txgpio, line))
138	return -EIO;
139
140	raw_spin_lock(&txgpio->lock);
141
142	thunderx_gpio_set(chip, line, value);
143
144	if (test_bit(line, txgpio->invert_mask))
145	bit_cfg \|= GPIO_BIT_CFG_PIN_XOR;
146
147	if (test_bit(line, txgpio->od_mask))
148	bit_cfg \|= GPIO_BIT_CFG_TX_OD;
149
150	writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
151
152	raw_spin_unlock(&txgpio->lock);
153	return 0;
154	}
155
156	static int thunderx_gpio_get_direction(struct gpio_chip *chip, unsigned int line)
157	{
158	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
159	u64 bit_cfg;
160
161	if (!thunderx_gpio_is_gpio_nowarn(txgpio, line))
162	/*
163	* Say it is input for now to avoid WARNing on
164	* gpiochip_add_data(). We will WARN if someone
165	* requests it or tries to use it.
166	*/
167	return 1;
168
169	bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
170
e42615ec MV	171	if (bit_cfg & GPIO_BIT_CFG_TX_OE)
	172	return GPIO_LINE_DIRECTION_OUT;
	173
	174	return GPIO_LINE_DIRECTION_IN;
5a2a3002 DD	175	}
	176
	177	static int thunderx_gpio_set_config(struct gpio_chip *chip,
	178	unsigned int line,
	179	unsigned long cfg)
	180	{
	181	bool orig_invert, orig_od, orig_dat, new_invert, new_od;
	182	u32 arg, sel;
	183	u64 bit_cfg;
	184	int bank = line / 64;
	185	int bank_bit = line % 64;
	186	int ret = -ENOTSUPP;
	187	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
	188	void __iomem reg = txgpio->register_base + (bank GPIO_2ND_BANK) + GPIO_TX_SET;
	189
	190	if (!thunderx_gpio_is_gpio(txgpio, line))
	191	return -EIO;
	192
	193	raw_spin_lock(&txgpio->lock);
	194	orig_invert = test_bit(line, txgpio->invert_mask);
	195	new_invert = orig_invert;
	196	orig_od = test_bit(line, txgpio->od_mask);
	197	new_od = orig_od;
	198	orig_dat = ((readq(reg) >> bank_bit) & 1) ^ orig_invert;
	199	bit_cfg = readq(txgpio->register_base + bit_cfg_reg(line));
	200	switch (pinconf_to_config_param(cfg)) {
	201	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
	202	/*
	203	* Weird, setting open-drain mode causes signal
	204	* inversion. Note this so we can compensate in the
	205	* dir_out function.
	206	*/
	207	set_bit(line, txgpio->invert_mask);
	208	new_invert = true;
	209	set_bit(line, txgpio->od_mask);
	210	new_od = true;
	211	ret = 0;
	212	break;
	213	case PIN_CONFIG_DRIVE_PUSH_PULL:
	214	clear_bit(line, txgpio->invert_mask);
	215	new_invert = false;
	216	clear_bit(line, txgpio->od_mask);
	217	new_od = false;
	218	ret = 0;
	219	break;
	220	case PIN_CONFIG_INPUT_DEBOUNCE:
	221	arg = pinconf_to_config_argument(cfg);
	222	if (arg > 1228) { /* 15 * 2^15 * 2.5nS maximum */
	223	ret = -EINVAL;
	224	break;
	225	}
	226	arg = 400; / scale to 2.5nS clocks. */
	227	sel = 0;
	228	while (arg > 15) {
	229	sel++;
	230	arg++; /* always round up */
	231	arg >>= 1;
	232	}
	233	txgpio->line_entries[line].fil_bits =
	234	(sel << GPIO_BIT_CFG_FIL_SEL_SHIFT) \|
	235	(arg << GPIO_BIT_CFG_FIL_CNT_SHIFT);
	236	bit_cfg &= ~GPIO_BIT_CFG_FIL_MASK;
	237	bit_cfg \|= txgpio->line_entries[line].fil_bits;
	238	writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(line));
239	ret = 0;
240	break;
241	default:
242	break;
243	}
244	raw_spin_unlock(&txgpio->lock);
245
246	/*
247	* If currently output and OPEN_DRAIN changed, install the new
248	* settings
249	*/
250	if ((new_invert != orig_invert \|\| new_od != orig_od) &&
251	(bit_cfg & GPIO_BIT_CFG_TX_OE))
252	ret = thunderx_gpio_dir_out(chip, line, orig_dat ^ new_invert);
253
254	return ret;
255	}
256
257	static int thunderx_gpio_get(struct gpio_chip *chip, unsigned int line)
258	{
259	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
260	int bank = line / 64;
261	int bank_bit = line % 64;
262	u64 read_bits = readq(txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_RX_DAT);
263	u64 masked_bits = read_bits & BIT_ULL(bank_bit);
264
265	if (test_bit(line, txgpio->invert_mask))
266	return masked_bits == 0;
267	else
268	return masked_bits != 0;
269	}
270
271	static void thunderx_gpio_set_multiple(struct gpio_chip *chip,
272	unsigned long *mask,
273	unsigned long *bits)
274	{
275	int bank;
276	u64 set_bits, clear_bits;
277	struct thunderx_gpio *txgpio = gpiochip_get_data(chip);
278
279	for (bank = 0; bank <= chip->ngpio / 64; bank++) {
280	set_bits = bits[bank] & mask[bank];
281	clear_bits = ~bits[bank] & mask[bank];
282	writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET);
283	writeq(clear_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_CLR);
284	}
285	}
286
7a9f4460	287	static void thunderx_gpio_irq_ack(struct irq_data *d)
5a2a3002	288	{
7a9f4460 KH	289	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
7a9f4460 KH	290	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
5a2a3002 DD	291
5a2a3002 DD	292	writeq(GPIO_INTR_INTR,
7a9f4460	293	txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
5a2a3002 DD	294	}
5a2a3002 DD	295
7a9f4460	296	static void thunderx_gpio_irq_mask(struct irq_data *d)
5a2a3002	297	{
7a9f4460 KH	298	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
7a9f4460 KH	299	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
5a2a3002 DD	300
5a2a3002 DD	301	writeq(GPIO_INTR_ENA_W1C,
7a9f4460	302	txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
5a2a3002 DD	303	}
5a2a3002 DD	304
7a9f4460	305	static void thunderx_gpio_irq_mask_ack(struct irq_data *d)
5a2a3002	306	{
7a9f4460 KH	307	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
7a9f4460 KH	308	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
5a2a3002 DD	309
5a2a3002 DD	310	writeq(GPIO_INTR_ENA_W1C \| GPIO_INTR_INTR,
7a9f4460	311	txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
5a2a3002 DD	312	}
5a2a3002 DD	313
7a9f4460	314	static void thunderx_gpio_irq_unmask(struct irq_data *d)
5a2a3002	315	{
7a9f4460 KH	316	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
7a9f4460 KH	317	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
5a2a3002 DD	318
5a2a3002 DD	319	writeq(GPIO_INTR_ENA_W1S,
7a9f4460	320	txgpio->register_base + intr_reg(irqd_to_hwirq(d)));
5a2a3002 DD	321	}
5a2a3002 DD	322
7a9f4460	323	static int thunderx_gpio_irq_set_type(struct irq_data *d,
5a2a3002 DD	324	unsigned int flow_type)
5a2a3002 DD	325	{
7a9f4460 KH	326	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	327	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
	328	struct thunderx_line *txline =
	329	&txgpio->line_entries[irqd_to_hwirq(d)];
5a2a3002 DD	330	u64 bit_cfg;
5a2a3002 DD	331
7a9f4460	332	irqd_set_trigger_type(d, flow_type);
5a2a3002 DD	333
	334	bit_cfg = txline->fil_bits \| GPIO_BIT_CFG_INT_EN;
	335
	336	if (flow_type & IRQ_TYPE_EDGE_BOTH) {
7a9f4460	337	irq_set_handler_locked(d, handle_fasteoi_ack_irq);
5a2a3002 DD	338	bit_cfg \|= GPIO_BIT_CFG_INT_TYPE;
5a2a3002 DD	339	} else {
7a9f4460	340	irq_set_handler_locked(d, handle_fasteoi_mask_irq);
5a2a3002 DD	341	}
	342
	343	raw_spin_lock(&txgpio->lock);
	344	if (flow_type & (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_LEVEL_LOW)) {
	345	bit_cfg \|= GPIO_BIT_CFG_PIN_XOR;
	346	set_bit(txline->line, txgpio->invert_mask);
	347	} else {
	348	clear_bit(txline->line, txgpio->invert_mask);
	349	}
	350	clear_bit(txline->line, txgpio->od_mask);
	351	writeq(bit_cfg, txgpio->register_base + bit_cfg_reg(txline->line));
	352	raw_spin_unlock(&txgpio->lock);
	353
	354	return IRQ_SET_MASK_OK;
	355	}
	356
	357	static void thunderx_gpio_irq_enable(struct irq_data *data)
	358	{
	359	irq_chip_enable_parent(data);
	360	thunderx_gpio_irq_unmask(data);
	361	}
	362
	363	static void thunderx_gpio_irq_disable(struct irq_data *data)
	364	{
	365	thunderx_gpio_irq_mask(data);
	366	irq_chip_disable_parent(data);
	367	}
	368
5a2a3002 DD	369	/*
	370	* Interrupts are chained from underlying MSI-X vectors. We have
	371	* these irq_chip functions to be able to handle level triggering
	372	* semantics and other acknowledgment tasks associated with the GPIO
	373	* mechanism.
	374	*/
	375	static struct irq_chip thunderx_gpio_irq_chip = {
	376	.name = "GPIO",
	377	.irq_enable = thunderx_gpio_irq_enable,
	378	.irq_disable = thunderx_gpio_irq_disable,
	379	.irq_ack = thunderx_gpio_irq_ack,
	380	.irq_mask = thunderx_gpio_irq_mask,
	381	.irq_mask_ack = thunderx_gpio_irq_mask_ack,
	382	.irq_unmask = thunderx_gpio_irq_unmask,
	383	.irq_eoi = irq_chip_eoi_parent,
	384	.irq_set_affinity = irq_chip_set_affinity_parent,
5a2a3002 DD	385	.irq_set_type = thunderx_gpio_irq_set_type,
	386
	387	.flags = IRQCHIP_SET_TYPE_MASKED
	388	};
	389
7a9f4460 KH	390	static int thunderx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
	391	unsigned int child,
	392	unsigned int child_type,
	393	unsigned int *parent,
	394	unsigned int *parent_type)
5a2a3002	395	{
7a9f4460 KH	396	struct thunderx_gpio *txgpio = gpiochip_get_data(gc);
	397	struct irq_data *irqd;
	398	unsigned int irq;
a564ac35	399
7a9f4460 KH	400	irq = txgpio->msix_entries[child].vector;
	401	irqd = irq_domain_get_irq_data(gc->irq.parent_domain, irq);
	402	if (!irqd)
a564ac35	403	return -EINVAL;
7a9f4460 KH	404	*parent = irqd_to_hwirq(irqd);
7a9f4460 KH	405	*parent_type = IRQ_TYPE_LEVEL_HIGH;
a7fc89f9	406	return 0;
5a2a3002 DD	407	}
5a2a3002 DD	408
91a29af4 MZ	409	static int thunderx_gpio_populate_parent_alloc_info(struct gpio_chip *chip,
	410	union gpio_irq_fwspec *gfwspec,
	411	unsigned int parent_hwirq,
	412	unsigned int parent_type)
a564ac35	413	{
91a29af4	414	msi_alloc_info_t *info = &gfwspec->msiinfo;
a564ac35	415
7a9f4460	416	info->hwirq = parent_hwirq;
91a29af4	417	return 0;
a564ac35 KH	418	}
a564ac35 KH	419
5a2a3002 DD	420	static int thunderx_gpio_probe(struct pci_dev *pdev,
	421	const struct pci_device_id *id)
	422	{
	423	void __iomem * const *tbl;
	424	struct device *dev = &pdev->dev;
	425	struct thunderx_gpio *txgpio;
	426	struct gpio_chip *chip;
7a9f4460	427	struct gpio_irq_chip *girq;
5a2a3002 DD	428	int ngpio, i;
	429	int err = 0;
	430
	431	txgpio = devm_kzalloc(dev, sizeof(*txgpio), GFP_KERNEL);
	432	if (!txgpio)
	433	return -ENOMEM;
	434
	435	raw_spin_lock_init(&txgpio->lock);
	436	chip = &txgpio->chip;
	437
	438	pci_set_drvdata(pdev, txgpio);
	439
	440	err = pcim_enable_device(pdev);
	441	if (err) {
	442	dev_err(dev, "Failed to enable PCI device: err %d\n", err);
	443	goto out;
	444	}
	445
	446	err = pcim_iomap_regions(pdev, 1 << 0, KBUILD_MODNAME);
	447	if (err) {
	448	dev_err(dev, "Failed to iomap PCI device: err %d\n", err);
	449	goto out;
	450	}
	451
	452	tbl = pcim_iomap_table(pdev);
	453	txgpio->register_base = tbl[0];
	454	if (!txgpio->register_base) {
	455	dev_err(dev, "Cannot map PCI resource\n");
	456	err = -ENOMEM;
	457	goto out;
	458	}
	459
	460	if (pdev->subsystem_device == 0xa10a) {
	461	/* CN88XX has no GPIO_CONST register*/
	462	ngpio = 50;
	463	txgpio->base_msi = 48;
	464	} else {
	465	u64 c = readq(txgpio->register_base + GPIO_CONST);
	466
	467	ngpio = c & GPIO_CONST_GPIOS_MASK;
	468	txgpio->base_msi = (c >> 8) & 0xff;
	469	}
	470
a86854d0	471	txgpio->msix_entries = devm_kcalloc(dev,
7a9f4460 KH	472	ngpio, sizeof(struct msix_entry),
7a9f4460 KH	473	GFP_KERNEL);
5a2a3002 DD	474	if (!txgpio->msix_entries) {
	475	err = -ENOMEM;
	476	goto out;
	477	}
	478
a86854d0 KC	479	txgpio->line_entries = devm_kcalloc(dev,
	480	ngpio,
	481	sizeof(struct thunderx_line),
5a2a3002 DD	482	GFP_KERNEL);
	483	if (!txgpio->line_entries) {
	484	err = -ENOMEM;
	485	goto out;
	486	}
	487
	488	for (i = 0; i < ngpio; i++) {
	489	u64 bit_cfg = readq(txgpio->register_base + bit_cfg_reg(i));
	490
	491	txgpio->msix_entries[i].entry = txgpio->base_msi + (2 * i);
	492	txgpio->line_entries[i].line = i;
	493	txgpio->line_entries[i].txgpio = txgpio;
	494	/*
	495	* If something has already programmed the pin, use
	496	* the existing glitch filter settings, otherwise go
	497	* to 400nS.
	498	*/
	499	txgpio->line_entries[i].fil_bits = bit_cfg ?
	500	(bit_cfg & GPIO_BIT_CFG_FIL_MASK) : GLITCH_FILTER_400NS;
	501
	502	if ((bit_cfg & GPIO_BIT_CFG_TX_OE) && (bit_cfg & GPIO_BIT_CFG_TX_OD))
	503	set_bit(i, txgpio->od_mask);
	504	if (bit_cfg & GPIO_BIT_CFG_PIN_XOR)
	505	set_bit(i, txgpio->invert_mask);
	506	}
	507
	508
	509	/* Enable all MSI-X for interrupts on all possible lines. */
	510	err = pci_enable_msix_range(pdev, txgpio->msix_entries, ngpio, ngpio);
	511	if (err < 0)
	512	goto out;
	513
5a2a3002 DD	514	chip->label = KBUILD_MODNAME;
	515	chip->parent = dev;
	516	chip->owner = THIS_MODULE;
	517	chip->request = thunderx_gpio_request;
	518	chip->base = -1; /* System allocated */
	519	chip->can_sleep = false;
	520	chip->ngpio = ngpio;
	521	chip->get_direction = thunderx_gpio_get_direction;
	522	chip->direction_input = thunderx_gpio_dir_in;
	523	chip->get = thunderx_gpio_get;
	524	chip->direction_output = thunderx_gpio_dir_out;
	525	chip->set = thunderx_gpio_set;
	526	chip->set_multiple = thunderx_gpio_set_multiple;
	527	chip->set_config = thunderx_gpio_set_config;
7a9f4460 KH	528	girq = &chip->irq;
	529	girq->chip = &thunderx_gpio_irq_chip;
	530	girq->fwnode = of_node_to_fwnode(dev->of_node);
	531	girq->parent_domain =
	532	irq_get_irq_data(txgpio->msix_entries[0].vector)->domain;
	533	girq->child_to_parent_hwirq = thunderx_gpio_child_to_parent_hwirq;
	534	girq->populate_parent_alloc_arg = thunderx_gpio_populate_parent_alloc_info;
	535	girq->handler = handle_bad_irq;
	536	girq->default_type = IRQ_TYPE_NONE;
	537
5a2a3002 DD	538	err = devm_gpiochip_add_data(dev, chip, txgpio);
	539	if (err)
	540	goto out;
	541
7a9f4460 KH	542	/* Push on irq_data and the domain for each line. */
	543	for (i = 0; i < ngpio; i++) {
	544	struct irq_fwspec fwspec;
	545
	546	fwspec.fwnode = of_node_to_fwnode(dev->of_node);
	547	fwspec.param_count = 2;
	548	fwspec.param[0] = i;
	549	fwspec.param[1] = IRQ_TYPE_NONE;
	550	err = irq_domain_push_irq(girq->domain,
	551	txgpio->msix_entries[i].vector,
	552	&fwspec);
	553	if (err < 0)
	554	dev_err(dev, "irq_domain_push_irq: %d\n", err);
	555	}
	556
5a2a3002 DD	557	dev_info(dev, "ThunderX GPIO: %d lines with base %d.\n",
	558	ngpio, chip->base);
	559	return 0;
	560	out:
	561	pci_set_drvdata(pdev, NULL);
	562	return err;
	563	}
	564
	565	static void thunderx_gpio_remove(struct pci_dev *pdev)
	566	{
	567	int i;
	568	struct thunderx_gpio *txgpio = pci_get_drvdata(pdev);
	569
	570	for (i = 0; i < txgpio->chip.ngpio; i++)
7a9f4460	571	irq_domain_pop_irq(txgpio->chip.irq.domain,
5a2a3002 DD	572	txgpio->msix_entries[i].vector);
5a2a3002 DD	573
7a9f4460	574	irq_domain_remove(txgpio->chip.irq.domain);
5a2a3002 DD	575
	576	pci_set_drvdata(pdev, NULL);
	577	}
	578
	579	static const struct pci_device_id thunderx_gpio_id_table[] = {
	580	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA00A) },
	581	{ 0, } /* end of table */
	582	};
	583
	584	MODULE_DEVICE_TABLE(pci, thunderx_gpio_id_table);
	585
	586	static struct pci_driver thunderx_gpio_driver = {
	587	.name = KBUILD_MODNAME,
	588	.id_table = thunderx_gpio_id_table,
	589	.probe = thunderx_gpio_probe,
	590	.remove = thunderx_gpio_remove,
	591	};
	592
	593	module_pci_driver(thunderx_gpio_driver);
	594
	595	MODULE_DESCRIPTION("Cavium Inc. ThunderX/OCTEON-TX GPIO Driver");
	596	MODULE_LICENSE("GPL");