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ac1dc6b2 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
5b2b135a TR |
2 | /* |
3 | * Copyright (c) 2016-2017 NVIDIA Corporation | |
4 | * | |
5 | * Author: Thierry Reding <treding@nvidia.com> | |
5b2b135a TR |
6 | */ |
7 | ||
8 | #include <linux/gpio/driver.h> | |
9 | #include <linux/interrupt.h> | |
10 | #include <linux/irq.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of_device.h> | |
13 | #include <linux/platform_device.h> | |
14 | ||
15 | #include <dt-bindings/gpio/tegra186-gpio.h> | |
bac5c3b8 | 16 | #include <dt-bindings/gpio/tegra194-gpio.h> |
5b2b135a TR |
17 | |
18 | #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 | |
19 | #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) | |
20 | #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) | |
21 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) | |
22 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) | |
23 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) | |
24 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) | |
25 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) | |
26 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) | |
27 | #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) | |
28 | ||
29 | #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 | |
30 | #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) | |
31 | ||
32 | #define TEGRA186_GPIO_INPUT 0x08 | |
33 | #define TEGRA186_GPIO_INPUT_HIGH BIT(0) | |
34 | ||
35 | #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c | |
36 | #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) | |
37 | ||
38 | #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 | |
39 | #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) | |
40 | ||
41 | #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 | |
42 | ||
43 | #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) | |
44 | ||
45 | struct tegra_gpio_port { | |
46 | const char *name; | |
47 | unsigned int offset; | |
48 | unsigned int pins; | |
49 | unsigned int irq; | |
50 | }; | |
51 | ||
52 | struct tegra_gpio_soc { | |
53 | const struct tegra_gpio_port *ports; | |
54 | unsigned int num_ports; | |
55 | const char *name; | |
56 | }; | |
57 | ||
58 | struct tegra_gpio { | |
59 | struct gpio_chip gpio; | |
60 | struct irq_chip intc; | |
61 | unsigned int num_irq; | |
62 | unsigned int *irq; | |
63 | ||
64 | const struct tegra_gpio_soc *soc; | |
65 | ||
66 | void __iomem *base; | |
67 | }; | |
68 | ||
69 | static const struct tegra_gpio_port * | |
70 | tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) | |
71 | { | |
72 | unsigned int start = 0, i; | |
73 | ||
74 | for (i = 0; i < gpio->soc->num_ports; i++) { | |
75 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; | |
76 | ||
77 | if (*pin >= start && *pin < start + port->pins) { | |
78 | *pin -= start; | |
79 | return port; | |
80 | } | |
81 | ||
82 | start += port->pins; | |
83 | } | |
84 | ||
85 | return NULL; | |
86 | } | |
87 | ||
88 | static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, | |
89 | unsigned int pin) | |
90 | { | |
91 | const struct tegra_gpio_port *port; | |
92 | ||
93 | port = tegra186_gpio_get_port(gpio, &pin); | |
94 | if (!port) | |
95 | return NULL; | |
96 | ||
97 | return gpio->base + port->offset + pin * 0x20; | |
98 | } | |
99 | ||
100 | static int tegra186_gpio_get_direction(struct gpio_chip *chip, | |
101 | unsigned int offset) | |
102 | { | |
103 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
104 | void __iomem *base; | |
105 | u32 value; | |
106 | ||
107 | base = tegra186_gpio_get_base(gpio, offset); | |
108 | if (WARN_ON(base == NULL)) | |
109 | return -ENODEV; | |
110 | ||
111 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
112 | if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) | |
113 | return 0; | |
114 | ||
115 | return 1; | |
116 | } | |
117 | ||
118 | static int tegra186_gpio_direction_input(struct gpio_chip *chip, | |
119 | unsigned int offset) | |
120 | { | |
121 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
122 | void __iomem *base; | |
123 | u32 value; | |
124 | ||
125 | base = tegra186_gpio_get_base(gpio, offset); | |
126 | if (WARN_ON(base == NULL)) | |
127 | return -ENODEV; | |
128 | ||
129 | value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); | |
130 | value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; | |
131 | writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); | |
132 | ||
133 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
134 | value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; | |
135 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; | |
136 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
141 | static int tegra186_gpio_direction_output(struct gpio_chip *chip, | |
142 | unsigned int offset, int level) | |
143 | { | |
144 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
145 | void __iomem *base; | |
146 | u32 value; | |
147 | ||
148 | /* configure output level first */ | |
149 | chip->set(chip, offset, level); | |
150 | ||
151 | base = tegra186_gpio_get_base(gpio, offset); | |
152 | if (WARN_ON(base == NULL)) | |
153 | return -EINVAL; | |
154 | ||
155 | /* set the direction */ | |
156 | value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); | |
157 | value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; | |
158 | writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); | |
159 | ||
160 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
161 | value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; | |
162 | value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; | |
163 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
164 | ||
165 | return 0; | |
166 | } | |
167 | ||
168 | static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) | |
169 | { | |
170 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
171 | void __iomem *base; | |
172 | u32 value; | |
173 | ||
174 | base = tegra186_gpio_get_base(gpio, offset); | |
175 | if (WARN_ON(base == NULL)) | |
176 | return -ENODEV; | |
177 | ||
178 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
179 | if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) | |
180 | value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); | |
181 | else | |
182 | value = readl(base + TEGRA186_GPIO_INPUT); | |
183 | ||
184 | return value & BIT(0); | |
185 | } | |
186 | ||
187 | static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, | |
188 | int level) | |
189 | { | |
190 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
191 | void __iomem *base; | |
192 | u32 value; | |
193 | ||
194 | base = tegra186_gpio_get_base(gpio, offset); | |
195 | if (WARN_ON(base == NULL)) | |
196 | return; | |
197 | ||
198 | value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); | |
199 | if (level == 0) | |
200 | value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; | |
201 | else | |
202 | value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; | |
203 | ||
204 | writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); | |
205 | } | |
206 | ||
207 | static int tegra186_gpio_of_xlate(struct gpio_chip *chip, | |
208 | const struct of_phandle_args *spec, | |
209 | u32 *flags) | |
210 | { | |
211 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
212 | unsigned int port, pin, i, offset = 0; | |
213 | ||
214 | if (WARN_ON(chip->of_gpio_n_cells < 2)) | |
215 | return -EINVAL; | |
216 | ||
217 | if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) | |
218 | return -EINVAL; | |
219 | ||
220 | port = spec->args[0] / 8; | |
221 | pin = spec->args[0] % 8; | |
222 | ||
223 | if (port >= gpio->soc->num_ports) { | |
224 | dev_err(chip->parent, "invalid port number: %u\n", port); | |
225 | return -EINVAL; | |
226 | } | |
227 | ||
228 | for (i = 0; i < port; i++) | |
229 | offset += gpio->soc->ports[i].pins; | |
230 | ||
231 | if (flags) | |
232 | *flags = spec->args[1]; | |
233 | ||
234 | return offset + pin; | |
235 | } | |
236 | ||
237 | static void tegra186_irq_ack(struct irq_data *data) | |
238 | { | |
239 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); | |
240 | void __iomem *base; | |
241 | ||
242 | base = tegra186_gpio_get_base(gpio, data->hwirq); | |
243 | if (WARN_ON(base == NULL)) | |
244 | return; | |
245 | ||
246 | writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); | |
247 | } | |
248 | ||
249 | static void tegra186_irq_mask(struct irq_data *data) | |
250 | { | |
251 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); | |
252 | void __iomem *base; | |
253 | u32 value; | |
254 | ||
255 | base = tegra186_gpio_get_base(gpio, data->hwirq); | |
256 | if (WARN_ON(base == NULL)) | |
257 | return; | |
258 | ||
259 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
260 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; | |
261 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
262 | } | |
263 | ||
264 | static void tegra186_irq_unmask(struct irq_data *data) | |
265 | { | |
266 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); | |
267 | void __iomem *base; | |
268 | u32 value; | |
269 | ||
270 | base = tegra186_gpio_get_base(gpio, data->hwirq); | |
271 | if (WARN_ON(base == NULL)) | |
272 | return; | |
273 | ||
274 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
275 | value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; | |
276 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
277 | } | |
278 | ||
3a2fa906 | 279 | static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) |
5b2b135a TR |
280 | { |
281 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); | |
282 | void __iomem *base; | |
283 | u32 value; | |
284 | ||
285 | base = tegra186_gpio_get_base(gpio, data->hwirq); | |
286 | if (WARN_ON(base == NULL)) | |
287 | return -ENODEV; | |
288 | ||
289 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
290 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; | |
291 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; | |
292 | ||
3a2fa906 | 293 | switch (type & IRQ_TYPE_SENSE_MASK) { |
5b2b135a TR |
294 | case IRQ_TYPE_NONE: |
295 | break; | |
296 | ||
297 | case IRQ_TYPE_EDGE_RISING: | |
298 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; | |
299 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; | |
300 | break; | |
301 | ||
302 | case IRQ_TYPE_EDGE_FALLING: | |
303 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; | |
304 | break; | |
305 | ||
306 | case IRQ_TYPE_EDGE_BOTH: | |
307 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; | |
308 | break; | |
309 | ||
310 | case IRQ_TYPE_LEVEL_HIGH: | |
311 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; | |
312 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; | |
313 | break; | |
314 | ||
315 | case IRQ_TYPE_LEVEL_LOW: | |
316 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; | |
317 | break; | |
318 | ||
319 | default: | |
320 | return -EINVAL; | |
321 | } | |
322 | ||
323 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
324 | ||
3a2fa906 | 325 | if ((type & IRQ_TYPE_EDGE_BOTH) == 0) |
5b2b135a TR |
326 | irq_set_handler_locked(data, handle_level_irq); |
327 | else | |
328 | irq_set_handler_locked(data, handle_edge_irq); | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
333 | static void tegra186_gpio_irq(struct irq_desc *desc) | |
334 | { | |
335 | struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); | |
336 | struct irq_domain *domain = gpio->gpio.irq.domain; | |
337 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
338 | unsigned int parent = irq_desc_get_irq(desc); | |
339 | unsigned int i, offset = 0; | |
340 | ||
341 | chained_irq_enter(chip, desc); | |
342 | ||
343 | for (i = 0; i < gpio->soc->num_ports; i++) { | |
344 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; | |
345 | void __iomem *base = gpio->base + port->offset; | |
346 | unsigned int pin, irq; | |
347 | unsigned long value; | |
348 | ||
349 | /* skip ports that are not associated with this controller */ | |
350 | if (parent != gpio->irq[port->irq]) | |
351 | goto skip; | |
352 | ||
353 | value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); | |
354 | ||
355 | for_each_set_bit(pin, &value, port->pins) { | |
356 | irq = irq_find_mapping(domain, offset + pin); | |
357 | if (WARN_ON(irq == 0)) | |
358 | continue; | |
359 | ||
360 | generic_handle_irq(irq); | |
361 | } | |
362 | ||
363 | skip: | |
364 | offset += port->pins; | |
365 | } | |
366 | ||
367 | chained_irq_exit(chip, desc); | |
368 | } | |
369 | ||
370 | static int tegra186_gpio_irq_domain_xlate(struct irq_domain *domain, | |
371 | struct device_node *np, | |
372 | const u32 *spec, unsigned int size, | |
373 | unsigned long *hwirq, | |
374 | unsigned int *type) | |
375 | { | |
376 | struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); | |
377 | unsigned int port, pin, i, offset = 0; | |
378 | ||
379 | if (size < 2) | |
380 | return -EINVAL; | |
381 | ||
382 | port = spec[0] / 8; | |
383 | pin = spec[0] % 8; | |
384 | ||
385 | if (port >= gpio->soc->num_ports) { | |
386 | dev_err(gpio->gpio.parent, "invalid port number: %u\n", port); | |
387 | return -EINVAL; | |
388 | } | |
389 | ||
390 | for (i = 0; i < port; i++) | |
391 | offset += gpio->soc->ports[i].pins; | |
392 | ||
393 | *type = spec[1] & IRQ_TYPE_SENSE_MASK; | |
394 | *hwirq = offset + pin; | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
399 | static const struct irq_domain_ops tegra186_gpio_irq_domain_ops = { | |
400 | .map = gpiochip_irq_map, | |
401 | .unmap = gpiochip_irq_unmap, | |
402 | .xlate = tegra186_gpio_irq_domain_xlate, | |
403 | }; | |
404 | ||
5b2b135a TR |
405 | static int tegra186_gpio_probe(struct platform_device *pdev) |
406 | { | |
407 | unsigned int i, j, offset; | |
408 | struct gpio_irq_chip *irq; | |
409 | struct tegra_gpio *gpio; | |
410 | struct resource *res; | |
411 | char **names; | |
412 | int err; | |
413 | ||
414 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); | |
415 | if (!gpio) | |
416 | return -ENOMEM; | |
417 | ||
418 | gpio->soc = of_device_get_match_data(&pdev->dev); | |
419 | ||
420 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio"); | |
421 | gpio->base = devm_ioremap_resource(&pdev->dev, res); | |
422 | if (IS_ERR(gpio->base)) | |
423 | return PTR_ERR(gpio->base); | |
424 | ||
425 | err = platform_irq_count(pdev); | |
426 | if (err < 0) | |
427 | return err; | |
428 | ||
429 | gpio->num_irq = err; | |
430 | ||
431 | gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), | |
432 | GFP_KERNEL); | |
433 | if (!gpio->irq) | |
434 | return -ENOMEM; | |
435 | ||
436 | for (i = 0; i < gpio->num_irq; i++) { | |
437 | err = platform_get_irq(pdev, i); | |
438 | if (err < 0) | |
439 | return err; | |
440 | ||
441 | gpio->irq[i] = err; | |
442 | } | |
443 | ||
444 | gpio->gpio.label = gpio->soc->name; | |
445 | gpio->gpio.parent = &pdev->dev; | |
446 | ||
447 | gpio->gpio.get_direction = tegra186_gpio_get_direction; | |
448 | gpio->gpio.direction_input = tegra186_gpio_direction_input; | |
449 | gpio->gpio.direction_output = tegra186_gpio_direction_output; | |
450 | gpio->gpio.get = tegra186_gpio_get, | |
451 | gpio->gpio.set = tegra186_gpio_set; | |
452 | ||
453 | gpio->gpio.base = -1; | |
454 | ||
455 | for (i = 0; i < gpio->soc->num_ports; i++) | |
456 | gpio->gpio.ngpio += gpio->soc->ports[i].pins; | |
457 | ||
458 | names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, | |
459 | sizeof(*names), GFP_KERNEL); | |
460 | if (!names) | |
461 | return -ENOMEM; | |
462 | ||
463 | for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { | |
464 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; | |
465 | char *name; | |
466 | ||
467 | for (j = 0; j < port->pins; j++) { | |
468 | name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, | |
469 | "P%s.%02x", port->name, j); | |
470 | if (!name) | |
471 | return -ENOMEM; | |
472 | ||
473 | names[offset + j] = name; | |
474 | } | |
475 | ||
476 | offset += port->pins; | |
477 | } | |
478 | ||
479 | gpio->gpio.names = (const char * const *)names; | |
480 | ||
481 | gpio->gpio.of_node = pdev->dev.of_node; | |
482 | gpio->gpio.of_gpio_n_cells = 2; | |
483 | gpio->gpio.of_xlate = tegra186_gpio_of_xlate; | |
484 | ||
485 | gpio->intc.name = pdev->dev.of_node->name; | |
486 | gpio->intc.irq_ack = tegra186_irq_ack; | |
487 | gpio->intc.irq_mask = tegra186_irq_mask; | |
488 | gpio->intc.irq_unmask = tegra186_irq_unmask; | |
489 | gpio->intc.irq_set_type = tegra186_irq_set_type; | |
490 | ||
491 | irq = &gpio->gpio.irq; | |
492 | irq->chip = &gpio->intc; | |
493 | irq->domain_ops = &tegra186_gpio_irq_domain_ops; | |
494 | irq->handler = handle_simple_irq; | |
5b2b135a TR |
495 | irq->default_type = IRQ_TYPE_NONE; |
496 | irq->parent_handler = tegra186_gpio_irq; | |
497 | irq->parent_handler_data = gpio; | |
498 | irq->num_parents = gpio->num_irq; | |
499 | irq->parents = gpio->irq; | |
500 | ||
501 | irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, | |
502 | sizeof(*irq->map), GFP_KERNEL); | |
503 | if (!irq->map) | |
504 | return -ENOMEM; | |
505 | ||
506 | for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { | |
507 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; | |
508 | ||
509 | for (j = 0; j < port->pins; j++) | |
510 | irq->map[offset + j] = irq->parents[port->irq]; | |
511 | ||
512 | offset += port->pins; | |
513 | } | |
514 | ||
515 | platform_set_drvdata(pdev, gpio); | |
516 | ||
517 | err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); | |
518 | if (err < 0) | |
519 | return err; | |
520 | ||
521 | return 0; | |
522 | } | |
523 | ||
524 | static int tegra186_gpio_remove(struct platform_device *pdev) | |
525 | { | |
526 | return 0; | |
527 | } | |
528 | ||
69118452 TR |
529 | #define TEGRA186_MAIN_GPIO_PORT(port, base, count, controller) \ |
530 | [TEGRA186_MAIN_GPIO_PORT_##port] = { \ | |
5b2b135a TR |
531 | .name = #port, \ |
532 | .offset = base, \ | |
533 | .pins = count, \ | |
534 | .irq = controller, \ | |
535 | } | |
536 | ||
537 | static const struct tegra_gpio_port tegra186_main_ports[] = { | |
69118452 TR |
538 | TEGRA186_MAIN_GPIO_PORT( A, 0x2000, 7, 2), |
539 | TEGRA186_MAIN_GPIO_PORT( B, 0x3000, 7, 3), | |
540 | TEGRA186_MAIN_GPIO_PORT( C, 0x3200, 7, 3), | |
541 | TEGRA186_MAIN_GPIO_PORT( D, 0x3400, 6, 3), | |
542 | TEGRA186_MAIN_GPIO_PORT( E, 0x2200, 8, 2), | |
543 | TEGRA186_MAIN_GPIO_PORT( F, 0x2400, 6, 2), | |
544 | TEGRA186_MAIN_GPIO_PORT( G, 0x4200, 6, 4), | |
545 | TEGRA186_MAIN_GPIO_PORT( H, 0x1000, 7, 1), | |
546 | TEGRA186_MAIN_GPIO_PORT( I, 0x0800, 8, 0), | |
547 | TEGRA186_MAIN_GPIO_PORT( J, 0x5000, 8, 5), | |
548 | TEGRA186_MAIN_GPIO_PORT( K, 0x5200, 1, 5), | |
549 | TEGRA186_MAIN_GPIO_PORT( L, 0x1200, 8, 1), | |
550 | TEGRA186_MAIN_GPIO_PORT( M, 0x5600, 6, 5), | |
551 | TEGRA186_MAIN_GPIO_PORT( N, 0x0000, 7, 0), | |
552 | TEGRA186_MAIN_GPIO_PORT( O, 0x0200, 4, 0), | |
553 | TEGRA186_MAIN_GPIO_PORT( P, 0x4000, 7, 4), | |
554 | TEGRA186_MAIN_GPIO_PORT( Q, 0x0400, 6, 0), | |
555 | TEGRA186_MAIN_GPIO_PORT( R, 0x0a00, 6, 0), | |
556 | TEGRA186_MAIN_GPIO_PORT( T, 0x0600, 4, 0), | |
557 | TEGRA186_MAIN_GPIO_PORT( X, 0x1400, 8, 1), | |
558 | TEGRA186_MAIN_GPIO_PORT( Y, 0x1600, 7, 1), | |
559 | TEGRA186_MAIN_GPIO_PORT(BB, 0x2600, 2, 2), | |
560 | TEGRA186_MAIN_GPIO_PORT(CC, 0x5400, 4, 5), | |
5b2b135a TR |
561 | }; |
562 | ||
563 | static const struct tegra_gpio_soc tegra186_main_soc = { | |
564 | .num_ports = ARRAY_SIZE(tegra186_main_ports), | |
565 | .ports = tegra186_main_ports, | |
566 | .name = "tegra186-gpio", | |
567 | }; | |
568 | ||
69118452 TR |
569 | #define TEGRA186_AON_GPIO_PORT(port, base, count, controller) \ |
570 | [TEGRA186_AON_GPIO_PORT_##port] = { \ | |
5b2b135a TR |
571 | .name = #port, \ |
572 | .offset = base, \ | |
573 | .pins = count, \ | |
574 | .irq = controller, \ | |
575 | } | |
576 | ||
577 | static const struct tegra_gpio_port tegra186_aon_ports[] = { | |
69118452 TR |
578 | TEGRA186_AON_GPIO_PORT( S, 0x0200, 5, 0), |
579 | TEGRA186_AON_GPIO_PORT( U, 0x0400, 6, 0), | |
580 | TEGRA186_AON_GPIO_PORT( V, 0x0800, 8, 0), | |
581 | TEGRA186_AON_GPIO_PORT( W, 0x0a00, 8, 0), | |
582 | TEGRA186_AON_GPIO_PORT( Z, 0x0e00, 4, 0), | |
583 | TEGRA186_AON_GPIO_PORT(AA, 0x0c00, 8, 0), | |
584 | TEGRA186_AON_GPIO_PORT(EE, 0x0600, 3, 0), | |
585 | TEGRA186_AON_GPIO_PORT(FF, 0x0000, 5, 0), | |
5b2b135a TR |
586 | }; |
587 | ||
588 | static const struct tegra_gpio_soc tegra186_aon_soc = { | |
589 | .num_ports = ARRAY_SIZE(tegra186_aon_ports), | |
590 | .ports = tegra186_aon_ports, | |
591 | .name = "tegra186-gpio-aon", | |
592 | }; | |
593 | ||
bac5c3b8 MP |
594 | #define TEGRA194_MAIN_GPIO_PORT(port, base, count, controller) \ |
595 | [TEGRA194_MAIN_GPIO_PORT_##port] = { \ | |
596 | .name = #port, \ | |
597 | .offset = base, \ | |
598 | .pins = count, \ | |
599 | .irq = controller, \ | |
600 | } | |
601 | ||
602 | static const struct tegra_gpio_port tegra194_main_ports[] = { | |
603 | TEGRA194_MAIN_GPIO_PORT( A, 0x1400, 8, 1), | |
604 | TEGRA194_MAIN_GPIO_PORT( B, 0x4e00, 2, 4), | |
605 | TEGRA194_MAIN_GPIO_PORT( C, 0x4600, 8, 4), | |
606 | TEGRA194_MAIN_GPIO_PORT( D, 0x4800, 4, 4), | |
607 | TEGRA194_MAIN_GPIO_PORT( E, 0x4a00, 8, 4), | |
608 | TEGRA194_MAIN_GPIO_PORT( F, 0x4c00, 6, 4), | |
609 | TEGRA194_MAIN_GPIO_PORT( G, 0x4000, 8, 4), | |
610 | TEGRA194_MAIN_GPIO_PORT( H, 0x4200, 8, 4), | |
611 | TEGRA194_MAIN_GPIO_PORT( I, 0x4400, 5, 4), | |
612 | TEGRA194_MAIN_GPIO_PORT( J, 0x5200, 6, 5), | |
613 | TEGRA194_MAIN_GPIO_PORT( K, 0x3000, 8, 3), | |
614 | TEGRA194_MAIN_GPIO_PORT( L, 0x3200, 4, 3), | |
615 | TEGRA194_MAIN_GPIO_PORT( M, 0x2600, 8, 2), | |
616 | TEGRA194_MAIN_GPIO_PORT( N, 0x2800, 3, 2), | |
617 | TEGRA194_MAIN_GPIO_PORT( O, 0x5000, 6, 5), | |
618 | TEGRA194_MAIN_GPIO_PORT( P, 0x2a00, 8, 2), | |
619 | TEGRA194_MAIN_GPIO_PORT( Q, 0x2c00, 8, 2), | |
620 | TEGRA194_MAIN_GPIO_PORT( R, 0x2e00, 6, 2), | |
621 | TEGRA194_MAIN_GPIO_PORT( S, 0x3600, 8, 3), | |
622 | TEGRA194_MAIN_GPIO_PORT( T, 0x3800, 8, 3), | |
623 | TEGRA194_MAIN_GPIO_PORT( U, 0x3a00, 1, 3), | |
624 | TEGRA194_MAIN_GPIO_PORT( V, 0x1000, 8, 1), | |
625 | TEGRA194_MAIN_GPIO_PORT( W, 0x1200, 2, 1), | |
626 | TEGRA194_MAIN_GPIO_PORT( X, 0x2000, 8, 2), | |
627 | TEGRA194_MAIN_GPIO_PORT( Y, 0x2200, 8, 2), | |
628 | TEGRA194_MAIN_GPIO_PORT( Z, 0x2400, 8, 2), | |
629 | TEGRA194_MAIN_GPIO_PORT(FF, 0x3400, 2, 3), | |
630 | TEGRA194_MAIN_GPIO_PORT(GG, 0x0000, 2, 0) | |
631 | }; | |
632 | ||
633 | static const struct tegra_gpio_soc tegra194_main_soc = { | |
634 | .num_ports = ARRAY_SIZE(tegra194_main_ports), | |
635 | .ports = tegra194_main_ports, | |
636 | .name = "tegra194-gpio", | |
637 | }; | |
638 | ||
639 | #define TEGRA194_AON_GPIO_PORT(port, base, count, controller) \ | |
640 | [TEGRA194_AON_GPIO_PORT_##port] = { \ | |
641 | .name = #port, \ | |
642 | .offset = base, \ | |
643 | .pins = count, \ | |
644 | .irq = controller, \ | |
645 | } | |
646 | ||
647 | static const struct tegra_gpio_port tegra194_aon_ports[] = { | |
648 | TEGRA194_AON_GPIO_PORT(AA, 0x0600, 8, 0), | |
649 | TEGRA194_AON_GPIO_PORT(BB, 0x0800, 4, 0), | |
650 | TEGRA194_AON_GPIO_PORT(CC, 0x0200, 8, 0), | |
651 | TEGRA194_AON_GPIO_PORT(DD, 0x0400, 3, 0), | |
652 | TEGRA194_AON_GPIO_PORT(EE, 0x0000, 7, 0) | |
653 | }; | |
654 | ||
655 | static const struct tegra_gpio_soc tegra194_aon_soc = { | |
656 | .num_ports = ARRAY_SIZE(tegra194_aon_ports), | |
657 | .ports = tegra194_aon_ports, | |
658 | .name = "tegra194-gpio-aon", | |
659 | }; | |
660 | ||
5b2b135a TR |
661 | static const struct of_device_id tegra186_gpio_of_match[] = { |
662 | { | |
663 | .compatible = "nvidia,tegra186-gpio", | |
664 | .data = &tegra186_main_soc | |
665 | }, { | |
666 | .compatible = "nvidia,tegra186-gpio-aon", | |
667 | .data = &tegra186_aon_soc | |
bac5c3b8 MP |
668 | }, { |
669 | .compatible = "nvidia,tegra194-gpio", | |
670 | .data = &tegra194_main_soc | |
671 | }, { | |
672 | .compatible = "nvidia,tegra194-gpio-aon", | |
673 | .data = &tegra194_aon_soc | |
5b2b135a TR |
674 | }, { |
675 | /* sentinel */ | |
676 | } | |
677 | }; | |
678 | ||
679 | static struct platform_driver tegra186_gpio_driver = { | |
680 | .driver = { | |
681 | .name = "tegra186-gpio", | |
682 | .of_match_table = tegra186_gpio_of_match, | |
683 | }, | |
684 | .probe = tegra186_gpio_probe, | |
685 | .remove = tegra186_gpio_remove, | |
686 | }; | |
687 | module_platform_driver(tegra186_gpio_driver); | |
688 | ||
689 | MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); | |
690 | MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); | |
691 | MODULE_LICENSE("GPL v2"); |