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fbdev: imsttfb: Fix use after free bug in imsttfb_probe
[linux-block.git] / drivers / gpio / gpio-tegra186.c
CommitLineData
ac1dc6b2 1// SPDX-License-Identifier: GPL-2.0-only
5b2b135a 2/*
10e4afd6 3 * Copyright (c) 2016-2022 NVIDIA Corporation
5b2b135a
TR		 4 *
5 * Author: Thierry Reding <treding@nvidia.com>
10e4afd6 6 * Dipen Patel <dpatel@nvidia.com>
5b2b135a
TR		 7 */
8
9#include <linux/gpio/driver.h>
27bb5fef 10#include <linux/hte.h>
5b2b135a
TR		 11#include <linux/interrupt.h>
12#include <linux/irq.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
27bb5fef 16#include <linux/seq_file.h>
5b2b135a
TR		 17
18#include <dt-bindings/gpio/tegra186-gpio.h>
bac5c3b8 19#include <dt-bindings/gpio/tegra194-gpio.h>
1db9b241 20#include <dt-bindings/gpio/tegra234-gpio.h>
d1056b77 21#include <dt-bindings/gpio/tegra241-gpio.h>
5b2b135a 22
22635ed8
TR		 23/* security registers */
24#define TEGRA186_GPIO_CTL_SCR 0x0c
25#define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28)
26#define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27)
27
28#define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4)
29
30/* control registers */
5b2b135a
TR		 31#define TEGRA186_GPIO_ENABLE_CONFIG 0x00
32#define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0)
33#define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1)
34#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2)
35#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2)
36#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2)
37#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2)
38#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2)
39#define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4)
adce1183 40#define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5)
5b2b135a 41#define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6)
10e4afd6 42#define TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC BIT(7)
5b2b135a
TR		 43
44#define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04
45#define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff)
46
47#define TEGRA186_GPIO_INPUT 0x08
48#define TEGRA186_GPIO_INPUT_HIGH BIT(0)
49
50#define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c
51#define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0)
52
53#define TEGRA186_GPIO_OUTPUT_VALUE 0x10
54#define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0)
55
56#define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14
57
58#define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4)
59
60struct tegra_gpio_port {
61 const char *name;
13a62a56
TR		 62 unsigned int bank;
63 unsigned int port;
5b2b135a 64 unsigned int pins;
5b2b135a
TR		 65};
66
b64d6c9a
TR		 67struct tegra186_pin_range {
68 unsigned int offset;
69 const char *group;
70};
71
5b2b135a
TR		 72struct tegra_gpio_soc {
73 const struct tegra_gpio_port *ports;
74 unsigned int num_ports;
75 const char *name;
2a365505 76 unsigned int instance;
b64d6c9a 77
21038680
TR		 78 unsigned int num_irqs_per_bank;
79
b64d6c9a
TR		 80 const struct tegra186_pin_range *pin_ranges;
81 unsigned int num_pin_ranges;
82 const char *pinmux;
10e4afd6 83 bool has_gte;
5b2b135a
TR		 84};
85
86struct tegra_gpio {
87 struct gpio_chip gpio;
5b2b135a
TR		 88 unsigned int num_irq;
89 unsigned int *irq;
90
91 const struct tegra_gpio_soc *soc;
ca038748
TR		 92 unsigned int num_irqs_per_bank;
93 unsigned int num_banks;
5b2b135a 94
22635ed8 95 void __iomem *secure;
5b2b135a
TR		 96 void __iomem *base;
97};
98
99static const struct tegra_gpio_port *
100tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin)
101{
102 unsigned int start = 0, i;
103
104 for (i = 0; i < gpio->soc->num_ports; i++) {
105 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
106
107 if (*pin >= start && *pin < start + port->pins) {
108 *pin -= start;
109 return port;
110 }
111
112 start += port->pins;
113 }
114
115 return NULL;
116}
117
118static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio,
119 unsigned int pin)
120{
121 const struct tegra_gpio_port *port;
13a62a56 122 unsigned int offset;
5b2b135a
TR		 123
124 port = tegra186_gpio_get_port(gpio, &pin);
125 if (!port)
126 return NULL;
127
13a62a56
TR		 128 offset = port->bank * 0x1000 + port->port * 0x200;
129
130 return gpio->base + offset + pin * 0x20;
5b2b135a
TR		 131}
132
133static int tegra186_gpio_get_direction(struct gpio_chip *chip,
134 unsigned int offset)
135{
136 struct tegra_gpio *gpio = gpiochip_get_data(chip);
137 void __iomem *base;
138 u32 value;
139
140 base = tegra186_gpio_get_base(gpio, offset);
141 if (WARN_ON(base == NULL))
142 return -ENODEV;
143
144 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
145 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
e42615ec 146 return GPIO_LINE_DIRECTION_OUT;
5b2b135a 147
e42615ec 148 return GPIO_LINE_DIRECTION_IN;
5b2b135a
TR		 149}
150
151static int tegra186_gpio_direction_input(struct gpio_chip *chip,
152 unsigned int offset)
153{
154 struct tegra_gpio *gpio = gpiochip_get_data(chip);
155 void __iomem *base;
156 u32 value;
157
158 base = tegra186_gpio_get_base(gpio, offset);
159 if (WARN_ON(base == NULL))
160 return -ENODEV;
161
162 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
163 value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
164 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
165
166 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
167 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
168 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
169 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
170
171 return 0;
172}
173
174static int tegra186_gpio_direction_output(struct gpio_chip *chip,
175 unsigned int offset, int level)
176{
177 struct tegra_gpio *gpio = gpiochip_get_data(chip);
178 void __iomem *base;
179 u32 value;
180
181 /* configure output level first */
182 chip->set(chip, offset, level);
183
184 base = tegra186_gpio_get_base(gpio, offset);
185 if (WARN_ON(base == NULL))
186 return -EINVAL;
187
188 /* set the direction */
189 value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL);
190 value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
191 writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL);
192
193 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
194 value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
195 value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
196 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
197
198 return 0;
199}
200
10e4afd6
DP		 201#define HTE_BOTH_EDGES (HTE_RISING_EDGE_TS | HTE_FALLING_EDGE_TS)
202
203static int tegra186_gpio_en_hw_ts(struct gpio_chip *gc, u32 offset,
204 unsigned long flags)
205{
206 struct tegra_gpio *gpio;
207 void __iomem *base;
208 int value;
209
210 if (!gc)
211 return -EINVAL;
212
213 gpio = gpiochip_get_data(gc);
214 if (!gpio)
215 return -ENODEV;
216
217 base = tegra186_gpio_get_base(gpio, offset);
218 if (WARN_ON(base == NULL))
219 return -EINVAL;
220
221 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
222 value |= TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
223
224 if (flags == HTE_BOTH_EDGES) {
225 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
226 } else if (flags == HTE_RISING_EDGE_TS) {
227 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
228 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
229 } else if (flags == HTE_FALLING_EDGE_TS) {
230 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
231 }
232
233 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
234
235 return 0;
236}
237
238static int tegra186_gpio_dis_hw_ts(struct gpio_chip *gc, u32 offset,
239 unsigned long flags)
240{
241 struct tegra_gpio *gpio;
242 void __iomem *base;
243 int value;
244
245 if (!gc)
246 return -EINVAL;
247
248 gpio = gpiochip_get_data(gc);
249 if (!gpio)
250 return -ENODEV;
251
252 base = tegra186_gpio_get_base(gpio, offset);
253 if (WARN_ON(base == NULL))
254 return -EINVAL;
255
256 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
257 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TIMESTAMP_FUNC;
258 if (flags == HTE_BOTH_EDGES) {
259 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
260 } else if (flags == HTE_RISING_EDGE_TS) {
261 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
262 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
263 } else if (flags == HTE_FALLING_EDGE_TS) {
264 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
265 }
266 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
267
268 return 0;
269}
270
5b2b135a
TR		 271static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset)
272{
273 struct tegra_gpio *gpio = gpiochip_get_data(chip);
274 void __iomem *base;
275 u32 value;
276
277 base = tegra186_gpio_get_base(gpio, offset);
278 if (WARN_ON(base == NULL))
279 return -ENODEV;
280
281 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
282 if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
283 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
284 else
285 value = readl(base + TEGRA186_GPIO_INPUT);
286
287 return value & BIT(0);
288}
289
290static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset,
291 int level)
292{
293 struct tegra_gpio *gpio = gpiochip_get_data(chip);
294 void __iomem *base;
295 u32 value;
296
297 base = tegra186_gpio_get_base(gpio, offset);
298 if (WARN_ON(base == NULL))
299 return;
300
301 value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE);
302 if (level == 0)
303 value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
304 else
305 value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
306
307 writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE);
308}
309
adce1183
TR		 310static int tegra186_gpio_set_config(struct gpio_chip *chip,
311 unsigned int offset,
312 unsigned long config)
313{
314 struct tegra_gpio *gpio = gpiochip_get_data(chip);
315 u32 debounce, value;
316 void __iomem *base;
317
318 base = tegra186_gpio_get_base(gpio, offset);
319 if (base == NULL)
320 return -ENXIO;
321
322 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
323 return -ENOTSUPP;
324
325 debounce = pinconf_to_config_argument(config);
326
327 /*
328 * The Tegra186 GPIO controller supports a maximum of 255 ms debounce
329 * time.
330 */
331 if (debounce > 255000)
332 return -EINVAL;
333
334 debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC);
335
336 value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce);
337 writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL);
338
339 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
340 value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE;
341 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
342
343 return 0;
344}
345
b64d6c9a
TR		 346static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip)
347{
348 struct tegra_gpio *gpio = gpiochip_get_data(chip);
349 struct pinctrl_dev *pctldev;
350 struct device_node *np;
351 unsigned int i, j;
352 int err;
353
354 if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0)
355 return 0;
356
357 np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux);
358 if (!np)
359 return -ENODEV;
360
361 pctldev = of_pinctrl_get(np);
362 of_node_put(np);
363 if (!pctldev)
364 return -EPROBE_DEFER;
365
366 for (i = 0; i < gpio->soc->num_pin_ranges; i++) {
367 unsigned int pin = gpio->soc->pin_ranges[i].offset, port;
368 const char *group = gpio->soc->pin_ranges[i].group;
369
370 port = pin / 8;
371 pin = pin % 8;
372
373 if (port >= gpio->soc->num_ports) {
374 dev_warn(chip->parent, "invalid port %u for %s\n",
375 port, group);
376 continue;
377 }
378
379 for (j = 0; j < port; j++)
380 pin += gpio->soc->ports[j].pins;
381
382 err = gpiochip_add_pingroup_range(chip, pctldev, pin, group);
383 if (err < 0)
384 return err;
385 }
386
387 return 0;
388}
389
5b2b135a
TR		 390static int tegra186_gpio_of_xlate(struct gpio_chip *chip,
391 const struct of_phandle_args *spec,
392 u32 *flags)
393{
394 struct tegra_gpio *gpio = gpiochip_get_data(chip);
395 unsigned int port, pin, i, offset = 0;
396
397 if (WARN_ON(chip->of_gpio_n_cells < 2))
398 return -EINVAL;
399
400 if (WARN_ON(spec->args_count < chip->of_gpio_n_cells))
401 return -EINVAL;
402
403 port = spec->args[0] / 8;
404 pin = spec->args[0] % 8;
405
406 if (port >= gpio->soc->num_ports) {
407 dev_err(chip->parent, "invalid port number: %u\n", port);
408 return -EINVAL;
409 }
410
411 for (i = 0; i < port; i++)
412 offset += gpio->soc->ports[i].pins;
413
414 if (flags)
415 *flags = spec->args[1];
416
417 return offset + pin;
418}
419
d1e972ac
MZ		 420#define to_tegra_gpio(x) container_of((x), struct tegra_gpio, gpio)
421
5b2b135a
TR		 422static void tegra186_irq_ack(struct irq_data *data)
423{
d1e972ac
MZ		 424 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
425 struct tegra_gpio *gpio = to_tegra_gpio(gc);
5b2b135a
TR		 426 void __iomem *base;
427
428 base = tegra186_gpio_get_base(gpio, data->hwirq);
429 if (WARN_ON(base == NULL))
430 return;
431
432 writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR);
433}
434
435static void tegra186_irq_mask(struct irq_data *data)
436{
d1e972ac
MZ		 437 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
438 struct tegra_gpio *gpio = to_tegra_gpio(gc);
5b2b135a
TR		 439 void __iomem *base;
440 u32 value;
441
442 base = tegra186_gpio_get_base(gpio, data->hwirq);
443 if (WARN_ON(base == NULL))
444 return;
445
446 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
447 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
448 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
bba00555
MZ		 449
450 gpiochip_disable_irq(&gpio->gpio, data->hwirq);
5b2b135a
TR		 451}
452
453static void tegra186_irq_unmask(struct irq_data *data)
454{
d1e972ac
MZ		 455 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
456 struct tegra_gpio *gpio = to_tegra_gpio(gc);
5b2b135a
TR		 457 void __iomem *base;
458 u32 value;
459
460 base = tegra186_gpio_get_base(gpio, data->hwirq);
461 if (WARN_ON(base == NULL))
462 return;
463
bba00555
MZ		 464 gpiochip_enable_irq(&gpio->gpio, data->hwirq);
465
5b2b135a
TR		 466 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
467 value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT;
468 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
469}
470
3a2fa906 471static int tegra186_irq_set_type(struct irq_data *data, unsigned int type)
5b2b135a 472{
d1e972ac
MZ		 473 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
474 struct tegra_gpio *gpio = to_tegra_gpio(gc);
5b2b135a
TR		 475 void __iomem *base;
476 u32 value;
477
478 base = tegra186_gpio_get_base(gpio, data->hwirq);
479 if (WARN_ON(base == NULL))
480 return -ENODEV;
481
482 value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG);
483 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK;
484 value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
485
3a2fa906 486 switch (type & IRQ_TYPE_SENSE_MASK) {
5b2b135a
TR		 487 case IRQ_TYPE_NONE:
488 break;
489
490 case IRQ_TYPE_EDGE_RISING:
491 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
492 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
493 break;
494
495 case IRQ_TYPE_EDGE_FALLING:
496 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE;
497 break;
498
499 case IRQ_TYPE_EDGE_BOTH:
500 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE;
501 break;
502
503 case IRQ_TYPE_LEVEL_HIGH:
504 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
505 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL;
506 break;
507
508 case IRQ_TYPE_LEVEL_LOW:
509 value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL;
510 break;
511
512 default:
513 return -EINVAL;
514 }
515
516 writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG);
517
3a2fa906 518 if ((type & IRQ_TYPE_EDGE_BOTH) == 0)
5b2b135a
TR		 519 irq_set_handler_locked(data, handle_level_irq);
520 else
521 irq_set_handler_locked(data, handle_edge_irq);
522
986ec63d
MZ		 523 if (data->parent_data)
524 return irq_chip_set_type_parent(data, type);
525
526 return 0;
527}
528
529static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on)
530{
531 if (data->parent_data)
532 return irq_chip_set_wake_parent(data, on);
533
534 return 0;
5b2b135a
TR		 535}
536
bba00555
MZ		 537static void tegra186_irq_print_chip(struct irq_data *data, struct seq_file *p)
538{
539 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
540
541 seq_printf(p, dev_name(gc->parent));
542}
543
544static const struct irq_chip tegra186_gpio_irq_chip = {
545 .irq_ack = tegra186_irq_ack,
546 .irq_mask = tegra186_irq_mask,
547 .irq_unmask = tegra186_irq_unmask,
548 .irq_set_type = tegra186_irq_set_type,
549 .irq_set_wake = tegra186_irq_set_wake,
550 .irq_print_chip = tegra186_irq_print_chip,
551 .flags = IRQCHIP_IMMUTABLE,
552 GPIOCHIP_IRQ_RESOURCE_HELPERS,
553};
554
5b2b135a
TR		 555static void tegra186_gpio_irq(struct irq_desc *desc)
556{
557 struct tegra_gpio *gpio = irq_desc_get_handler_data(desc);
558 struct irq_domain *domain = gpio->gpio.irq.domain;
559 struct irq_chip *chip = irq_desc_get_chip(desc);
560 unsigned int parent = irq_desc_get_irq(desc);
21038680 561 unsigned int i, j, offset = 0;
5b2b135a
TR		 562
563 chained_irq_enter(chip, desc);
564
565 for (i = 0; i < gpio->soc->num_ports; i++) {
566 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
dbd1c54f 567 unsigned int pin;
5b2b135a 568 unsigned long value;
13a62a56
TR		 569 void __iomem *base;
570
571 base = gpio->base + port->bank * 0x1000 + port->port * 0x200;
5b2b135a 572
13a62a56 573 /* skip ports that are not associated with this bank */
21038680
TR		 574 for (j = 0; j < gpio->num_irqs_per_bank; j++) {
575 if (parent == gpio->irq[port->bank * gpio->num_irqs_per_bank + j])
576 break;
577 }
578
579 if (j == gpio->num_irqs_per_bank)
5b2b135a
TR		 580 goto skip;
581
582 value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1));
583
584 for_each_set_bit(pin, &value, port->pins) {
dbd1c54f
MZ		 585 int ret = generic_handle_domain_irq(domain, offset + pin);
586 WARN_RATELIMIT(ret, "hwirq = %d", offset + pin);
5b2b135a
TR		 587 }
588
589skip:
590 offset += port->pins;
591 }
592
593 chained_irq_exit(chip, desc);
594}
595
2a365505
TR		 596static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain,
597 struct irq_fwspec *fwspec,
598 unsigned long *hwirq,
599 unsigned int *type)
5b2b135a
TR		 600{
601 struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data);
602 unsigned int port, pin, i, offset = 0;
603
2a365505
TR		 604 if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2))
605 return -EINVAL;
606
607 if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells))
5b2b135a
TR		 608 return -EINVAL;
609
2a365505
TR		 610 port = fwspec->param[0] / 8;
611 pin = fwspec->param[0] % 8;
5b2b135a 612
2a365505 613 if (port >= gpio->soc->num_ports)
5b2b135a 614 return -EINVAL;
5b2b135a
TR		 615
616 for (i = 0; i < port; i++)
617 offset += gpio->soc->ports[i].pins;
618
2a365505 619 *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;
5b2b135a
TR		 620 *hwirq = offset + pin;
621
622 return 0;
623}
624
91a29af4
MZ		 625static int tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip,
626 union gpio_irq_fwspec *gfwspec,
627 unsigned int parent_hwirq,
628 unsigned int parent_type)
2a365505
TR		 629{
630 struct tegra_gpio *gpio = gpiochip_get_data(chip);
91a29af4 631 struct irq_fwspec *fwspec = &gfwspec->fwspec;
24258761
KH		 632
633 fwspec->fwnode = chip->irq.parent_domain->fwnode;
2a365505
TR		 634 fwspec->param_count = 3;
635 fwspec->param[0] = gpio->soc->instance;
636 fwspec->param[1] = parent_hwirq;
637 fwspec->param[2] = parent_type;
24258761 638
91a29af4 639 return 0;
2a365505
TR		 640}
641
642static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
643 unsigned int hwirq,
644 unsigned int type,
645 unsigned int *parent_hwirq,
646 unsigned int *parent_type)
647{
648 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
649 *parent_type = type;
650
651 return 0;
652}
653
654static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip,
655 unsigned int offset)
656{
657 struct tegra_gpio *gpio = gpiochip_get_data(chip);
658 unsigned int i;
659
660 for (i = 0; i < gpio->soc->num_ports; i++) {
661 if (offset < gpio->soc->ports[i].pins)
662 break;
663
664 offset -= gpio->soc->ports[i].pins;
665 }
666
667 return offset + i * 8;
668}
669
670static const struct of_device_id tegra186_pmc_of_match[] = {
671 { .compatible = "nvidia,tegra186-pmc" },
672 { .compatible = "nvidia,tegra194-pmc" },
0c27537a 673 { .compatible = "nvidia,tegra234-pmc" },
2a365505 674 { /* sentinel */ }
5b2b135a
TR		 675};
676
22635ed8
TR		 677static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio)
678{
21038680 679 struct device *dev = gpio->gpio.parent;
2e539b73 680 unsigned int i;
22635ed8
TR		 681 u32 value;
682
683 for (i = 0; i < gpio->soc->num_ports; i++) {
684 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
685 unsigned int offset, p = port->port;
686 void __iomem *base;
687
688 base = gpio->secure + port->bank * 0x1000 + 0x800;
689
690 value = readl(base + TEGRA186_GPIO_CTL_SCR);
691
692 /*
693 * For controllers that haven't been locked down yet, make
694 * sure to program the default interrupt route mapping.
695 */
696 if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 &&
697 (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) {
21038680
TR		 698 /*
699 * On Tegra194 and later, each pin can be routed to one or more
700 * interrupts.
701 */
2e539b73
TR		 702 dev_dbg(dev, "programming default interrupt routing for port %s\n",
703 port->name);
704
705 offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, 0);
706
707 /*
708 * By default we only want to route GPIO pins to IRQ 0. This works
709 * only under the assumption that we're running as the host kernel
710 * and hence all GPIO pins are owned by Linux.
711 *
712 * For cases where Linux is the guest OS, the hypervisor will have
713 * to configure the interrupt routing and pass only the valid
714 * interrupts via device tree.
715 */
716 value = readl(base + offset);
717 value = BIT(port->pins) - 1;
718 writel(value, base + offset);
22635ed8
TR		 719 }
720 }
721}
722
ca038748
TR		 723static unsigned int tegra186_gpio_irqs_per_bank(struct tegra_gpio *gpio)
724{
725 struct device *dev = gpio->gpio.parent;
726
727 if (gpio->num_irq > gpio->num_banks) {
728 if (gpio->num_irq % gpio->num_banks != 0)
729 goto error;
730 }
731
732 if (gpio->num_irq < gpio->num_banks)
733 goto error;
734
735 gpio->num_irqs_per_bank = gpio->num_irq / gpio->num_banks;
736
21038680
TR		 737 if (gpio->num_irqs_per_bank > gpio->soc->num_irqs_per_bank)
738 goto error;
739
ca038748
TR		 740 return 0;
741
742error:
743 dev_err(dev, "invalid number of interrupts (%u) for %u banks\n",
744 gpio->num_irq, gpio->num_banks);
745 return -EINVAL;
746}
747
5b2b135a
TR		 748static int tegra186_gpio_probe(struct platform_device *pdev)
749{
750 unsigned int i, j, offset;
751 struct gpio_irq_chip *irq;
752 struct tegra_gpio *gpio;
2a365505 753 struct device_node *np;
5b2b135a
TR		 754 char **names;
755 int err;
756
757 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
758 if (!gpio)
759 return -ENOMEM;
760
2606e7c9 761 gpio->soc = device_get_match_data(&pdev->dev);
ca038748
TR		 762 gpio->gpio.label = gpio->soc->name;
763 gpio->gpio.parent = &pdev->dev;
764
765 /* count the number of banks in the controller */
766 for (i = 0; i < gpio->soc->num_ports; i++)
767 if (gpio->soc->ports[i].bank > gpio->num_banks)
768 gpio->num_banks = gpio->soc->ports[i].bank;
769
770 gpio->num_banks++;
5b2b135a 771
ca038748 772 /* get register apertures */
22635ed8 773 gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security");
2606e7c9
A		 774 if (IS_ERR(gpio->secure)) {
775 gpio->secure = devm_platform_ioremap_resource(pdev, 0);
776 if (IS_ERR(gpio->secure))
777 return PTR_ERR(gpio->secure);
778 }
22635ed8 779
cc4c8318 780 gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
2606e7c9
A		 781 if (IS_ERR(gpio->base)) {
782 gpio->base = devm_platform_ioremap_resource(pdev, 1);
783 if (IS_ERR(gpio->base))
784 return PTR_ERR(gpio->base);
785 }
5b2b135a
TR		 786
787 err = platform_irq_count(pdev);
788 if (err < 0)
789 return err;
790
791 gpio->num_irq = err;
792
ca038748
TR		 793 err = tegra186_gpio_irqs_per_bank(gpio);
794 if (err < 0)
795 return err;
796
5b2b135a
TR		 797 gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq),
798 GFP_KERNEL);
799 if (!gpio->irq)
800 return -ENOMEM;
801
802 for (i = 0; i < gpio->num_irq; i++) {
803 err = platform_get_irq(pdev, i);
804 if (err < 0)
805 return err;
806
807 gpio->irq[i] = err;
808 }
809
b64d6c9a
TR		 810 gpio->gpio.request = gpiochip_generic_request;
811 gpio->gpio.free = gpiochip_generic_free;
5b2b135a
TR		 812 gpio->gpio.get_direction = tegra186_gpio_get_direction;
813 gpio->gpio.direction_input = tegra186_gpio_direction_input;
814 gpio->gpio.direction_output = tegra186_gpio_direction_output;
7de2e5fc 815 gpio->gpio.get = tegra186_gpio_get;
5b2b135a 816 gpio->gpio.set = tegra186_gpio_set;
adce1183 817 gpio->gpio.set_config = tegra186_gpio_set_config;
b64d6c9a 818 gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges;
10e4afd6
DP		 819 if (gpio->soc->has_gte) {
820 gpio->gpio.en_hw_timestamp = tegra186_gpio_en_hw_ts;
821 gpio->gpio.dis_hw_timestamp = tegra186_gpio_dis_hw_ts;
822 }
5b2b135a
TR		 823
824 gpio->gpio.base = -1;
825
826 for (i = 0; i < gpio->soc->num_ports; i++)
827 gpio->gpio.ngpio += gpio->soc->ports[i].pins;
828
829 names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio,
830 sizeof(*names), GFP_KERNEL);
831 if (!names)
832 return -ENOMEM;
833
834 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
835 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
836 char *name;
837
838 for (j = 0; j < port->pins; j++) {
839 name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL,
840 "P%s.%02x", port->name, j);
841 if (!name)
842 return -ENOMEM;
843
844 names[offset + j] = name;
845 }
846
847 offset += port->pins;
848 }
849
850 gpio->gpio.names = (const char * const *)names;
851
2606e7c9 852#if defined(CONFIG_OF_GPIO)
5b2b135a
TR		 853 gpio->gpio.of_gpio_n_cells = 2;
854 gpio->gpio.of_xlate = tegra186_gpio_of_xlate;
2606e7c9 855#endif /* CONFIG_OF_GPIO */
5b2b135a 856
5b2b135a 857 irq = &gpio->gpio.irq;
bba00555 858 gpio_irq_chip_set_chip(irq, &tegra186_gpio_irq_chip);
2a365505
TR		 859 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
860 irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq;
24258761 861 irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec;
2a365505
TR		 862 irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq;
863 irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate;
5b2b135a 864 irq->handler = handle_simple_irq;
5b2b135a
TR		 865 irq->default_type = IRQ_TYPE_NONE;
866 irq->parent_handler = tegra186_gpio_irq;
867 irq->parent_handler_data = gpio;
868 irq->num_parents = gpio->num_irq;
ca038748
TR		 869
870 /*
871 * To simplify things, use a single interrupt per bank for now. Some
872 * chips support up to 8 interrupts per bank, which can be useful to
873 * distribute the load and decrease the processing latency for GPIOs
874 * but it also requires a more complicated interrupt routing than we
875 * currently program.
876 */
877 if (gpio->num_irqs_per_bank > 1) {
878 irq->parents = devm_kcalloc(&pdev->dev, gpio->num_banks,
879 sizeof(*irq->parents), GFP_KERNEL);
880 if (!irq->parents)
881 return -ENOMEM;
882
883 for (i = 0; i < gpio->num_banks; i++)
884 irq->parents[i] = gpio->irq[i * gpio->num_irqs_per_bank];
885
886 irq->num_parents = gpio->num_banks;
887 } else {
888 irq->num_parents = gpio->num_irq;
889 irq->parents = gpio->irq;
890 }
891
21038680
TR		 892 if (gpio->soc->num_irqs_per_bank > 1)
893 tegra186_gpio_init_route_mapping(gpio);
5b2b135a 894
2a365505
TR		 895 np = of_find_matching_node(NULL, tegra186_pmc_of_match);
896 if (np) {
897 irq->parent_domain = irq_find_host(np);
898 of_node_put(np);
899
900 if (!irq->parent_domain)
901 return -EPROBE_DEFER;
902 }
903
5b2b135a
TR		 904 irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio,
905 sizeof(*irq->map), GFP_KERNEL);
906 if (!irq->map)
907 return -ENOMEM;
908
909 for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) {
910 const struct tegra_gpio_port *port = &gpio->soc->ports[i];
911
912 for (j = 0; j < port->pins; j++)
13a62a56 913 irq->map[offset + j] = irq->parents[port->bank];
5b2b135a
TR		 914
915 offset += port->pins;
916 }
917
6e153938 918 return devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio);
5b2b135a
TR		 919}
920
13a62a56
TR		 921#define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
922 [TEGRA186_MAIN_GPIO_PORT_##_name] = { \
923 .name = #_name, \
924 .bank = _bank, \
925 .port = _port, \
926 .pins = _pins, \
5b2b135a
TR		 927 }
928
929static const struct tegra_gpio_port tegra186_main_ports[] = {
13a62a56
TR		 930 TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7),
931 TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7),
932 TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7),
933 TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6),
934 TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8),
935 TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6),
936 TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6),
937 TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7),
938 TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8),
939 TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8),
940 TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1),
941 TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8),
942 TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6),
943 TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7),
944 TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4),
945 TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7),
946 TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6),
947 TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6),
948 TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4),
949 TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8),
950 TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7),
951 TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2),
952 TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4),
5b2b135a
TR		 953};
954
955static const struct tegra_gpio_soc tegra186_main_soc = {
956 .num_ports = ARRAY_SIZE(tegra186_main_ports),
957 .ports = tegra186_main_ports,
958 .name = "tegra186-gpio",
2a365505 959 .instance = 0,
21038680 960 .num_irqs_per_bank = 1,
5b2b135a
TR		 961};
962
13a62a56
TR		 963#define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \
964 [TEGRA186_AON_GPIO_PORT_##_name] = { \
965 .name = #_name, \
966 .bank = _bank, \
967 .port = _port, \
968 .pins = _pins, \
5b2b135a
TR		 969 }
970
971static const struct tegra_gpio_port tegra186_aon_ports[] = {
13a62a56
TR		 972 TEGRA186_AON_GPIO_PORT( S, 0, 1, 5),
973 TEGRA186_AON_GPIO_PORT( U, 0, 2, 6),
974 TEGRA186_AON_GPIO_PORT( V, 0, 4, 8),
975 TEGRA186_AON_GPIO_PORT( W, 0, 5, 8),
976 TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4),
977 TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8),
978 TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3),
979 TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5),
5b2b135a
TR		 980};
981
982static const struct tegra_gpio_soc tegra186_aon_soc = {
983 .num_ports = ARRAY_SIZE(tegra186_aon_ports),
984 .ports = tegra186_aon_ports,
985 .name = "tegra186-gpio-aon",
2a365505 986 .instance = 1,
21038680 987 .num_irqs_per_bank = 1,
5b2b135a
TR		 988};
989
13a62a56
TR		 990#define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
991 [TEGRA194_MAIN_GPIO_PORT_##_name] = { \
992 .name = #_name, \
993 .bank = _bank, \
994 .port = _port, \
995 .pins = _pins, \
bac5c3b8
MP		 996 }
997
998static const struct tegra_gpio_port tegra194_main_ports[] = {
13a62a56
TR		 999 TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8),
1000 TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2),
1001 TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8),
1002 TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4),
1003 TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8),
1004 TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6),
1005 TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8),
1006 TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8),
1007 TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5),
1008 TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6),
1009 TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8),
1010 TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4),
1011 TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8),
1012 TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3),
1013 TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6),
1014 TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8),
1015 TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8),
1016 TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6),
1017 TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8),
1018 TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8),
1019 TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1),
1020 TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8),
1021 TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2),
1022 TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8),
1023 TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8),
1024 TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8),
1025 TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2),
1026 TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2)
bac5c3b8
MP		 1027};
1028
ffa91e7c
TR		 1029static const struct tegra186_pin_range tegra194_main_pin_ranges[] = {
1030 { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" },
1031 { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" },
1032};
1033
bac5c3b8
MP		 1034static const struct tegra_gpio_soc tegra194_main_soc = {
1035 .num_ports = ARRAY_SIZE(tegra194_main_ports),
1036 .ports = tegra194_main_ports,
1037 .name = "tegra194-gpio",
2a365505 1038 .instance = 0,
21038680 1039 .num_irqs_per_bank = 8,
ffa91e7c
TR		 1040 .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges),
1041 .pin_ranges = tegra194_main_pin_ranges,
1042 .pinmux = "nvidia,tegra194-pinmux",
bac5c3b8
MP		 1043};
1044
13a62a56
TR		 1045#define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1046 [TEGRA194_AON_GPIO_PORT_##_name] = { \
1047 .name = #_name, \
1048 .bank = _bank, \
1049 .port = _port, \
1050 .pins = _pins, \
bac5c3b8
MP		 1051 }
1052
1053static const struct tegra_gpio_port tegra194_aon_ports[] = {
13a62a56
TR		 1054 TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8),
1055 TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4),
1056 TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8),
1057 TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3),
1058 TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7)
bac5c3b8
MP		 1059};
1060
1061static const struct tegra_gpio_soc tegra194_aon_soc = {
1062 .num_ports = ARRAY_SIZE(tegra194_aon_ports),
1063 .ports = tegra194_aon_ports,
1064 .name = "tegra194-gpio-aon",
2a365505 1065 .instance = 1,
21038680 1066 .num_irqs_per_bank = 8,
10e4afd6 1067 .has_gte = true,
bac5c3b8
MP		 1068};
1069
1db9b241
PS		 1070#define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1071 [TEGRA234_MAIN_GPIO_PORT_##_name] = { \
1072 .name = #_name, \
1073 .bank = _bank, \
1074 .port = _port, \
1075 .pins = _pins, \
1076 }
1077
1078static const struct tegra_gpio_port tegra234_main_ports[] = {
1079 TEGRA234_MAIN_GPIO_PORT( A, 0, 0, 8),
1080 TEGRA234_MAIN_GPIO_PORT( B, 0, 3, 1),
1081 TEGRA234_MAIN_GPIO_PORT( C, 5, 1, 8),
1082 TEGRA234_MAIN_GPIO_PORT( D, 5, 2, 4),
1083 TEGRA234_MAIN_GPIO_PORT( E, 5, 3, 8),
1084 TEGRA234_MAIN_GPIO_PORT( F, 5, 4, 6),
1085 TEGRA234_MAIN_GPIO_PORT( G, 4, 0, 8),
1086 TEGRA234_MAIN_GPIO_PORT( H, 4, 1, 8),
1087 TEGRA234_MAIN_GPIO_PORT( I, 4, 2, 7),
1088 TEGRA234_MAIN_GPIO_PORT( J, 5, 0, 6),
1089 TEGRA234_MAIN_GPIO_PORT( K, 3, 0, 8),
1090 TEGRA234_MAIN_GPIO_PORT( L, 3, 1, 4),
1091 TEGRA234_MAIN_GPIO_PORT( M, 2, 0, 8),
1092 TEGRA234_MAIN_GPIO_PORT( N, 2, 1, 8),
1093 TEGRA234_MAIN_GPIO_PORT( P, 2, 2, 8),
1094 TEGRA234_MAIN_GPIO_PORT( Q, 2, 3, 8),
1095 TEGRA234_MAIN_GPIO_PORT( R, 2, 4, 6),
1096 TEGRA234_MAIN_GPIO_PORT( X, 1, 0, 8),
1097 TEGRA234_MAIN_GPIO_PORT( Y, 1, 1, 8),
1098 TEGRA234_MAIN_GPIO_PORT( Z, 1, 2, 8),
1099 TEGRA234_MAIN_GPIO_PORT(AC, 0, 1, 8),
1100 TEGRA234_MAIN_GPIO_PORT(AD, 0, 2, 4),
1101 TEGRA234_MAIN_GPIO_PORT(AE, 3, 3, 2),
1102 TEGRA234_MAIN_GPIO_PORT(AF, 3, 4, 4),
1103 TEGRA234_MAIN_GPIO_PORT(AG, 3, 2, 8),
1104};
1105
1106static const struct tegra_gpio_soc tegra234_main_soc = {
1107 .num_ports = ARRAY_SIZE(tegra234_main_ports),
1108 .ports = tegra234_main_ports,
1109 .name = "tegra234-gpio",
1110 .instance = 0,
1111 .num_irqs_per_bank = 8,
1112};
1113
1114#define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1115 [TEGRA234_AON_GPIO_PORT_##_name] = { \
1116 .name = #_name, \
1117 .bank = _bank, \
1118 .port = _port, \
1119 .pins = _pins, \
1120 }
1121
1122static const struct tegra_gpio_port tegra234_aon_ports[] = {
1123 TEGRA234_AON_GPIO_PORT(AA, 0, 4, 8),
1124 TEGRA234_AON_GPIO_PORT(BB, 0, 5, 4),
1125 TEGRA234_AON_GPIO_PORT(CC, 0, 2, 8),
1126 TEGRA234_AON_GPIO_PORT(DD, 0, 3, 3),
1127 TEGRA234_AON_GPIO_PORT(EE, 0, 0, 8),
1128 TEGRA234_AON_GPIO_PORT(GG, 0, 1, 1),
1129};
1130
1131static const struct tegra_gpio_soc tegra234_aon_soc = {
1132 .num_ports = ARRAY_SIZE(tegra234_aon_ports),
1133 .ports = tegra234_aon_ports,
1134 .name = "tegra234-gpio-aon",
1135 .instance = 1,
1136 .num_irqs_per_bank = 8,
7d507452 1137 .has_gte = true,
1db9b241
PS		 1138};
1139
d1056b77
A		 1140#define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
1141 [TEGRA241_MAIN_GPIO_PORT_##_name] = { \
1142 .name = #_name, \
1143 .bank = _bank, \
1144 .port = _port, \
1145 .pins = _pins, \
1146 }
1147
1148static const struct tegra_gpio_port tegra241_main_ports[] = {
1149 TEGRA241_MAIN_GPIO_PORT(A, 0, 0, 8),
1150 TEGRA241_MAIN_GPIO_PORT(B, 0, 1, 8),
1151 TEGRA241_MAIN_GPIO_PORT(C, 0, 2, 2),
1152 TEGRA241_MAIN_GPIO_PORT(D, 0, 3, 6),
1153 TEGRA241_MAIN_GPIO_PORT(E, 0, 4, 8),
1154 TEGRA241_MAIN_GPIO_PORT(F, 1, 0, 8),
1155 TEGRA241_MAIN_GPIO_PORT(G, 1, 1, 8),
1156 TEGRA241_MAIN_GPIO_PORT(H, 1, 2, 8),
1157 TEGRA241_MAIN_GPIO_PORT(J, 1, 3, 8),
1158 TEGRA241_MAIN_GPIO_PORT(K, 1, 4, 4),
1159 TEGRA241_MAIN_GPIO_PORT(L, 1, 5, 6),
1160};
1161
1162static const struct tegra_gpio_soc tegra241_main_soc = {
1163 .num_ports = ARRAY_SIZE(tegra241_main_ports),
1164 .ports = tegra241_main_ports,
1165 .name = "tegra241-gpio",
1166 .instance = 0,
5f84e73f 1167 .num_irqs_per_bank = 8,
d1056b77
A		 1168};
1169
1170#define TEGRA241_AON_GPIO_PORT(_name, _bank, _port, _pins) \
1171 [TEGRA241_AON_GPIO_PORT_##_name] = { \
1172 .name = #_name, \
1173 .bank = _bank, \
1174 .port = _port, \
1175 .pins = _pins, \
1176 }
1177
1178static const struct tegra_gpio_port tegra241_aon_ports[] = {
1179 TEGRA241_AON_GPIO_PORT(AA, 0, 0, 8),
1180 TEGRA241_AON_GPIO_PORT(BB, 0, 0, 4),
1181};
1182
1183static const struct tegra_gpio_soc tegra241_aon_soc = {
1184 .num_ports = ARRAY_SIZE(tegra241_aon_ports),
1185 .ports = tegra241_aon_ports,
1186 .name = "tegra241-gpio-aon",
1187 .instance = 1,
5f84e73f 1188 .num_irqs_per_bank = 8,
d1056b77
A		 1189};
1190
5b2b135a
TR		 1191static const struct of_device_id tegra186_gpio_of_match[] = {
1192 {
1193 .compatible = "nvidia,tegra186-gpio",
1194 .data = &tegra186_main_soc
1195 }, {
1196 .compatible = "nvidia,tegra186-gpio-aon",
1197 .data = &tegra186_aon_soc
bac5c3b8
MP		 1198 }, {
1199 .compatible = "nvidia,tegra194-gpio",
1200 .data = &tegra194_main_soc
1201 }, {
1202 .compatible = "nvidia,tegra194-gpio-aon",
1203 .data = &tegra194_aon_soc
1db9b241
PS		 1204 }, {
1205 .compatible = "nvidia,tegra234-gpio",
1206 .data = &tegra234_main_soc
1207 }, {
1208 .compatible = "nvidia,tegra234-gpio-aon",
1209 .data = &tegra234_aon_soc
5b2b135a
TR		 1210 }, {
1211 /* sentinel */
1212 }
1213};
fef2d3bb 1214MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match);
5b2b135a 1215
2606e7c9
A		 1216static const struct acpi_device_id tegra186_gpio_acpi_match[] = {
1217 { .id = "NVDA0108", .driver_data = (kernel_ulong_t)&tegra186_main_soc },
1218 { .id = "NVDA0208", .driver_data = (kernel_ulong_t)&tegra186_aon_soc },
1219 { .id = "NVDA0308", .driver_data = (kernel_ulong_t)&tegra194_main_soc },
1220 { .id = "NVDA0408", .driver_data = (kernel_ulong_t)&tegra194_aon_soc },
d1056b77
A		 1221 { .id = "NVDA0508", .driver_data = (kernel_ulong_t)&tegra241_main_soc },
1222 { .id = "NVDA0608", .driver_data = (kernel_ulong_t)&tegra241_aon_soc },
2606e7c9
A		 1223 {}
1224};
1225MODULE_DEVICE_TABLE(acpi, tegra186_gpio_acpi_match);
1226
5b2b135a
TR		 1227static struct platform_driver tegra186_gpio_driver = {
1228 .driver = {
1229 .name = "tegra186-gpio",
1230 .of_match_table = tegra186_gpio_of_match,
2606e7c9 1231 .acpi_match_table = tegra186_gpio_acpi_match,
5b2b135a
TR		 1232 },
1233 .probe = tegra186_gpio_probe,
5b2b135a
TR		 1234};
1235module_platform_driver(tegra186_gpio_driver);
1236
1237MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver");
1238MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1239MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)