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5b2b135a TR |
1 | /* |
2 | * Copyright (c) 2016-2017 NVIDIA Corporation | |
3 | * | |
4 | * Author: Thierry Reding <treding@nvidia.com> | |
5 | * | |
6 | * This software is licensed under the terms of the GNU General Public | |
7 | * License version 2, as published by the Free Software Foundation, and | |
8 | * may be copied, distributed, and modified under those terms. | |
9 | */ | |
10 | ||
11 | #include <linux/gpio/driver.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/irq.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/of_device.h> | |
16 | #include <linux/platform_device.h> | |
17 | ||
18 | #include <dt-bindings/gpio/tegra186-gpio.h> | |
bac5c3b8 | 19 | #include <dt-bindings/gpio/tegra194-gpio.h> |
5b2b135a TR |
20 | |
21 | #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 | |
22 | #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) | |
23 | #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) | |
24 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) | |
25 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) | |
26 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) | |
27 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) | |
28 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) | |
29 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) | |
30 | #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) | |
31 | ||
32 | #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 | |
33 | #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) | |
34 | ||
35 | #define TEGRA186_GPIO_INPUT 0x08 | |
36 | #define TEGRA186_GPIO_INPUT_HIGH BIT(0) | |
37 | ||
38 | #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c | |
39 | #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) | |
40 | ||
41 | #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 | |
42 | #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) | |
43 | ||
44 | #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 | |
45 | ||
46 | #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) | |
47 | ||
48 | struct tegra_gpio_port { | |
49 | const char *name; | |
50 | unsigned int offset; | |
51 | unsigned int pins; | |
52 | unsigned int irq; | |
53 | }; | |
54 | ||
55 | struct tegra_gpio_soc { | |
56 | const struct tegra_gpio_port *ports; | |
57 | unsigned int num_ports; | |
58 | const char *name; | |
59 | }; | |
60 | ||
61 | struct tegra_gpio { | |
62 | struct gpio_chip gpio; | |
63 | struct irq_chip intc; | |
64 | unsigned int num_irq; | |
65 | unsigned int *irq; | |
66 | ||
67 | const struct tegra_gpio_soc *soc; | |
68 | ||
69 | void __iomem *base; | |
70 | }; | |
71 | ||
72 | static const struct tegra_gpio_port * | |
73 | tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) | |
74 | { | |
75 | unsigned int start = 0, i; | |
76 | ||
77 | for (i = 0; i < gpio->soc->num_ports; i++) { | |
78 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; | |
79 | ||
80 | if (*pin >= start && *pin < start + port->pins) { | |
81 | *pin -= start; | |
82 | return port; | |
83 | } | |
84 | ||
85 | start += port->pins; | |
86 | } | |
87 | ||
88 | return NULL; | |
89 | } | |
90 | ||
91 | static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, | |
92 | unsigned int pin) | |
93 | { | |
94 | const struct tegra_gpio_port *port; | |
95 | ||
96 | port = tegra186_gpio_get_port(gpio, &pin); | |
97 | if (!port) | |
98 | return NULL; | |
99 | ||
100 | return gpio->base + port->offset + pin * 0x20; | |
101 | } | |
102 | ||
103 | static int tegra186_gpio_get_direction(struct gpio_chip *chip, | |
104 | unsigned int offset) | |
105 | { | |
106 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
107 | void __iomem *base; | |
108 | u32 value; | |
109 | ||
110 | base = tegra186_gpio_get_base(gpio, offset); | |
111 | if (WARN_ON(base == NULL)) | |
112 | return -ENODEV; | |
113 | ||
114 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
115 | if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) | |
116 | return 0; | |
117 | ||
118 | return 1; | |
119 | } | |
120 | ||
121 | static int tegra186_gpio_direction_input(struct gpio_chip *chip, | |
122 | unsigned int offset) | |
123 | { | |
124 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
125 | void __iomem *base; | |
126 | u32 value; | |
127 | ||
128 | base = tegra186_gpio_get_base(gpio, offset); | |
129 | if (WARN_ON(base == NULL)) | |
130 | return -ENODEV; | |
131 | ||
132 | value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); | |
133 | value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; | |
134 | writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); | |
135 | ||
136 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
137 | value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; | |
138 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; | |
139 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
140 | ||
141 | return 0; | |
142 | } | |
143 | ||
144 | static int tegra186_gpio_direction_output(struct gpio_chip *chip, | |
145 | unsigned int offset, int level) | |
146 | { | |
147 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
148 | void __iomem *base; | |
149 | u32 value; | |
150 | ||
151 | /* configure output level first */ | |
152 | chip->set(chip, offset, level); | |
153 | ||
154 | base = tegra186_gpio_get_base(gpio, offset); | |
155 | if (WARN_ON(base == NULL)) | |
156 | return -EINVAL; | |
157 | ||
158 | /* set the direction */ | |
159 | value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); | |
160 | value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; | |
161 | writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); | |
162 | ||
163 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
164 | value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; | |
165 | value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; | |
166 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
171 | static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) | |
172 | { | |
173 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
174 | void __iomem *base; | |
175 | u32 value; | |
176 | ||
177 | base = tegra186_gpio_get_base(gpio, offset); | |
178 | if (WARN_ON(base == NULL)) | |
179 | return -ENODEV; | |
180 | ||
181 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
182 | if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) | |
183 | value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); | |
184 | else | |
185 | value = readl(base + TEGRA186_GPIO_INPUT); | |
186 | ||
187 | return value & BIT(0); | |
188 | } | |
189 | ||
190 | static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, | |
191 | int level) | |
192 | { | |
193 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
194 | void __iomem *base; | |
195 | u32 value; | |
196 | ||
197 | base = tegra186_gpio_get_base(gpio, offset); | |
198 | if (WARN_ON(base == NULL)) | |
199 | return; | |
200 | ||
201 | value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); | |
202 | if (level == 0) | |
203 | value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; | |
204 | else | |
205 | value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; | |
206 | ||
207 | writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); | |
208 | } | |
209 | ||
210 | static int tegra186_gpio_of_xlate(struct gpio_chip *chip, | |
211 | const struct of_phandle_args *spec, | |
212 | u32 *flags) | |
213 | { | |
214 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
215 | unsigned int port, pin, i, offset = 0; | |
216 | ||
217 | if (WARN_ON(chip->of_gpio_n_cells < 2)) | |
218 | return -EINVAL; | |
219 | ||
220 | if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) | |
221 | return -EINVAL; | |
222 | ||
223 | port = spec->args[0] / 8; | |
224 | pin = spec->args[0] % 8; | |
225 | ||
226 | if (port >= gpio->soc->num_ports) { | |
227 | dev_err(chip->parent, "invalid port number: %u\n", port); | |
228 | return -EINVAL; | |
229 | } | |
230 | ||
231 | for (i = 0; i < port; i++) | |
232 | offset += gpio->soc->ports[i].pins; | |
233 | ||
234 | if (flags) | |
235 | *flags = spec->args[1]; | |
236 | ||
237 | return offset + pin; | |
238 | } | |
239 | ||
240 | static void tegra186_irq_ack(struct irq_data *data) | |
241 | { | |
242 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); | |
243 | void __iomem *base; | |
244 | ||
245 | base = tegra186_gpio_get_base(gpio, data->hwirq); | |
246 | if (WARN_ON(base == NULL)) | |
247 | return; | |
248 | ||
249 | writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); | |
250 | } | |
251 | ||
252 | static void tegra186_irq_mask(struct irq_data *data) | |
253 | { | |
254 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); | |
255 | void __iomem *base; | |
256 | u32 value; | |
257 | ||
258 | base = tegra186_gpio_get_base(gpio, data->hwirq); | |
259 | if (WARN_ON(base == NULL)) | |
260 | return; | |
261 | ||
262 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
263 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; | |
264 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
265 | } | |
266 | ||
267 | static void tegra186_irq_unmask(struct irq_data *data) | |
268 | { | |
269 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); | |
270 | void __iomem *base; | |
271 | u32 value; | |
272 | ||
273 | base = tegra186_gpio_get_base(gpio, data->hwirq); | |
274 | if (WARN_ON(base == NULL)) | |
275 | return; | |
276 | ||
277 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
278 | value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; | |
279 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
280 | } | |
281 | ||
282 | static int tegra186_irq_set_type(struct irq_data *data, unsigned int flow) | |
283 | { | |
284 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); | |
285 | void __iomem *base; | |
286 | u32 value; | |
287 | ||
288 | base = tegra186_gpio_get_base(gpio, data->hwirq); | |
289 | if (WARN_ON(base == NULL)) | |
290 | return -ENODEV; | |
291 | ||
292 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
293 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; | |
294 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; | |
295 | ||
296 | switch (flow & IRQ_TYPE_SENSE_MASK) { | |
297 | case IRQ_TYPE_NONE: | |
298 | break; | |
299 | ||
300 | case IRQ_TYPE_EDGE_RISING: | |
301 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; | |
302 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; | |
303 | break; | |
304 | ||
305 | case IRQ_TYPE_EDGE_FALLING: | |
306 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; | |
307 | break; | |
308 | ||
309 | case IRQ_TYPE_EDGE_BOTH: | |
310 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; | |
311 | break; | |
312 | ||
313 | case IRQ_TYPE_LEVEL_HIGH: | |
314 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; | |
315 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; | |
316 | break; | |
317 | ||
318 | case IRQ_TYPE_LEVEL_LOW: | |
319 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; | |
320 | break; | |
321 | ||
322 | default: | |
323 | return -EINVAL; | |
324 | } | |
325 | ||
326 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
327 | ||
328 | if ((flow & IRQ_TYPE_EDGE_BOTH) == 0) | |
329 | irq_set_handler_locked(data, handle_level_irq); | |
330 | else | |
331 | irq_set_handler_locked(data, handle_edge_irq); | |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
336 | static void tegra186_gpio_irq(struct irq_desc *desc) | |
337 | { | |
338 | struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); | |
339 | struct irq_domain *domain = gpio->gpio.irq.domain; | |
340 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
341 | unsigned int parent = irq_desc_get_irq(desc); | |
342 | unsigned int i, offset = 0; | |
343 | ||
344 | chained_irq_enter(chip, desc); | |
345 | ||
346 | for (i = 0; i < gpio->soc->num_ports; i++) { | |
347 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; | |
348 | void __iomem *base = gpio->base + port->offset; | |
349 | unsigned int pin, irq; | |
350 | unsigned long value; | |
351 | ||
352 | /* skip ports that are not associated with this controller */ | |
353 | if (parent != gpio->irq[port->irq]) | |
354 | goto skip; | |
355 | ||
356 | value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); | |
357 | ||
358 | for_each_set_bit(pin, &value, port->pins) { | |
359 | irq = irq_find_mapping(domain, offset + pin); | |
360 | if (WARN_ON(irq == 0)) | |
361 | continue; | |
362 | ||
363 | generic_handle_irq(irq); | |
364 | } | |
365 | ||
366 | skip: | |
367 | offset += port->pins; | |
368 | } | |
369 | ||
370 | chained_irq_exit(chip, desc); | |
371 | } | |
372 | ||
373 | static int tegra186_gpio_irq_domain_xlate(struct irq_domain *domain, | |
374 | struct device_node *np, | |
375 | const u32 *spec, unsigned int size, | |
376 | unsigned long *hwirq, | |
377 | unsigned int *type) | |
378 | { | |
379 | struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); | |
380 | unsigned int port, pin, i, offset = 0; | |
381 | ||
382 | if (size < 2) | |
383 | return -EINVAL; | |
384 | ||
385 | port = spec[0] / 8; | |
386 | pin = spec[0] % 8; | |
387 | ||
388 | if (port >= gpio->soc->num_ports) { | |
389 | dev_err(gpio->gpio.parent, "invalid port number: %u\n", port); | |
390 | return -EINVAL; | |
391 | } | |
392 | ||
393 | for (i = 0; i < port; i++) | |
394 | offset += gpio->soc->ports[i].pins; | |
395 | ||
396 | *type = spec[1] & IRQ_TYPE_SENSE_MASK; | |
397 | *hwirq = offset + pin; | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
402 | static const struct irq_domain_ops tegra186_gpio_irq_domain_ops = { | |
403 | .map = gpiochip_irq_map, | |
404 | .unmap = gpiochip_irq_unmap, | |
405 | .xlate = tegra186_gpio_irq_domain_xlate, | |
406 | }; | |
407 | ||
5b2b135a TR |
408 | static int tegra186_gpio_probe(struct platform_device *pdev) |
409 | { | |
410 | unsigned int i, j, offset; | |
411 | struct gpio_irq_chip *irq; | |
412 | struct tegra_gpio *gpio; | |
413 | struct resource *res; | |
414 | char **names; | |
415 | int err; | |
416 | ||
417 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); | |
418 | if (!gpio) | |
419 | return -ENOMEM; | |
420 | ||
421 | gpio->soc = of_device_get_match_data(&pdev->dev); | |
422 | ||
423 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gpio"); | |
424 | gpio->base = devm_ioremap_resource(&pdev->dev, res); | |
425 | if (IS_ERR(gpio->base)) | |
426 | return PTR_ERR(gpio->base); | |
427 | ||
428 | err = platform_irq_count(pdev); | |
429 | if (err < 0) | |
430 | return err; | |
431 | ||
432 | gpio->num_irq = err; | |
433 | ||
434 | gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), | |
435 | GFP_KERNEL); | |
436 | if (!gpio->irq) | |
437 | return -ENOMEM; | |
438 | ||
439 | for (i = 0; i < gpio->num_irq; i++) { | |
440 | err = platform_get_irq(pdev, i); | |
441 | if (err < 0) | |
442 | return err; | |
443 | ||
444 | gpio->irq[i] = err; | |
445 | } | |
446 | ||
447 | gpio->gpio.label = gpio->soc->name; | |
448 | gpio->gpio.parent = &pdev->dev; | |
449 | ||
450 | gpio->gpio.get_direction = tegra186_gpio_get_direction; | |
451 | gpio->gpio.direction_input = tegra186_gpio_direction_input; | |
452 | gpio->gpio.direction_output = tegra186_gpio_direction_output; | |
453 | gpio->gpio.get = tegra186_gpio_get, | |
454 | gpio->gpio.set = tegra186_gpio_set; | |
455 | ||
456 | gpio->gpio.base = -1; | |
457 | ||
458 | for (i = 0; i < gpio->soc->num_ports; i++) | |
459 | gpio->gpio.ngpio += gpio->soc->ports[i].pins; | |
460 | ||
461 | names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, | |
462 | sizeof(*names), GFP_KERNEL); | |
463 | if (!names) | |
464 | return -ENOMEM; | |
465 | ||
466 | for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { | |
467 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; | |
468 | char *name; | |
469 | ||
470 | for (j = 0; j < port->pins; j++) { | |
471 | name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, | |
472 | "P%s.%02x", port->name, j); | |
473 | if (!name) | |
474 | return -ENOMEM; | |
475 | ||
476 | names[offset + j] = name; | |
477 | } | |
478 | ||
479 | offset += port->pins; | |
480 | } | |
481 | ||
482 | gpio->gpio.names = (const char * const *)names; | |
483 | ||
484 | gpio->gpio.of_node = pdev->dev.of_node; | |
485 | gpio->gpio.of_gpio_n_cells = 2; | |
486 | gpio->gpio.of_xlate = tegra186_gpio_of_xlate; | |
487 | ||
488 | gpio->intc.name = pdev->dev.of_node->name; | |
489 | gpio->intc.irq_ack = tegra186_irq_ack; | |
490 | gpio->intc.irq_mask = tegra186_irq_mask; | |
491 | gpio->intc.irq_unmask = tegra186_irq_unmask; | |
492 | gpio->intc.irq_set_type = tegra186_irq_set_type; | |
493 | ||
494 | irq = &gpio->gpio.irq; | |
495 | irq->chip = &gpio->intc; | |
496 | irq->domain_ops = &tegra186_gpio_irq_domain_ops; | |
497 | irq->handler = handle_simple_irq; | |
5b2b135a TR |
498 | irq->default_type = IRQ_TYPE_NONE; |
499 | irq->parent_handler = tegra186_gpio_irq; | |
500 | irq->parent_handler_data = gpio; | |
501 | irq->num_parents = gpio->num_irq; | |
502 | irq->parents = gpio->irq; | |
503 | ||
504 | irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, | |
505 | sizeof(*irq->map), GFP_KERNEL); | |
506 | if (!irq->map) | |
507 | return -ENOMEM; | |
508 | ||
509 | for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { | |
510 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; | |
511 | ||
512 | for (j = 0; j < port->pins; j++) | |
513 | irq->map[offset + j] = irq->parents[port->irq]; | |
514 | ||
515 | offset += port->pins; | |
516 | } | |
517 | ||
518 | platform_set_drvdata(pdev, gpio); | |
519 | ||
520 | err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); | |
521 | if (err < 0) | |
522 | return err; | |
523 | ||
524 | return 0; | |
525 | } | |
526 | ||
527 | static int tegra186_gpio_remove(struct platform_device *pdev) | |
528 | { | |
529 | return 0; | |
530 | } | |
531 | ||
532 | #define TEGRA_MAIN_GPIO_PORT(port, base, count, controller) \ | |
533 | [TEGRA_MAIN_GPIO_PORT_##port] = { \ | |
534 | .name = #port, \ | |
535 | .offset = base, \ | |
536 | .pins = count, \ | |
537 | .irq = controller, \ | |
538 | } | |
539 | ||
540 | static const struct tegra_gpio_port tegra186_main_ports[] = { | |
541 | TEGRA_MAIN_GPIO_PORT( A, 0x2000, 7, 2), | |
542 | TEGRA_MAIN_GPIO_PORT( B, 0x3000, 7, 3), | |
543 | TEGRA_MAIN_GPIO_PORT( C, 0x3200, 7, 3), | |
544 | TEGRA_MAIN_GPIO_PORT( D, 0x3400, 6, 3), | |
545 | TEGRA_MAIN_GPIO_PORT( E, 0x2200, 8, 2), | |
546 | TEGRA_MAIN_GPIO_PORT( F, 0x2400, 6, 2), | |
547 | TEGRA_MAIN_GPIO_PORT( G, 0x4200, 6, 4), | |
548 | TEGRA_MAIN_GPIO_PORT( H, 0x1000, 7, 1), | |
549 | TEGRA_MAIN_GPIO_PORT( I, 0x0800, 8, 0), | |
550 | TEGRA_MAIN_GPIO_PORT( J, 0x5000, 8, 5), | |
551 | TEGRA_MAIN_GPIO_PORT( K, 0x5200, 1, 5), | |
552 | TEGRA_MAIN_GPIO_PORT( L, 0x1200, 8, 1), | |
553 | TEGRA_MAIN_GPIO_PORT( M, 0x5600, 6, 5), | |
554 | TEGRA_MAIN_GPIO_PORT( N, 0x0000, 7, 0), | |
555 | TEGRA_MAIN_GPIO_PORT( O, 0x0200, 4, 0), | |
556 | TEGRA_MAIN_GPIO_PORT( P, 0x4000, 7, 4), | |
557 | TEGRA_MAIN_GPIO_PORT( Q, 0x0400, 6, 0), | |
558 | TEGRA_MAIN_GPIO_PORT( R, 0x0a00, 6, 0), | |
559 | TEGRA_MAIN_GPIO_PORT( T, 0x0600, 4, 0), | |
560 | TEGRA_MAIN_GPIO_PORT( X, 0x1400, 8, 1), | |
561 | TEGRA_MAIN_GPIO_PORT( Y, 0x1600, 7, 1), | |
562 | TEGRA_MAIN_GPIO_PORT(BB, 0x2600, 2, 2), | |
563 | TEGRA_MAIN_GPIO_PORT(CC, 0x5400, 4, 5), | |
564 | }; | |
565 | ||
566 | static const struct tegra_gpio_soc tegra186_main_soc = { | |
567 | .num_ports = ARRAY_SIZE(tegra186_main_ports), | |
568 | .ports = tegra186_main_ports, | |
569 | .name = "tegra186-gpio", | |
570 | }; | |
571 | ||
572 | #define TEGRA_AON_GPIO_PORT(port, base, count, controller) \ | |
573 | [TEGRA_AON_GPIO_PORT_##port] = { \ | |
574 | .name = #port, \ | |
575 | .offset = base, \ | |
576 | .pins = count, \ | |
577 | .irq = controller, \ | |
578 | } | |
579 | ||
580 | static const struct tegra_gpio_port tegra186_aon_ports[] = { | |
581 | TEGRA_AON_GPIO_PORT( S, 0x0200, 5, 0), | |
582 | TEGRA_AON_GPIO_PORT( U, 0x0400, 6, 0), | |
583 | TEGRA_AON_GPIO_PORT( V, 0x0800, 8, 0), | |
584 | TEGRA_AON_GPIO_PORT( W, 0x0a00, 8, 0), | |
585 | TEGRA_AON_GPIO_PORT( Z, 0x0e00, 4, 0), | |
586 | TEGRA_AON_GPIO_PORT(AA, 0x0c00, 8, 0), | |
587 | TEGRA_AON_GPIO_PORT(EE, 0x0600, 3, 0), | |
588 | TEGRA_AON_GPIO_PORT(FF, 0x0000, 5, 0), | |
589 | }; | |
590 | ||
591 | static const struct tegra_gpio_soc tegra186_aon_soc = { | |
592 | .num_ports = ARRAY_SIZE(tegra186_aon_ports), | |
593 | .ports = tegra186_aon_ports, | |
594 | .name = "tegra186-gpio-aon", | |
595 | }; | |
596 | ||
bac5c3b8 MP |
597 | #define TEGRA194_MAIN_GPIO_PORT(port, base, count, controller) \ |
598 | [TEGRA194_MAIN_GPIO_PORT_##port] = { \ | |
599 | .name = #port, \ | |
600 | .offset = base, \ | |
601 | .pins = count, \ | |
602 | .irq = controller, \ | |
603 | } | |
604 | ||
605 | static const struct tegra_gpio_port tegra194_main_ports[] = { | |
606 | TEGRA194_MAIN_GPIO_PORT( A, 0x1400, 8, 1), | |
607 | TEGRA194_MAIN_GPIO_PORT( B, 0x4e00, 2, 4), | |
608 | TEGRA194_MAIN_GPIO_PORT( C, 0x4600, 8, 4), | |
609 | TEGRA194_MAIN_GPIO_PORT( D, 0x4800, 4, 4), | |
610 | TEGRA194_MAIN_GPIO_PORT( E, 0x4a00, 8, 4), | |
611 | TEGRA194_MAIN_GPIO_PORT( F, 0x4c00, 6, 4), | |
612 | TEGRA194_MAIN_GPIO_PORT( G, 0x4000, 8, 4), | |
613 | TEGRA194_MAIN_GPIO_PORT( H, 0x4200, 8, 4), | |
614 | TEGRA194_MAIN_GPIO_PORT( I, 0x4400, 5, 4), | |
615 | TEGRA194_MAIN_GPIO_PORT( J, 0x5200, 6, 5), | |
616 | TEGRA194_MAIN_GPIO_PORT( K, 0x3000, 8, 3), | |
617 | TEGRA194_MAIN_GPIO_PORT( L, 0x3200, 4, 3), | |
618 | TEGRA194_MAIN_GPIO_PORT( M, 0x2600, 8, 2), | |
619 | TEGRA194_MAIN_GPIO_PORT( N, 0x2800, 3, 2), | |
620 | TEGRA194_MAIN_GPIO_PORT( O, 0x5000, 6, 5), | |
621 | TEGRA194_MAIN_GPIO_PORT( P, 0x2a00, 8, 2), | |
622 | TEGRA194_MAIN_GPIO_PORT( Q, 0x2c00, 8, 2), | |
623 | TEGRA194_MAIN_GPIO_PORT( R, 0x2e00, 6, 2), | |
624 | TEGRA194_MAIN_GPIO_PORT( S, 0x3600, 8, 3), | |
625 | TEGRA194_MAIN_GPIO_PORT( T, 0x3800, 8, 3), | |
626 | TEGRA194_MAIN_GPIO_PORT( U, 0x3a00, 1, 3), | |
627 | TEGRA194_MAIN_GPIO_PORT( V, 0x1000, 8, 1), | |
628 | TEGRA194_MAIN_GPIO_PORT( W, 0x1200, 2, 1), | |
629 | TEGRA194_MAIN_GPIO_PORT( X, 0x2000, 8, 2), | |
630 | TEGRA194_MAIN_GPIO_PORT( Y, 0x2200, 8, 2), | |
631 | TEGRA194_MAIN_GPIO_PORT( Z, 0x2400, 8, 2), | |
632 | TEGRA194_MAIN_GPIO_PORT(FF, 0x3400, 2, 3), | |
633 | TEGRA194_MAIN_GPIO_PORT(GG, 0x0000, 2, 0) | |
634 | }; | |
635 | ||
636 | static const struct tegra_gpio_soc tegra194_main_soc = { | |
637 | .num_ports = ARRAY_SIZE(tegra194_main_ports), | |
638 | .ports = tegra194_main_ports, | |
639 | .name = "tegra194-gpio", | |
640 | }; | |
641 | ||
642 | #define TEGRA194_AON_GPIO_PORT(port, base, count, controller) \ | |
643 | [TEGRA194_AON_GPIO_PORT_##port] = { \ | |
644 | .name = #port, \ | |
645 | .offset = base, \ | |
646 | .pins = count, \ | |
647 | .irq = controller, \ | |
648 | } | |
649 | ||
650 | static const struct tegra_gpio_port tegra194_aon_ports[] = { | |
651 | TEGRA194_AON_GPIO_PORT(AA, 0x0600, 8, 0), | |
652 | TEGRA194_AON_GPIO_PORT(BB, 0x0800, 4, 0), | |
653 | TEGRA194_AON_GPIO_PORT(CC, 0x0200, 8, 0), | |
654 | TEGRA194_AON_GPIO_PORT(DD, 0x0400, 3, 0), | |
655 | TEGRA194_AON_GPIO_PORT(EE, 0x0000, 7, 0) | |
656 | }; | |
657 | ||
658 | static const struct tegra_gpio_soc tegra194_aon_soc = { | |
659 | .num_ports = ARRAY_SIZE(tegra194_aon_ports), | |
660 | .ports = tegra194_aon_ports, | |
661 | .name = "tegra194-gpio-aon", | |
662 | }; | |
663 | ||
5b2b135a TR |
664 | static const struct of_device_id tegra186_gpio_of_match[] = { |
665 | { | |
666 | .compatible = "nvidia,tegra186-gpio", | |
667 | .data = &tegra186_main_soc | |
668 | }, { | |
669 | .compatible = "nvidia,tegra186-gpio-aon", | |
670 | .data = &tegra186_aon_soc | |
bac5c3b8 MP |
671 | }, { |
672 | .compatible = "nvidia,tegra194-gpio", | |
673 | .data = &tegra194_main_soc | |
674 | }, { | |
675 | .compatible = "nvidia,tegra194-gpio-aon", | |
676 | .data = &tegra194_aon_soc | |
5b2b135a TR |
677 | }, { |
678 | /* sentinel */ | |
679 | } | |
680 | }; | |
681 | ||
682 | static struct platform_driver tegra186_gpio_driver = { | |
683 | .driver = { | |
684 | .name = "tegra186-gpio", | |
685 | .of_match_table = tegra186_gpio_of_match, | |
686 | }, | |
687 | .probe = tegra186_gpio_probe, | |
688 | .remove = tegra186_gpio_remove, | |
689 | }; | |
690 | module_platform_driver(tegra186_gpio_driver); | |
691 | ||
692 | MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); | |
693 | MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); | |
694 | MODULE_LICENSE("GPL v2"); |