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ac1dc6b2 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
5b2b135a TR |
2 | /* |
3 | * Copyright (c) 2016-2017 NVIDIA Corporation | |
4 | * | |
5 | * Author: Thierry Reding <treding@nvidia.com> | |
5b2b135a TR |
6 | */ |
7 | ||
8 | #include <linux/gpio/driver.h> | |
9 | #include <linux/interrupt.h> | |
10 | #include <linux/irq.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of_device.h> | |
13 | #include <linux/platform_device.h> | |
14 | ||
15 | #include <dt-bindings/gpio/tegra186-gpio.h> | |
bac5c3b8 | 16 | #include <dt-bindings/gpio/tegra194-gpio.h> |
5b2b135a | 17 | |
22635ed8 TR |
18 | /* security registers */ |
19 | #define TEGRA186_GPIO_CTL_SCR 0x0c | |
20 | #define TEGRA186_GPIO_CTL_SCR_SEC_WEN BIT(28) | |
21 | #define TEGRA186_GPIO_CTL_SCR_SEC_REN BIT(27) | |
22 | ||
23 | #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4) | |
24 | ||
25 | /* control registers */ | |
5b2b135a TR |
26 | #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 |
27 | #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) | |
28 | #define TEGRA186_GPIO_ENABLE_CONFIG_OUT BIT(1) | |
29 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_NONE (0x0 << 2) | |
30 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL (0x1 << 2) | |
31 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE (0x2 << 2) | |
32 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE (0x3 << 2) | |
33 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK (0x3 << 2) | |
34 | #define TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL BIT(4) | |
adce1183 | 35 | #define TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE BIT(5) |
5b2b135a TR |
36 | #define TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT BIT(6) |
37 | ||
38 | #define TEGRA186_GPIO_DEBOUNCE_CONTROL 0x04 | |
39 | #define TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(x) ((x) & 0xff) | |
40 | ||
41 | #define TEGRA186_GPIO_INPUT 0x08 | |
42 | #define TEGRA186_GPIO_INPUT_HIGH BIT(0) | |
43 | ||
44 | #define TEGRA186_GPIO_OUTPUT_CONTROL 0x0c | |
45 | #define TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED BIT(0) | |
46 | ||
47 | #define TEGRA186_GPIO_OUTPUT_VALUE 0x10 | |
48 | #define TEGRA186_GPIO_OUTPUT_VALUE_HIGH BIT(0) | |
49 | ||
50 | #define TEGRA186_GPIO_INTERRUPT_CLEAR 0x14 | |
51 | ||
52 | #define TEGRA186_GPIO_INTERRUPT_STATUS(x) (0x100 + (x) * 4) | |
53 | ||
54 | struct tegra_gpio_port { | |
55 | const char *name; | |
13a62a56 TR |
56 | unsigned int bank; |
57 | unsigned int port; | |
5b2b135a | 58 | unsigned int pins; |
5b2b135a TR |
59 | }; |
60 | ||
b64d6c9a TR |
61 | struct tegra186_pin_range { |
62 | unsigned int offset; | |
63 | const char *group; | |
64 | }; | |
65 | ||
5b2b135a TR |
66 | struct tegra_gpio_soc { |
67 | const struct tegra_gpio_port *ports; | |
68 | unsigned int num_ports; | |
69 | const char *name; | |
2a365505 | 70 | unsigned int instance; |
b64d6c9a TR |
71 | |
72 | const struct tegra186_pin_range *pin_ranges; | |
73 | unsigned int num_pin_ranges; | |
74 | const char *pinmux; | |
5b2b135a TR |
75 | }; |
76 | ||
77 | struct tegra_gpio { | |
78 | struct gpio_chip gpio; | |
79 | struct irq_chip intc; | |
80 | unsigned int num_irq; | |
81 | unsigned int *irq; | |
82 | ||
83 | const struct tegra_gpio_soc *soc; | |
84 | ||
22635ed8 | 85 | void __iomem *secure; |
5b2b135a TR |
86 | void __iomem *base; |
87 | }; | |
88 | ||
89 | static const struct tegra_gpio_port * | |
90 | tegra186_gpio_get_port(struct tegra_gpio *gpio, unsigned int *pin) | |
91 | { | |
92 | unsigned int start = 0, i; | |
93 | ||
94 | for (i = 0; i < gpio->soc->num_ports; i++) { | |
95 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; | |
96 | ||
97 | if (*pin >= start && *pin < start + port->pins) { | |
98 | *pin -= start; | |
99 | return port; | |
100 | } | |
101 | ||
102 | start += port->pins; | |
103 | } | |
104 | ||
105 | return NULL; | |
106 | } | |
107 | ||
108 | static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, | |
109 | unsigned int pin) | |
110 | { | |
111 | const struct tegra_gpio_port *port; | |
13a62a56 | 112 | unsigned int offset; |
5b2b135a TR |
113 | |
114 | port = tegra186_gpio_get_port(gpio, &pin); | |
115 | if (!port) | |
116 | return NULL; | |
117 | ||
13a62a56 TR |
118 | offset = port->bank * 0x1000 + port->port * 0x200; |
119 | ||
120 | return gpio->base + offset + pin * 0x20; | |
5b2b135a TR |
121 | } |
122 | ||
123 | static int tegra186_gpio_get_direction(struct gpio_chip *chip, | |
124 | unsigned int offset) | |
125 | { | |
126 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
127 | void __iomem *base; | |
128 | u32 value; | |
129 | ||
130 | base = tegra186_gpio_get_base(gpio, offset); | |
131 | if (WARN_ON(base == NULL)) | |
132 | return -ENODEV; | |
133 | ||
134 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
135 | if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) | |
e42615ec | 136 | return GPIO_LINE_DIRECTION_OUT; |
5b2b135a | 137 | |
e42615ec | 138 | return GPIO_LINE_DIRECTION_IN; |
5b2b135a TR |
139 | } |
140 | ||
141 | static int tegra186_gpio_direction_input(struct gpio_chip *chip, | |
142 | unsigned int offset) | |
143 | { | |
144 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
145 | void __iomem *base; | |
146 | u32 value; | |
147 | ||
148 | base = tegra186_gpio_get_base(gpio, offset); | |
149 | if (WARN_ON(base == NULL)) | |
150 | return -ENODEV; | |
151 | ||
152 | value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); | |
153 | value |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; | |
154 | writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); | |
155 | ||
156 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
157 | value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; | |
158 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT; | |
159 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
164 | static int tegra186_gpio_direction_output(struct gpio_chip *chip, | |
165 | unsigned int offset, int level) | |
166 | { | |
167 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
168 | void __iomem *base; | |
169 | u32 value; | |
170 | ||
171 | /* configure output level first */ | |
172 | chip->set(chip, offset, level); | |
173 | ||
174 | base = tegra186_gpio_get_base(gpio, offset); | |
175 | if (WARN_ON(base == NULL)) | |
176 | return -EINVAL; | |
177 | ||
178 | /* set the direction */ | |
179 | value = readl(base + TEGRA186_GPIO_OUTPUT_CONTROL); | |
180 | value &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED; | |
181 | writel(value, base + TEGRA186_GPIO_OUTPUT_CONTROL); | |
182 | ||
183 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
184 | value |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE; | |
185 | value |= TEGRA186_GPIO_ENABLE_CONFIG_OUT; | |
186 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | static int tegra186_gpio_get(struct gpio_chip *chip, unsigned int offset) | |
192 | { | |
193 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
194 | void __iomem *base; | |
195 | u32 value; | |
196 | ||
197 | base = tegra186_gpio_get_base(gpio, offset); | |
198 | if (WARN_ON(base == NULL)) | |
199 | return -ENODEV; | |
200 | ||
201 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
202 | if (value & TEGRA186_GPIO_ENABLE_CONFIG_OUT) | |
203 | value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); | |
204 | else | |
205 | value = readl(base + TEGRA186_GPIO_INPUT); | |
206 | ||
207 | return value & BIT(0); | |
208 | } | |
209 | ||
210 | static void tegra186_gpio_set(struct gpio_chip *chip, unsigned int offset, | |
211 | int level) | |
212 | { | |
213 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
214 | void __iomem *base; | |
215 | u32 value; | |
216 | ||
217 | base = tegra186_gpio_get_base(gpio, offset); | |
218 | if (WARN_ON(base == NULL)) | |
219 | return; | |
220 | ||
221 | value = readl(base + TEGRA186_GPIO_OUTPUT_VALUE); | |
222 | if (level == 0) | |
223 | value &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH; | |
224 | else | |
225 | value |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH; | |
226 | ||
227 | writel(value, base + TEGRA186_GPIO_OUTPUT_VALUE); | |
228 | } | |
229 | ||
adce1183 TR |
230 | static int tegra186_gpio_set_config(struct gpio_chip *chip, |
231 | unsigned int offset, | |
232 | unsigned long config) | |
233 | { | |
234 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
235 | u32 debounce, value; | |
236 | void __iomem *base; | |
237 | ||
238 | base = tegra186_gpio_get_base(gpio, offset); | |
239 | if (base == NULL) | |
240 | return -ENXIO; | |
241 | ||
242 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
243 | return -ENOTSUPP; | |
244 | ||
245 | debounce = pinconf_to_config_argument(config); | |
246 | ||
247 | /* | |
248 | * The Tegra186 GPIO controller supports a maximum of 255 ms debounce | |
249 | * time. | |
250 | */ | |
251 | if (debounce > 255000) | |
252 | return -EINVAL; | |
253 | ||
254 | debounce = DIV_ROUND_UP(debounce, USEC_PER_MSEC); | |
255 | ||
256 | value = TEGRA186_GPIO_DEBOUNCE_CONTROL_THRESHOLD(debounce); | |
257 | writel(value, base + TEGRA186_GPIO_DEBOUNCE_CONTROL); | |
258 | ||
259 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
260 | value |= TEGRA186_GPIO_ENABLE_CONFIG_DEBOUNCE; | |
261 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
262 | ||
263 | return 0; | |
264 | } | |
265 | ||
b64d6c9a TR |
266 | static int tegra186_gpio_add_pin_ranges(struct gpio_chip *chip) |
267 | { | |
268 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
269 | struct pinctrl_dev *pctldev; | |
270 | struct device_node *np; | |
271 | unsigned int i, j; | |
272 | int err; | |
273 | ||
274 | if (!gpio->soc->pinmux || gpio->soc->num_pin_ranges == 0) | |
275 | return 0; | |
276 | ||
277 | np = of_find_compatible_node(NULL, NULL, gpio->soc->pinmux); | |
278 | if (!np) | |
279 | return -ENODEV; | |
280 | ||
281 | pctldev = of_pinctrl_get(np); | |
282 | of_node_put(np); | |
283 | if (!pctldev) | |
284 | return -EPROBE_DEFER; | |
285 | ||
286 | for (i = 0; i < gpio->soc->num_pin_ranges; i++) { | |
287 | unsigned int pin = gpio->soc->pin_ranges[i].offset, port; | |
288 | const char *group = gpio->soc->pin_ranges[i].group; | |
289 | ||
290 | port = pin / 8; | |
291 | pin = pin % 8; | |
292 | ||
293 | if (port >= gpio->soc->num_ports) { | |
294 | dev_warn(chip->parent, "invalid port %u for %s\n", | |
295 | port, group); | |
296 | continue; | |
297 | } | |
298 | ||
299 | for (j = 0; j < port; j++) | |
300 | pin += gpio->soc->ports[j].pins; | |
301 | ||
302 | err = gpiochip_add_pingroup_range(chip, pctldev, pin, group); | |
303 | if (err < 0) | |
304 | return err; | |
305 | } | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
5b2b135a TR |
310 | static int tegra186_gpio_of_xlate(struct gpio_chip *chip, |
311 | const struct of_phandle_args *spec, | |
312 | u32 *flags) | |
313 | { | |
314 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
315 | unsigned int port, pin, i, offset = 0; | |
316 | ||
317 | if (WARN_ON(chip->of_gpio_n_cells < 2)) | |
318 | return -EINVAL; | |
319 | ||
320 | if (WARN_ON(spec->args_count < chip->of_gpio_n_cells)) | |
321 | return -EINVAL; | |
322 | ||
323 | port = spec->args[0] / 8; | |
324 | pin = spec->args[0] % 8; | |
325 | ||
326 | if (port >= gpio->soc->num_ports) { | |
327 | dev_err(chip->parent, "invalid port number: %u\n", port); | |
328 | return -EINVAL; | |
329 | } | |
330 | ||
331 | for (i = 0; i < port; i++) | |
332 | offset += gpio->soc->ports[i].pins; | |
333 | ||
334 | if (flags) | |
335 | *flags = spec->args[1]; | |
336 | ||
337 | return offset + pin; | |
338 | } | |
339 | ||
340 | static void tegra186_irq_ack(struct irq_data *data) | |
341 | { | |
342 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); | |
343 | void __iomem *base; | |
344 | ||
345 | base = tegra186_gpio_get_base(gpio, data->hwirq); | |
346 | if (WARN_ON(base == NULL)) | |
347 | return; | |
348 | ||
349 | writel(1, base + TEGRA186_GPIO_INTERRUPT_CLEAR); | |
350 | } | |
351 | ||
352 | static void tegra186_irq_mask(struct irq_data *data) | |
353 | { | |
354 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); | |
355 | void __iomem *base; | |
356 | u32 value; | |
357 | ||
358 | base = tegra186_gpio_get_base(gpio, data->hwirq); | |
359 | if (WARN_ON(base == NULL)) | |
360 | return; | |
361 | ||
362 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
363 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; | |
364 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
365 | } | |
366 | ||
367 | static void tegra186_irq_unmask(struct irq_data *data) | |
368 | { | |
369 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); | |
370 | void __iomem *base; | |
371 | u32 value; | |
372 | ||
373 | base = tegra186_gpio_get_base(gpio, data->hwirq); | |
374 | if (WARN_ON(base == NULL)) | |
375 | return; | |
376 | ||
377 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
378 | value |= TEGRA186_GPIO_ENABLE_CONFIG_INTERRUPT; | |
379 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
380 | } | |
381 | ||
3a2fa906 | 382 | static int tegra186_irq_set_type(struct irq_data *data, unsigned int type) |
5b2b135a TR |
383 | { |
384 | struct tegra_gpio *gpio = irq_data_get_irq_chip_data(data); | |
385 | void __iomem *base; | |
386 | u32 value; | |
387 | ||
388 | base = tegra186_gpio_get_base(gpio, data->hwirq); | |
389 | if (WARN_ON(base == NULL)) | |
390 | return -ENODEV; | |
391 | ||
392 | value = readl(base + TEGRA186_GPIO_ENABLE_CONFIG); | |
393 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_MASK; | |
394 | value &= ~TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; | |
395 | ||
3a2fa906 | 396 | switch (type & IRQ_TYPE_SENSE_MASK) { |
5b2b135a TR |
397 | case IRQ_TYPE_NONE: |
398 | break; | |
399 | ||
400 | case IRQ_TYPE_EDGE_RISING: | |
401 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; | |
402 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; | |
403 | break; | |
404 | ||
405 | case IRQ_TYPE_EDGE_FALLING: | |
406 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_SINGLE_EDGE; | |
407 | break; | |
408 | ||
409 | case IRQ_TYPE_EDGE_BOTH: | |
410 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_DOUBLE_EDGE; | |
411 | break; | |
412 | ||
413 | case IRQ_TYPE_LEVEL_HIGH: | |
414 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; | |
415 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_LEVEL; | |
416 | break; | |
417 | ||
418 | case IRQ_TYPE_LEVEL_LOW: | |
419 | value |= TEGRA186_GPIO_ENABLE_CONFIG_TRIGGER_TYPE_LEVEL; | |
420 | break; | |
421 | ||
422 | default: | |
423 | return -EINVAL; | |
424 | } | |
425 | ||
426 | writel(value, base + TEGRA186_GPIO_ENABLE_CONFIG); | |
427 | ||
3a2fa906 | 428 | if ((type & IRQ_TYPE_EDGE_BOTH) == 0) |
5b2b135a TR |
429 | irq_set_handler_locked(data, handle_level_irq); |
430 | else | |
431 | irq_set_handler_locked(data, handle_edge_irq); | |
432 | ||
986ec63d MZ |
433 | if (data->parent_data) |
434 | return irq_chip_set_type_parent(data, type); | |
435 | ||
436 | return 0; | |
437 | } | |
438 | ||
439 | static int tegra186_irq_set_wake(struct irq_data *data, unsigned int on) | |
440 | { | |
441 | if (data->parent_data) | |
442 | return irq_chip_set_wake_parent(data, on); | |
443 | ||
444 | return 0; | |
5b2b135a TR |
445 | } |
446 | ||
c4e1f7d9 LW |
447 | static int tegra186_irq_set_affinity(struct irq_data *data, |
448 | const struct cpumask *dest, | |
449 | bool force) | |
450 | { | |
451 | if (data->parent_data) | |
452 | return irq_chip_set_affinity_parent(data, dest, force); | |
453 | ||
454 | return -EINVAL; | |
455 | } | |
456 | ||
5b2b135a TR |
457 | static void tegra186_gpio_irq(struct irq_desc *desc) |
458 | { | |
459 | struct tegra_gpio *gpio = irq_desc_get_handler_data(desc); | |
460 | struct irq_domain *domain = gpio->gpio.irq.domain; | |
461 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
462 | unsigned int parent = irq_desc_get_irq(desc); | |
463 | unsigned int i, offset = 0; | |
464 | ||
465 | chained_irq_enter(chip, desc); | |
466 | ||
467 | for (i = 0; i < gpio->soc->num_ports; i++) { | |
468 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; | |
5b2b135a TR |
469 | unsigned int pin, irq; |
470 | unsigned long value; | |
13a62a56 TR |
471 | void __iomem *base; |
472 | ||
473 | base = gpio->base + port->bank * 0x1000 + port->port * 0x200; | |
5b2b135a | 474 | |
13a62a56 TR |
475 | /* skip ports that are not associated with this bank */ |
476 | if (parent != gpio->irq[port->bank]) | |
5b2b135a TR |
477 | goto skip; |
478 | ||
479 | value = readl(base + TEGRA186_GPIO_INTERRUPT_STATUS(1)); | |
480 | ||
481 | for_each_set_bit(pin, &value, port->pins) { | |
482 | irq = irq_find_mapping(domain, offset + pin); | |
483 | if (WARN_ON(irq == 0)) | |
484 | continue; | |
485 | ||
486 | generic_handle_irq(irq); | |
487 | } | |
488 | ||
489 | skip: | |
490 | offset += port->pins; | |
491 | } | |
492 | ||
493 | chained_irq_exit(chip, desc); | |
494 | } | |
495 | ||
2a365505 TR |
496 | static int tegra186_gpio_irq_domain_translate(struct irq_domain *domain, |
497 | struct irq_fwspec *fwspec, | |
498 | unsigned long *hwirq, | |
499 | unsigned int *type) | |
5b2b135a TR |
500 | { |
501 | struct tegra_gpio *gpio = gpiochip_get_data(domain->host_data); | |
502 | unsigned int port, pin, i, offset = 0; | |
503 | ||
2a365505 TR |
504 | if (WARN_ON(gpio->gpio.of_gpio_n_cells < 2)) |
505 | return -EINVAL; | |
506 | ||
507 | if (WARN_ON(fwspec->param_count < gpio->gpio.of_gpio_n_cells)) | |
5b2b135a TR |
508 | return -EINVAL; |
509 | ||
2a365505 TR |
510 | port = fwspec->param[0] / 8; |
511 | pin = fwspec->param[0] % 8; | |
5b2b135a | 512 | |
2a365505 | 513 | if (port >= gpio->soc->num_ports) |
5b2b135a | 514 | return -EINVAL; |
5b2b135a TR |
515 | |
516 | for (i = 0; i < port; i++) | |
517 | offset += gpio->soc->ports[i].pins; | |
518 | ||
2a365505 | 519 | *type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK; |
5b2b135a TR |
520 | *hwirq = offset + pin; |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
24258761 | 525 | static void *tegra186_gpio_populate_parent_fwspec(struct gpio_chip *chip, |
2a365505 TR |
526 | unsigned int parent_hwirq, |
527 | unsigned int parent_type) | |
528 | { | |
529 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
24258761 | 530 | struct irq_fwspec *fwspec; |
2a365505 | 531 | |
24258761 KH |
532 | fwspec = kmalloc(sizeof(*fwspec), GFP_KERNEL); |
533 | if (!fwspec) | |
534 | return NULL; | |
535 | ||
536 | fwspec->fwnode = chip->irq.parent_domain->fwnode; | |
2a365505 TR |
537 | fwspec->param_count = 3; |
538 | fwspec->param[0] = gpio->soc->instance; | |
539 | fwspec->param[1] = parent_hwirq; | |
540 | fwspec->param[2] = parent_type; | |
24258761 KH |
541 | |
542 | return fwspec; | |
2a365505 TR |
543 | } |
544 | ||
545 | static int tegra186_gpio_child_to_parent_hwirq(struct gpio_chip *chip, | |
546 | unsigned int hwirq, | |
547 | unsigned int type, | |
548 | unsigned int *parent_hwirq, | |
549 | unsigned int *parent_type) | |
550 | { | |
551 | *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); | |
552 | *parent_type = type; | |
553 | ||
554 | return 0; | |
555 | } | |
556 | ||
557 | static unsigned int tegra186_gpio_child_offset_to_irq(struct gpio_chip *chip, | |
558 | unsigned int offset) | |
559 | { | |
560 | struct tegra_gpio *gpio = gpiochip_get_data(chip); | |
561 | unsigned int i; | |
562 | ||
563 | for (i = 0; i < gpio->soc->num_ports; i++) { | |
564 | if (offset < gpio->soc->ports[i].pins) | |
565 | break; | |
566 | ||
567 | offset -= gpio->soc->ports[i].pins; | |
568 | } | |
569 | ||
570 | return offset + i * 8; | |
571 | } | |
572 | ||
573 | static const struct of_device_id tegra186_pmc_of_match[] = { | |
574 | { .compatible = "nvidia,tegra186-pmc" }, | |
575 | { .compatible = "nvidia,tegra194-pmc" }, | |
576 | { /* sentinel */ } | |
5b2b135a TR |
577 | }; |
578 | ||
22635ed8 TR |
579 | static void tegra186_gpio_init_route_mapping(struct tegra_gpio *gpio) |
580 | { | |
581 | unsigned int i, j; | |
582 | u32 value; | |
583 | ||
584 | for (i = 0; i < gpio->soc->num_ports; i++) { | |
585 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; | |
586 | unsigned int offset, p = port->port; | |
587 | void __iomem *base; | |
588 | ||
589 | base = gpio->secure + port->bank * 0x1000 + 0x800; | |
590 | ||
591 | value = readl(base + TEGRA186_GPIO_CTL_SCR); | |
592 | ||
593 | /* | |
594 | * For controllers that haven't been locked down yet, make | |
595 | * sure to program the default interrupt route mapping. | |
596 | */ | |
597 | if ((value & TEGRA186_GPIO_CTL_SCR_SEC_REN) == 0 && | |
598 | (value & TEGRA186_GPIO_CTL_SCR_SEC_WEN) == 0) { | |
599 | for (j = 0; j < 8; j++) { | |
600 | offset = TEGRA186_GPIO_INT_ROUTE_MAPPING(p, j); | |
601 | ||
602 | value = readl(base + offset); | |
603 | value = BIT(port->pins) - 1; | |
604 | writel(value, base + offset); | |
605 | } | |
606 | } | |
607 | } | |
608 | } | |
609 | ||
5b2b135a TR |
610 | static int tegra186_gpio_probe(struct platform_device *pdev) |
611 | { | |
612 | unsigned int i, j, offset; | |
613 | struct gpio_irq_chip *irq; | |
614 | struct tegra_gpio *gpio; | |
2a365505 | 615 | struct device_node *np; |
5b2b135a TR |
616 | char **names; |
617 | int err; | |
618 | ||
619 | gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); | |
620 | if (!gpio) | |
621 | return -ENOMEM; | |
622 | ||
623 | gpio->soc = of_device_get_match_data(&pdev->dev); | |
624 | ||
22635ed8 TR |
625 | gpio->secure = devm_platform_ioremap_resource_byname(pdev, "security"); |
626 | if (IS_ERR(gpio->secure)) | |
627 | return PTR_ERR(gpio->secure); | |
628 | ||
cc4c8318 | 629 | gpio->base = devm_platform_ioremap_resource_byname(pdev, "gpio"); |
5b2b135a TR |
630 | if (IS_ERR(gpio->base)) |
631 | return PTR_ERR(gpio->base); | |
632 | ||
633 | err = platform_irq_count(pdev); | |
634 | if (err < 0) | |
635 | return err; | |
636 | ||
637 | gpio->num_irq = err; | |
638 | ||
639 | gpio->irq = devm_kcalloc(&pdev->dev, gpio->num_irq, sizeof(*gpio->irq), | |
640 | GFP_KERNEL); | |
641 | if (!gpio->irq) | |
642 | return -ENOMEM; | |
643 | ||
644 | for (i = 0; i < gpio->num_irq; i++) { | |
645 | err = platform_get_irq(pdev, i); | |
646 | if (err < 0) | |
647 | return err; | |
648 | ||
649 | gpio->irq[i] = err; | |
650 | } | |
651 | ||
652 | gpio->gpio.label = gpio->soc->name; | |
653 | gpio->gpio.parent = &pdev->dev; | |
654 | ||
b64d6c9a TR |
655 | gpio->gpio.request = gpiochip_generic_request; |
656 | gpio->gpio.free = gpiochip_generic_free; | |
5b2b135a TR |
657 | gpio->gpio.get_direction = tegra186_gpio_get_direction; |
658 | gpio->gpio.direction_input = tegra186_gpio_direction_input; | |
659 | gpio->gpio.direction_output = tegra186_gpio_direction_output; | |
660 | gpio->gpio.get = tegra186_gpio_get, | |
661 | gpio->gpio.set = tegra186_gpio_set; | |
adce1183 | 662 | gpio->gpio.set_config = tegra186_gpio_set_config; |
b64d6c9a | 663 | gpio->gpio.add_pin_ranges = tegra186_gpio_add_pin_ranges; |
5b2b135a TR |
664 | |
665 | gpio->gpio.base = -1; | |
666 | ||
667 | for (i = 0; i < gpio->soc->num_ports; i++) | |
668 | gpio->gpio.ngpio += gpio->soc->ports[i].pins; | |
669 | ||
670 | names = devm_kcalloc(gpio->gpio.parent, gpio->gpio.ngpio, | |
671 | sizeof(*names), GFP_KERNEL); | |
672 | if (!names) | |
673 | return -ENOMEM; | |
674 | ||
675 | for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { | |
676 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; | |
677 | char *name; | |
678 | ||
679 | for (j = 0; j < port->pins; j++) { | |
680 | name = devm_kasprintf(gpio->gpio.parent, GFP_KERNEL, | |
681 | "P%s.%02x", port->name, j); | |
682 | if (!name) | |
683 | return -ENOMEM; | |
684 | ||
685 | names[offset + j] = name; | |
686 | } | |
687 | ||
688 | offset += port->pins; | |
689 | } | |
690 | ||
691 | gpio->gpio.names = (const char * const *)names; | |
692 | ||
693 | gpio->gpio.of_node = pdev->dev.of_node; | |
694 | gpio->gpio.of_gpio_n_cells = 2; | |
695 | gpio->gpio.of_xlate = tegra186_gpio_of_xlate; | |
696 | ||
697 | gpio->intc.name = pdev->dev.of_node->name; | |
698 | gpio->intc.irq_ack = tegra186_irq_ack; | |
699 | gpio->intc.irq_mask = tegra186_irq_mask; | |
700 | gpio->intc.irq_unmask = tegra186_irq_unmask; | |
701 | gpio->intc.irq_set_type = tegra186_irq_set_type; | |
986ec63d | 702 | gpio->intc.irq_set_wake = tegra186_irq_set_wake; |
c4e1f7d9 | 703 | gpio->intc.irq_set_affinity = tegra186_irq_set_affinity; |
5b2b135a TR |
704 | |
705 | irq = &gpio->gpio.irq; | |
706 | irq->chip = &gpio->intc; | |
2a365505 TR |
707 | irq->fwnode = of_node_to_fwnode(pdev->dev.of_node); |
708 | irq->child_to_parent_hwirq = tegra186_gpio_child_to_parent_hwirq; | |
24258761 | 709 | irq->populate_parent_alloc_arg = tegra186_gpio_populate_parent_fwspec; |
2a365505 TR |
710 | irq->child_offset_to_irq = tegra186_gpio_child_offset_to_irq; |
711 | irq->child_irq_domain_ops.translate = tegra186_gpio_irq_domain_translate; | |
5b2b135a | 712 | irq->handler = handle_simple_irq; |
5b2b135a TR |
713 | irq->default_type = IRQ_TYPE_NONE; |
714 | irq->parent_handler = tegra186_gpio_irq; | |
715 | irq->parent_handler_data = gpio; | |
716 | irq->num_parents = gpio->num_irq; | |
717 | irq->parents = gpio->irq; | |
718 | ||
2a365505 TR |
719 | np = of_find_matching_node(NULL, tegra186_pmc_of_match); |
720 | if (np) { | |
721 | irq->parent_domain = irq_find_host(np); | |
722 | of_node_put(np); | |
723 | ||
724 | if (!irq->parent_domain) | |
725 | return -EPROBE_DEFER; | |
726 | } | |
727 | ||
22635ed8 TR |
728 | tegra186_gpio_init_route_mapping(gpio); |
729 | ||
5b2b135a TR |
730 | irq->map = devm_kcalloc(&pdev->dev, gpio->gpio.ngpio, |
731 | sizeof(*irq->map), GFP_KERNEL); | |
732 | if (!irq->map) | |
733 | return -ENOMEM; | |
734 | ||
735 | for (i = 0, offset = 0; i < gpio->soc->num_ports; i++) { | |
736 | const struct tegra_gpio_port *port = &gpio->soc->ports[i]; | |
737 | ||
738 | for (j = 0; j < port->pins; j++) | |
13a62a56 | 739 | irq->map[offset + j] = irq->parents[port->bank]; |
5b2b135a TR |
740 | |
741 | offset += port->pins; | |
742 | } | |
743 | ||
744 | platform_set_drvdata(pdev, gpio); | |
745 | ||
746 | err = devm_gpiochip_add_data(&pdev->dev, &gpio->gpio, gpio); | |
747 | if (err < 0) | |
748 | return err; | |
749 | ||
750 | return 0; | |
751 | } | |
752 | ||
753 | static int tegra186_gpio_remove(struct platform_device *pdev) | |
754 | { | |
755 | return 0; | |
756 | } | |
757 | ||
13a62a56 TR |
758 | #define TEGRA186_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ |
759 | [TEGRA186_MAIN_GPIO_PORT_##_name] = { \ | |
760 | .name = #_name, \ | |
761 | .bank = _bank, \ | |
762 | .port = _port, \ | |
763 | .pins = _pins, \ | |
5b2b135a TR |
764 | } |
765 | ||
766 | static const struct tegra_gpio_port tegra186_main_ports[] = { | |
13a62a56 TR |
767 | TEGRA186_MAIN_GPIO_PORT( A, 2, 0, 7), |
768 | TEGRA186_MAIN_GPIO_PORT( B, 3, 0, 7), | |
769 | TEGRA186_MAIN_GPIO_PORT( C, 3, 1, 7), | |
770 | TEGRA186_MAIN_GPIO_PORT( D, 3, 2, 6), | |
771 | TEGRA186_MAIN_GPIO_PORT( E, 2, 1, 8), | |
772 | TEGRA186_MAIN_GPIO_PORT( F, 2, 2, 6), | |
773 | TEGRA186_MAIN_GPIO_PORT( G, 4, 1, 6), | |
774 | TEGRA186_MAIN_GPIO_PORT( H, 1, 0, 7), | |
775 | TEGRA186_MAIN_GPIO_PORT( I, 0, 4, 8), | |
776 | TEGRA186_MAIN_GPIO_PORT( J, 5, 0, 8), | |
777 | TEGRA186_MAIN_GPIO_PORT( K, 5, 1, 1), | |
778 | TEGRA186_MAIN_GPIO_PORT( L, 1, 1, 8), | |
779 | TEGRA186_MAIN_GPIO_PORT( M, 5, 3, 6), | |
780 | TEGRA186_MAIN_GPIO_PORT( N, 0, 0, 7), | |
781 | TEGRA186_MAIN_GPIO_PORT( O, 0, 1, 4), | |
782 | TEGRA186_MAIN_GPIO_PORT( P, 4, 0, 7), | |
783 | TEGRA186_MAIN_GPIO_PORT( Q, 0, 2, 6), | |
784 | TEGRA186_MAIN_GPIO_PORT( R, 0, 5, 6), | |
785 | TEGRA186_MAIN_GPIO_PORT( T, 0, 3, 4), | |
786 | TEGRA186_MAIN_GPIO_PORT( X, 1, 2, 8), | |
787 | TEGRA186_MAIN_GPIO_PORT( Y, 1, 3, 7), | |
788 | TEGRA186_MAIN_GPIO_PORT(BB, 2, 3, 2), | |
789 | TEGRA186_MAIN_GPIO_PORT(CC, 5, 2, 4), | |
5b2b135a TR |
790 | }; |
791 | ||
792 | static const struct tegra_gpio_soc tegra186_main_soc = { | |
793 | .num_ports = ARRAY_SIZE(tegra186_main_ports), | |
794 | .ports = tegra186_main_ports, | |
795 | .name = "tegra186-gpio", | |
2a365505 | 796 | .instance = 0, |
5b2b135a TR |
797 | }; |
798 | ||
13a62a56 TR |
799 | #define TEGRA186_AON_GPIO_PORT(_name, _bank, _port, _pins) \ |
800 | [TEGRA186_AON_GPIO_PORT_##_name] = { \ | |
801 | .name = #_name, \ | |
802 | .bank = _bank, \ | |
803 | .port = _port, \ | |
804 | .pins = _pins, \ | |
5b2b135a TR |
805 | } |
806 | ||
807 | static const struct tegra_gpio_port tegra186_aon_ports[] = { | |
13a62a56 TR |
808 | TEGRA186_AON_GPIO_PORT( S, 0, 1, 5), |
809 | TEGRA186_AON_GPIO_PORT( U, 0, 2, 6), | |
810 | TEGRA186_AON_GPIO_PORT( V, 0, 4, 8), | |
811 | TEGRA186_AON_GPIO_PORT( W, 0, 5, 8), | |
812 | TEGRA186_AON_GPIO_PORT( Z, 0, 7, 4), | |
813 | TEGRA186_AON_GPIO_PORT(AA, 0, 6, 8), | |
814 | TEGRA186_AON_GPIO_PORT(EE, 0, 3, 3), | |
815 | TEGRA186_AON_GPIO_PORT(FF, 0, 0, 5), | |
5b2b135a TR |
816 | }; |
817 | ||
818 | static const struct tegra_gpio_soc tegra186_aon_soc = { | |
819 | .num_ports = ARRAY_SIZE(tegra186_aon_ports), | |
820 | .ports = tegra186_aon_ports, | |
821 | .name = "tegra186-gpio-aon", | |
2a365505 | 822 | .instance = 1, |
5b2b135a TR |
823 | }; |
824 | ||
13a62a56 TR |
825 | #define TEGRA194_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ |
826 | [TEGRA194_MAIN_GPIO_PORT_##_name] = { \ | |
827 | .name = #_name, \ | |
828 | .bank = _bank, \ | |
829 | .port = _port, \ | |
830 | .pins = _pins, \ | |
bac5c3b8 MP |
831 | } |
832 | ||
833 | static const struct tegra_gpio_port tegra194_main_ports[] = { | |
13a62a56 TR |
834 | TEGRA194_MAIN_GPIO_PORT( A, 1, 2, 8), |
835 | TEGRA194_MAIN_GPIO_PORT( B, 4, 7, 2), | |
836 | TEGRA194_MAIN_GPIO_PORT( C, 4, 3, 8), | |
837 | TEGRA194_MAIN_GPIO_PORT( D, 4, 4, 4), | |
838 | TEGRA194_MAIN_GPIO_PORT( E, 4, 5, 8), | |
839 | TEGRA194_MAIN_GPIO_PORT( F, 4, 6, 6), | |
840 | TEGRA194_MAIN_GPIO_PORT( G, 4, 0, 8), | |
841 | TEGRA194_MAIN_GPIO_PORT( H, 4, 1, 8), | |
842 | TEGRA194_MAIN_GPIO_PORT( I, 4, 2, 5), | |
843 | TEGRA194_MAIN_GPIO_PORT( J, 5, 1, 6), | |
844 | TEGRA194_MAIN_GPIO_PORT( K, 3, 0, 8), | |
845 | TEGRA194_MAIN_GPIO_PORT( L, 3, 1, 4), | |
846 | TEGRA194_MAIN_GPIO_PORT( M, 2, 3, 8), | |
847 | TEGRA194_MAIN_GPIO_PORT( N, 2, 4, 3), | |
848 | TEGRA194_MAIN_GPIO_PORT( O, 5, 0, 6), | |
849 | TEGRA194_MAIN_GPIO_PORT( P, 2, 5, 8), | |
850 | TEGRA194_MAIN_GPIO_PORT( Q, 2, 6, 8), | |
851 | TEGRA194_MAIN_GPIO_PORT( R, 2, 7, 6), | |
852 | TEGRA194_MAIN_GPIO_PORT( S, 3, 3, 8), | |
853 | TEGRA194_MAIN_GPIO_PORT( T, 3, 4, 8), | |
854 | TEGRA194_MAIN_GPIO_PORT( U, 3, 5, 1), | |
855 | TEGRA194_MAIN_GPIO_PORT( V, 1, 0, 8), | |
856 | TEGRA194_MAIN_GPIO_PORT( W, 1, 1, 2), | |
857 | TEGRA194_MAIN_GPIO_PORT( X, 2, 0, 8), | |
858 | TEGRA194_MAIN_GPIO_PORT( Y, 2, 1, 8), | |
859 | TEGRA194_MAIN_GPIO_PORT( Z, 2, 2, 8), | |
860 | TEGRA194_MAIN_GPIO_PORT(FF, 3, 2, 2), | |
861 | TEGRA194_MAIN_GPIO_PORT(GG, 0, 0, 2) | |
bac5c3b8 MP |
862 | }; |
863 | ||
ffa91e7c TR |
864 | static const struct tegra186_pin_range tegra194_main_pin_ranges[] = { |
865 | { TEGRA194_MAIN_GPIO(GG, 0), "pex_l5_clkreq_n_pgg0" }, | |
866 | { TEGRA194_MAIN_GPIO(GG, 1), "pex_l5_rst_n_pgg1" }, | |
867 | }; | |
868 | ||
bac5c3b8 MP |
869 | static const struct tegra_gpio_soc tegra194_main_soc = { |
870 | .num_ports = ARRAY_SIZE(tegra194_main_ports), | |
871 | .ports = tegra194_main_ports, | |
872 | .name = "tegra194-gpio", | |
2a365505 | 873 | .instance = 0, |
ffa91e7c TR |
874 | .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), |
875 | .pin_ranges = tegra194_main_pin_ranges, | |
876 | .pinmux = "nvidia,tegra194-pinmux", | |
bac5c3b8 MP |
877 | }; |
878 | ||
13a62a56 TR |
879 | #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ |
880 | [TEGRA194_AON_GPIO_PORT_##_name] = { \ | |
881 | .name = #_name, \ | |
882 | .bank = _bank, \ | |
883 | .port = _port, \ | |
884 | .pins = _pins, \ | |
bac5c3b8 MP |
885 | } |
886 | ||
887 | static const struct tegra_gpio_port tegra194_aon_ports[] = { | |
13a62a56 TR |
888 | TEGRA194_AON_GPIO_PORT(AA, 0, 3, 8), |
889 | TEGRA194_AON_GPIO_PORT(BB, 0, 4, 4), | |
890 | TEGRA194_AON_GPIO_PORT(CC, 0, 1, 8), | |
891 | TEGRA194_AON_GPIO_PORT(DD, 0, 2, 3), | |
892 | TEGRA194_AON_GPIO_PORT(EE, 0, 0, 7) | |
bac5c3b8 MP |
893 | }; |
894 | ||
895 | static const struct tegra_gpio_soc tegra194_aon_soc = { | |
896 | .num_ports = ARRAY_SIZE(tegra194_aon_ports), | |
897 | .ports = tegra194_aon_ports, | |
898 | .name = "tegra194-gpio-aon", | |
2a365505 | 899 | .instance = 1, |
bac5c3b8 MP |
900 | }; |
901 | ||
5b2b135a TR |
902 | static const struct of_device_id tegra186_gpio_of_match[] = { |
903 | { | |
904 | .compatible = "nvidia,tegra186-gpio", | |
905 | .data = &tegra186_main_soc | |
906 | }, { | |
907 | .compatible = "nvidia,tegra186-gpio-aon", | |
908 | .data = &tegra186_aon_soc | |
bac5c3b8 MP |
909 | }, { |
910 | .compatible = "nvidia,tegra194-gpio", | |
911 | .data = &tegra194_main_soc | |
912 | }, { | |
913 | .compatible = "nvidia,tegra194-gpio-aon", | |
914 | .data = &tegra194_aon_soc | |
5b2b135a TR |
915 | }, { |
916 | /* sentinel */ | |
917 | } | |
918 | }; | |
fef2d3bb | 919 | MODULE_DEVICE_TABLE(of, tegra186_gpio_of_match); |
5b2b135a TR |
920 | |
921 | static struct platform_driver tegra186_gpio_driver = { | |
922 | .driver = { | |
923 | .name = "tegra186-gpio", | |
924 | .of_match_table = tegra186_gpio_of_match, | |
925 | }, | |
926 | .probe = tegra186_gpio_probe, | |
927 | .remove = tegra186_gpio_remove, | |
928 | }; | |
929 | module_platform_driver(tegra186_gpio_driver); | |
930 | ||
931 | MODULE_DESCRIPTION("NVIDIA Tegra186 GPIO controller driver"); | |
932 | MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); | |
933 | MODULE_LICENSE("GPL v2"); |