[linux-2.6-block.git] / drivers / gpio / gpio-tegra.c

/*
 * arch/arm/mach-tegra/gpio.c
 *
 * Copyright (c) 2010 Google, Inc
 *
 * Author:
 *	Erik Gilling <konkers@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/irqdomain.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>

#define GPIO_BANK(x)		((x) >> 5)
#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
#define GPIO_BIT(x)		((x) & 0x7)

#define GPIO_REG(x)		(GPIO_BANK(x) * tegra_gpio_bank_stride + \
					GPIO_PORT(x) * 4)

#define GPIO_CNF(x)		(GPIO_REG(x) + 0x00)
#define GPIO_OE(x)		(GPIO_REG(x) + 0x10)
#define GPIO_OUT(x)		(GPIO_REG(x) + 0X20)
#define GPIO_IN(x)		(GPIO_REG(x) + 0x30)
#define GPIO_INT_STA(x)		(GPIO_REG(x) + 0x40)
#define GPIO_INT_ENB(x)		(GPIO_REG(x) + 0x50)
#define GPIO_INT_LVL(x)		(GPIO_REG(x) + 0x60)
#define GPIO_INT_CLR(x)		(GPIO_REG(x) + 0x70)

#define GPIO_MSK_CNF(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
#define GPIO_MSK_OE(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
#define GPIO_MSK_OUT(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
#define GPIO_MSK_INT_STA(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
#define GPIO_MSK_INT_ENB(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
#define GPIO_MSK_INT_LVL(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)

#define GPIO_INT_LVL_MASK		0x010101
#define GPIO_INT_LVL_EDGE_RISING	0x000101
#define GPIO_INT_LVL_EDGE_FALLING	0x000100
#define GPIO_INT_LVL_EDGE_BOTH		0x010100
#define GPIO_INT_LVL_LEVEL_HIGH		0x000001
#define GPIO_INT_LVL_LEVEL_LOW		0x000000

struct tegra_gpio_bank {
	int bank;
	int irq;
	spinlock_t lvl_lock[4];
#ifdef CONFIG_PM_SLEEP
	u32 cnf[4];
	u32 out[4];
	u32 oe[4];
	u32 int_enb[4];
	u32 int_lvl[4];
	u32 wake_enb[4];
#endif
};

static struct device *dev;
static struct irq_domain *irq_domain;
static void __iomem *regs;
static u32 tegra_gpio_bank_count;
static u32 tegra_gpio_bank_stride;
static u32 tegra_gpio_upper_offset;
static struct tegra_gpio_bank *tegra_gpio_banks;

static inline void tegra_gpio_writel(u32 val, u32 reg)
{
	__raw_writel(val, regs + reg);
}

static inline u32 tegra_gpio_readl(u32 reg)
{
	return __raw_readl(regs + reg);
}

static int tegra_gpio_compose(int bank, int port, int bit)
{
	return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
}

static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
{
	u32 val;

	val = 0x100 << GPIO_BIT(gpio);
	if (value)
		val |= 1 << GPIO_BIT(gpio);
	tegra_gpio_writel(val, reg);
}

static void tegra_gpio_enable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
}

static void tegra_gpio_disable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
}

static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	return pinctrl_request_gpio(offset);
}

static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	pinctrl_free_gpio(offset);
	tegra_gpio_disable(offset);
}

static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
}

static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	/* If gpio is in output mode then read from the out value */
	if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
		return (tegra_gpio_readl(GPIO_OUT(offset)) >>
				GPIO_BIT(offset)) & 0x1;

	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
}

static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
	tegra_gpio_enable(offset);
	return 0;
}

static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
					int value)
{
	tegra_gpio_set(chip, offset, value);
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
	tegra_gpio_enable(offset);
	return 0;
}

static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return irq_find_mapping(irq_domain, offset);
}

static struct gpio_chip tegra_gpio_chip = {
	.label			= "tegra-gpio",
	.request		= tegra_gpio_request,
	.free			= tegra_gpio_free,
	.direction_input	= tegra_gpio_direction_input,
	.get			= tegra_gpio_get,
	.direction_output	= tegra_gpio_direction_output,
	.set			= tegra_gpio_set,
	.to_irq			= tegra_gpio_to_irq,
	.base			= 0,
};

static void tegra_gpio_irq_ack(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
}

static void tegra_gpio_irq_mask(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
}

static void tegra_gpio_irq_unmask(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
}

static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	int gpio = d->hwirq;
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	int port = GPIO_PORT(gpio);
	int lvl_type;
	int val;
	unsigned long flags;
	int ret;

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_RISING:
		lvl_type = GPIO_INT_LVL_EDGE_RISING;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		lvl_type = GPIO_INT_LVL_EDGE_FALLING;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		lvl_type = GPIO_INT_LVL_EDGE_BOTH;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		lvl_type = GPIO_INT_LVL_LEVEL_LOW;
		break;

	default:
		return -EINVAL;
	}

	ret = gpiochip_lock_as_irq(&tegra_gpio_chip, gpio);
	if (ret) {
		dev_err(dev, "unable to lock Tegra GPIO %d as IRQ\n", gpio);
		return ret;
	}

	spin_lock_irqsave(&bank->lvl_lock[port], flags);

	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
	val |= lvl_type << GPIO_BIT(gpio);
	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));

	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);

	tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
	tegra_gpio_enable(gpio);

	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		__irq_set_handler_locked(d->irq, handle_level_irq);
	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		__irq_set_handler_locked(d->irq, handle_edge_irq);

	return 0;
}

static void tegra_gpio_irq_shutdown(struct irq_data *d)
{
	int gpio = d->hwirq;

	gpiochip_unlock_as_irq(&tegra_gpio_chip, gpio);
}

static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	struct tegra_gpio_bank *bank;
	int port;
	int pin;
	int unmasked = 0;
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	bank = irq_get_handler_data(irq);

	for (port = 0; port < 4; port++) {
		int gpio = tegra_gpio_compose(bank->bank, port, 0);
		unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
			tegra_gpio_readl(GPIO_INT_ENB(gpio));
		u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));

		for_each_set_bit(pin, &sta, 8) {
			tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));

			/* if gpio is edge triggered, clear condition
			 * before executing the hander so that we don't
			 * miss edges
			 */
			if (lvl & (0x100 << pin)) {
				unmasked = 1;
				chained_irq_exit(chip, desc);
			}

			generic_handle_irq(gpio_to_irq(gpio + pin));
		}
	}

	if (!unmasked)
		chained_irq_exit(chip, desc);

}

#ifdef CONFIG_PM_SLEEP
static int tegra_gpio_resume(struct device *dev)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);

	for (b = 0; b < tegra_gpio_bank_count; b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
			tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
			tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
			tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
			tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
		}
	}

	local_irq_restore(flags);
	return 0;
}

static int tegra_gpio_suspend(struct device *dev)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);
	for (b = 0; b < tegra_gpio_bank_count; b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
			bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
			bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
			bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
			bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));

			/* Enable gpio irq for wake up source */
			tegra_gpio_writel(bank->wake_enb[p],
					  GPIO_INT_ENB(gpio));
		}
	}
	local_irq_restore(flags);
	return 0;
}

static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
{
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	int gpio = d->hwirq;
	u32 port, bit, mask;

	port = GPIO_PORT(gpio);
	bit = GPIO_BIT(gpio);
	mask = BIT(bit);

	if (enable)
		bank->wake_enb[port] |= mask;
	else
		bank->wake_enb[port] &= ~mask;

	return irq_set_irq_wake(bank->irq, enable);
}
#endif

static struct irq_chip tegra_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= tegra_gpio_irq_ack,
	.irq_mask	= tegra_gpio_irq_mask,
	.irq_unmask	= tegra_gpio_irq_unmask,
	.irq_set_type	= tegra_gpio_irq_set_type,
	.irq_shutdown	= tegra_gpio_irq_shutdown,
#ifdef CONFIG_PM_SLEEP
	.irq_set_wake	= tegra_gpio_irq_set_wake,
#endif
};

static const struct dev_pm_ops tegra_gpio_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
};

struct tegra_gpio_soc_config {
	u32 bank_stride;
	u32 upper_offset;
};

static struct tegra_gpio_soc_config tegra20_gpio_config = {
	.bank_stride = 0x80,
	.upper_offset = 0x800,
};

static struct tegra_gpio_soc_config tegra30_gpio_config = {
	.bank_stride = 0x100,
	.upper_offset = 0x80,
};

static const struct of_device_id tegra_gpio_of_match[] = {
	{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
	{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
	{ },
};

/* This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

static int tegra_gpio_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct tegra_gpio_soc_config *config;
	struct resource *res;
	struct tegra_gpio_bank *bank;
	int ret;
	int gpio;
	int i;
	int j;

	dev = &pdev->dev;

	match = of_match_device(tegra_gpio_of_match, &pdev->dev);
	if (!match) {
		dev_err(&pdev->dev, "Error: No device match found\n");
		return -ENODEV;
	}
	config = (struct tegra_gpio_soc_config *)match->data;

	tegra_gpio_bank_stride = config->bank_stride;
	tegra_gpio_upper_offset = config->upper_offset;

	for (;;) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
		if (!res)
			break;
		tegra_gpio_bank_count++;
	}
	if (!tegra_gpio_bank_count) {
		dev_err(&pdev->dev, "Missing IRQ resource\n");
		return -ENODEV;
	}

	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;

	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
			tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
			GFP_KERNEL);
	if (!tegra_gpio_banks)
		return -ENODEV;

	irq_domain = irq_domain_add_linear(pdev->dev.of_node,
					   tegra_gpio_chip.ngpio,
					   &irq_domain_simple_ops, NULL);
	if (!irq_domain)
		return -ENODEV;

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
		if (!res) {
			dev_err(&pdev->dev, "Missing IRQ resource\n");
			return -ENODEV;
		}

		bank = &tegra_gpio_banks[i];
		bank->bank = i;
		bank->irq = res->start;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
		}
	}

	tegra_gpio_chip.of_node = pdev->dev.of_node;

	ret = gpiochip_add(&tegra_gpio_chip);
	if (ret < 0) {
		irq_domain_remove(irq_domain);
		return ret;
	}

	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
		int irq = irq_create_mapping(irq_domain, gpio);
		/* No validity check; all Tegra GPIOs are valid IRQs */

		bank = &tegra_gpio_banks[GPIO_BANK(gpio)];

		irq_set_lockdep_class(irq, &gpio_lock_class);
		irq_set_chip_data(irq, bank);
		irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
					 handle_simple_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		bank = &tegra_gpio_banks[i];

		irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
		irq_set_handler_data(bank->irq, bank);

		for (j = 0; j < 4; j++)
			spin_lock_init(&bank->lvl_lock[j]);
	}

	return 0;
}

static struct platform_driver tegra_gpio_driver = {
	.driver		= {
		.name	= "tegra-gpio",
		.pm	= &tegra_gpio_pm_ops,
		.of_match_table = tegra_gpio_of_match,
	},
	.probe		= tegra_gpio_probe,
};

static int __init tegra_gpio_init(void)
{
	return platform_driver_register(&tegra_gpio_driver);
}
postcore_initcall(tegra_gpio_init);

#ifdef	CONFIG_DEBUG_FS

#include <linux/debugfs.h>
#include <linux/seq_file.h>

static int dbg_gpio_show(struct seq_file *s, void *unused)
{
	int i;
	int j;

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			seq_printf(s,
				"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
				i, j,
				tegra_gpio_readl(GPIO_CNF(gpio)),
				tegra_gpio_readl(GPIO_OE(gpio)),
				tegra_gpio_readl(GPIO_OUT(gpio)),
				tegra_gpio_readl(GPIO_IN(gpio)),
				tegra_gpio_readl(GPIO_INT_STA(gpio)),
				tegra_gpio_readl(GPIO_INT_ENB(gpio)),
				tegra_gpio_readl(GPIO_INT_LVL(gpio)));
		}
	}
	return 0;
}

static int dbg_gpio_open(struct inode *inode, struct file *file)
{
	return single_open(file, dbg_gpio_show, &inode->i_private);
}

static const struct file_operations debug_fops = {
	.open		= dbg_gpio_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init tegra_gpio_debuginit(void)
{
	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
					NULL, NULL, &debug_fops);
	return 0;
}
late_initcall(tegra_gpio_debuginit);
#endif
Commit	Line	Data
3c92db9a EG	1	/*
	2	* arch/arm/mach-tegra/gpio.c
	3	*
	4	* Copyright (c) 2010 Google, Inc
	5	*
	6	* Author:
	7	* Erik Gilling <konkers@google.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
641d0342	20	#include <linux/err.h>
3c92db9a EG	21	#include <linux/init.h>
3c92db9a EG	22	#include <linux/irq.h>
2e47b8b3	23	#include <linux/interrupt.h>
3c92db9a EG	24	#include <linux/io.h>
3c92db9a EG	25	#include <linux/gpio.h>
5c1e2c9d	26	#include <linux/of_device.h>
88d8951e SW	27	#include <linux/platform_device.h>
88d8951e SW	28	#include <linux/module.h>
6f74dc9b	29	#include <linux/irqdomain.h>
de88cbb7	30	#include <linux/irqchip/chained_irq.h>
3e215d0a	31	#include <linux/pinctrl/consumer.h>
8939ddc7	32	#include <linux/pm.h>
3c92db9a	33
3c92db9a EG	34	#define GPIO_BANK(x) ((x) >> 5)
	35	#define GPIO_PORT(x) (((x) >> 3) & 0x3)
	36	#define GPIO_BIT(x) ((x) & 0x7)
	37
5c1e2c9d SW	38	#define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \
5c1e2c9d SW	39	GPIO_PORT(x) * 4)
3c92db9a EG	40
	41	#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
	42	#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
	43	#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
	44	#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
	45	#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
	46	#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
	47	#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
	48	#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
	49
5c1e2c9d SW	50	#define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
	51	#define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
	52	#define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
	53	#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
	54	#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
	55	#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
3c92db9a EG	56
	57	#define GPIO_INT_LVL_MASK 0x010101
	58	#define GPIO_INT_LVL_EDGE_RISING 0x000101
	59	#define GPIO_INT_LVL_EDGE_FALLING 0x000100
	60	#define GPIO_INT_LVL_EDGE_BOTH 0x010100
	61	#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
	62	#define GPIO_INT_LVL_LEVEL_LOW 0x000000
	63
	64	struct tegra_gpio_bank {
	65	int bank;
	66	int irq;
	67	spinlock_t lvl_lock[4];
8939ddc7	68	#ifdef CONFIG_PM_SLEEP
2e47b8b3 CC	69	u32 cnf[4];
	70	u32 out[4];
	71	u32 oe[4];
	72	u32 int_enb[4];
	73	u32 int_lvl[4];
203f31cb	74	u32 wake_enb[4];
2e47b8b3	75	#endif
3c92db9a EG	76	};
3c92db9a EG	77
df231f28	78	static struct device *dev;
bdc93a77	79	static struct irq_domain *irq_domain;
88d8951e	80	static void __iomem *regs;
3391811c	81	static u32 tegra_gpio_bank_count;
5c1e2c9d SW	82	static u32 tegra_gpio_bank_stride;
5c1e2c9d SW	83	static u32 tegra_gpio_upper_offset;
3391811c	84	static struct tegra_gpio_bank *tegra_gpio_banks;
88d8951e SW	85
	86	static inline void tegra_gpio_writel(u32 val, u32 reg)
	87	{
	88	__raw_writel(val, regs + reg);
	89	}
	90
	91	static inline u32 tegra_gpio_readl(u32 reg)
	92	{
	93	return __raw_readl(regs + reg);
	94	}
3c92db9a EG	95
	96	static int tegra_gpio_compose(int bank, int port, int bit)
	97	{
	98	return (bank << 5) \| ((port & 0x3) << 3) \| (bit & 0x7);
	99	}
	100
	101	static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
	102	{
	103	u32 val;
	104
	105	val = 0x100 << GPIO_BIT(gpio);
	106	if (value)
	107	val \|= 1 << GPIO_BIT(gpio);
88d8951e	108	tegra_gpio_writel(val, reg);
3c92db9a EG	109	}
3c92db9a EG	110
3e215d0a	111	static void tegra_gpio_enable(int gpio)
3c92db9a EG	112	{
	113	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
	114	}
	115
3e215d0a	116	static void tegra_gpio_disable(int gpio)
3c92db9a EG	117	{
	118	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
	119	}
	120
924a0987	121	static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
3e215d0a SW	122	{
	123	return pinctrl_request_gpio(offset);
	124	}
	125
924a0987	126	static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
3e215d0a SW	127	{
	128	pinctrl_free_gpio(offset);
	129	tegra_gpio_disable(offset);
	130	}
	131
3c92db9a EG	132	static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	133	{
	134	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
	135	}
	136
	137	static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
	138	{
195812e4 LD	139	/* If gpio is in output mode then read from the out value */
	140	if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
	141	return (tegra_gpio_readl(GPIO_OUT(offset)) >>
	142	GPIO_BIT(offset)) & 0x1;
	143
88d8951e	144	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
3c92db9a EG	145	}
	146
	147	static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	148	{
	149	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
3e215d0a	150	tegra_gpio_enable(offset);
3c92db9a EG	151	return 0;
	152	}
	153
	154	static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
	155	int value)
	156	{
	157	tegra_gpio_set(chip, offset, value);
	158	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
3e215d0a	159	tegra_gpio_enable(offset);
3c92db9a EG	160	return 0;
	161	}
	162
438a99c0 SW	163	static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
438a99c0 SW	164	{
bdc93a77	165	return irq_find_mapping(irq_domain, offset);
438a99c0	166	}
3c92db9a EG	167
	168	static struct gpio_chip tegra_gpio_chip = {
	169	.label = "tegra-gpio",
3e215d0a SW	170	.request = tegra_gpio_request,
3e215d0a SW	171	.free = tegra_gpio_free,
3c92db9a EG	172	.direction_input = tegra_gpio_direction_input,
	173	.get = tegra_gpio_get,
	174	.direction_output = tegra_gpio_direction_output,
	175	.set = tegra_gpio_set,
438a99c0	176	.to_irq = tegra_gpio_to_irq,
3c92db9a	177	.base = 0,
3c92db9a EG	178	};
3c92db9a EG	179
37337a8d	180	static void tegra_gpio_irq_ack(struct irq_data *d)
3c92db9a	181	{
6f74dc9b	182	int gpio = d->hwirq;
3c92db9a	183
88d8951e	184	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
3c92db9a EG	185	}
3c92db9a EG	186
37337a8d	187	static void tegra_gpio_irq_mask(struct irq_data *d)
3c92db9a	188	{
6f74dc9b	189	int gpio = d->hwirq;
3c92db9a EG	190
	191	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
	192	}
	193
37337a8d	194	static void tegra_gpio_irq_unmask(struct irq_data *d)
3c92db9a	195	{
6f74dc9b	196	int gpio = d->hwirq;
3c92db9a EG	197
	198	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
	199	}
	200
37337a8d	201	static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
3c92db9a	202	{
6f74dc9b	203	int gpio = d->hwirq;
37337a8d	204	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
3c92db9a EG	205	int port = GPIO_PORT(gpio);
	206	int lvl_type;
	207	int val;
	208	unsigned long flags;
df231f28	209	int ret;
3c92db9a EG	210
	211	switch (type & IRQ_TYPE_SENSE_MASK) {
	212	case IRQ_TYPE_EDGE_RISING:
	213	lvl_type = GPIO_INT_LVL_EDGE_RISING;
	214	break;
	215
	216	case IRQ_TYPE_EDGE_FALLING:
	217	lvl_type = GPIO_INT_LVL_EDGE_FALLING;
	218	break;
	219
	220	case IRQ_TYPE_EDGE_BOTH:
	221	lvl_type = GPIO_INT_LVL_EDGE_BOTH;
	222	break;
	223
	224	case IRQ_TYPE_LEVEL_HIGH:
	225	lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
	226	break;
	227
	228	case IRQ_TYPE_LEVEL_LOW:
	229	lvl_type = GPIO_INT_LVL_LEVEL_LOW;
	230	break;
	231
	232	default:
	233	return -EINVAL;
	234	}
	235
e3a2e878	236	ret = gpiochip_lock_as_irq(&tegra_gpio_chip, gpio);
df231f28 SW	237	if (ret) {
	238	dev_err(dev, "unable to lock Tegra GPIO %d as IRQ\n", gpio);
	239	return ret;
	240	}
	241
3c92db9a EG	242	spin_lock_irqsave(&bank->lvl_lock[port], flags);
3c92db9a EG	243
88d8951e	244	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
3c92db9a EG	245	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
3c92db9a EG	246	val \|= lvl_type << GPIO_BIT(gpio);
88d8951e	247	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
3c92db9a EG	248
	249	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
	250
d941136f SW	251	tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
	252	tegra_gpio_enable(gpio);
	253
3c92db9a	254	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
6845664a	255	__irq_set_handler_locked(d->irq, handle_level_irq);
3c92db9a	256	else if (type & (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
6845664a	257	__irq_set_handler_locked(d->irq, handle_edge_irq);
3c92db9a EG	258
	259	return 0;
	260	}
	261
df231f28 SW	262	static void tegra_gpio_irq_shutdown(struct irq_data *d)
	263	{
	264	int gpio = d->hwirq;
	265
e3a2e878	266	gpiochip_unlock_as_irq(&tegra_gpio_chip, gpio);
df231f28 SW	267	}
df231f28 SW	268
3c92db9a EG	269	static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
	270	{
	271	struct tegra_gpio_bank *bank;
	272	int port;
	273	int pin;
	274	int unmasked = 0;
98022940	275	struct irq_chip *chip = irq_desc_get_chip(desc);
3c92db9a	276
98022940	277	chained_irq_enter(chip, desc);
3c92db9a	278
6845664a	279	bank = irq_get_handler_data(irq);
3c92db9a EG	280
	281	for (port = 0; port < 4; port++) {
	282	int gpio = tegra_gpio_compose(bank->bank, port, 0);
88d8951e SW	283	unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
	284	tegra_gpio_readl(GPIO_INT_ENB(gpio));
	285	u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
3c92db9a EG	286
3c92db9a EG	287	for_each_set_bit(pin, &sta, 8) {
88d8951e	288	tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
3c92db9a EG	289
	290	/* if gpio is edge triggered, clear condition
	291	* before executing the hander so that we don't
	292	* miss edges
	293	*/
	294	if (lvl & (0x100 << pin)) {
	295	unmasked = 1;
98022940	296	chained_irq_exit(chip, desc);
3c92db9a EG	297	}
	298
	299	generic_handle_irq(gpio_to_irq(gpio + pin));
	300	}
	301	}
	302
	303	if (!unmasked)
98022940	304	chained_irq_exit(chip, desc);
3c92db9a EG	305
	306	}
	307
8939ddc7 LD	308	#ifdef CONFIG_PM_SLEEP
8939ddc7 LD	309	static int tegra_gpio_resume(struct device *dev)
2e47b8b3 CC	310	{
2e47b8b3 CC	311	unsigned long flags;
c8309ef6 CC	312	int b;
c8309ef6 CC	313	int p;
2e47b8b3 CC	314
	315	local_irq_save(flags);
	316
3391811c	317	for (b = 0; b < tegra_gpio_bank_count; b++) {
2e47b8b3 CC	318	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	319
	320	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	321	unsigned int gpio = (b<<5) \| (p<<3);
88d8951e SW	322	tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
	323	tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
	324	tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
	325	tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
	326	tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
2e47b8b3 CC	327	}
	328	}
	329
	330	local_irq_restore(flags);
8939ddc7	331	return 0;
2e47b8b3 CC	332	}
2e47b8b3 CC	333
8939ddc7	334	static int tegra_gpio_suspend(struct device *dev)
2e47b8b3 CC	335	{
2e47b8b3 CC	336	unsigned long flags;
c8309ef6 CC	337	int b;
c8309ef6 CC	338	int p;
2e47b8b3	339
2e47b8b3	340	local_irq_save(flags);
3391811c	341	for (b = 0; b < tegra_gpio_bank_count; b++) {
2e47b8b3 CC	342	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	343
	344	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	345	unsigned int gpio = (b<<5) \| (p<<3);
88d8951e SW	346	bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
	347	bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
	348	bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
	349	bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
	350	bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
203f31cb JL	351
	352	/* Enable gpio irq for wake up source */
	353	tegra_gpio_writel(bank->wake_enb[p],
	354	GPIO_INT_ENB(gpio));
2e47b8b3 CC	355	}
	356	}
	357	local_irq_restore(flags);
8939ddc7	358	return 0;
2e47b8b3 CC	359	}
2e47b8b3 CC	360
203f31cb	361	static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
2e47b8b3	362	{
37337a8d	363	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
203f31cb JL	364	int gpio = d->hwirq;
	365	u32 port, bit, mask;
	366
	367	port = GPIO_PORT(gpio);
	368	bit = GPIO_BIT(gpio);
	369	mask = BIT(bit);
	370
	371	if (enable)
	372	bank->wake_enb[port] \|= mask;
	373	else
	374	bank->wake_enb[port] &= ~mask;
	375
6845664a	376	return irq_set_irq_wake(bank->irq, enable);
2e47b8b3 CC	377	}
2e47b8b3 CC	378	#endif
3c92db9a EG	379
	380	static struct irq_chip tegra_gpio_irq_chip = {
	381	.name = "GPIO",
37337a8d LB	382	.irq_ack = tegra_gpio_irq_ack,
	383	.irq_mask = tegra_gpio_irq_mask,
	384	.irq_unmask = tegra_gpio_irq_unmask,
	385	.irq_set_type = tegra_gpio_irq_set_type,
df231f28	386	.irq_shutdown = tegra_gpio_irq_shutdown,
8939ddc7	387	#ifdef CONFIG_PM_SLEEP
203f31cb	388	.irq_set_wake = tegra_gpio_irq_set_wake,
2e47b8b3	389	#endif
3c92db9a EG	390	};
3c92db9a EG	391
8939ddc7 LD	392	static const struct dev_pm_ops tegra_gpio_pm_ops = {
	393	SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
	394	};
	395
5c1e2c9d SW	396	struct tegra_gpio_soc_config {
	397	u32 bank_stride;
	398	u32 upper_offset;
	399	};
	400
	401	static struct tegra_gpio_soc_config tegra20_gpio_config = {
	402	.bank_stride = 0x80,
	403	.upper_offset = 0x800,
	404	};
	405
	406	static struct tegra_gpio_soc_config tegra30_gpio_config = {
	407	.bank_stride = 0x100,
	408	.upper_offset = 0x80,
	409	};
	410
30373b63	411	static const struct of_device_id tegra_gpio_of_match[] = {
5c1e2c9d SW	412	{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
	413	{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
	414	{ },
	415	};
3c92db9a EG	416
	417	/* This lock class tells lockdep that GPIO irqs are in a different
	418	* category than their parents, so it won't report false recursion.
	419	*/
	420	static struct lock_class_key gpio_lock_class;
	421
3836309d	422	static int tegra_gpio_probe(struct platform_device *pdev)
3c92db9a	423	{
5c1e2c9d SW	424	const struct of_device_id *match;
5c1e2c9d SW	425	struct tegra_gpio_soc_config *config;
88d8951e	426	struct resource *res;
3c92db9a	427	struct tegra_gpio_bank *bank;
f57f98a6	428	int ret;
47008001	429	int gpio;
3c92db9a EG	430	int i;
	431	int j;
	432
df231f28 SW	433	dev = &pdev->dev;
df231f28 SW	434
5c1e2c9d	435	match = of_match_device(tegra_gpio_of_match, &pdev->dev);
165b6c2f SW	436	if (!match) {
	437	dev_err(&pdev->dev, "Error: No device match found\n");
	438	return -ENODEV;
	439	}
	440	config = (struct tegra_gpio_soc_config *)match->data;
5c1e2c9d SW	441
	442	tegra_gpio_bank_stride = config->bank_stride;
	443	tegra_gpio_upper_offset = config->upper_offset;
	444
3391811c SW	445	for (;;) {
	446	res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
	447	if (!res)
	448	break;
	449	tegra_gpio_bank_count++;
	450	}
	451	if (!tegra_gpio_bank_count) {
	452	dev_err(&pdev->dev, "Missing IRQ resource\n");
	453	return -ENODEV;
	454	}
	455
	456	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
	457
	458	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
	459	tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
	460	GFP_KERNEL);
c88a73b3	461	if (!tegra_gpio_banks)
3391811c	462	return -ENODEV;
3391811c	463
d0235677 LW	464	irq_domain = irq_domain_add_linear(pdev->dev.of_node,
d0235677 LW	465	tegra_gpio_chip.ngpio,
bdc93a77	466	&irq_domain_simple_ops, NULL);
d0235677 LW	467	if (!irq_domain)
d0235677 LW	468	return -ENODEV;
6f74dc9b	469
3391811c	470	for (i = 0; i < tegra_gpio_bank_count; i++) {
88d8951e SW	471	res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
	472	if (!res) {
	473	dev_err(&pdev->dev, "Missing IRQ resource\n");
	474	return -ENODEV;
	475	}
	476
	477	bank = &tegra_gpio_banks[i];
	478	bank->bank = i;
	479	bank->irq = res->start;
	480	}
	481
	482	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
641d0342 TR	483	regs = devm_ioremap_resource(&pdev->dev, res);
	484	if (IS_ERR(regs))
	485	return PTR_ERR(regs);
88d8951e	486
4a3398ee	487	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	488	for (j = 0; j < 4; j++) {
3c92db9a EG	489	int gpio = tegra_gpio_compose(i, j, 0);
88d8951e	490	tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
3c92db9a EG	491	}
	492	}
	493
88d8951e	494	tegra_gpio_chip.of_node = pdev->dev.of_node;
df221227	495
f57f98a6 SW	496	ret = gpiochip_add(&tegra_gpio_chip);
	497	if (ret < 0) {
	498	irq_domain_remove(irq_domain);
	499	return ret;
	500	}
3c92db9a	501
3391811c	502	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
d0235677	503	int irq = irq_create_mapping(irq_domain, gpio);
47008001	504	/* No validity check; all Tegra GPIOs are valid IRQs */
3c92db9a	505
47008001	506	bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
3c92db9a	507
47008001 SW	508	irq_set_lockdep_class(irq, &gpio_lock_class);
	509	irq_set_chip_data(irq, bank);
	510	irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
f38c02f3	511	handle_simple_irq);
47008001	512	set_irq_flags(irq, IRQF_VALID);
3c92db9a EG	513	}
3c92db9a EG	514
3391811c	515	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	516	bank = &tegra_gpio_banks[i];
3c92db9a EG	517
6845664a TG	518	irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
6845664a TG	519	irq_set_handler_data(bank->irq, bank);
3c92db9a EG	520
	521	for (j = 0; j < 4; j++)
	522	spin_lock_init(&bank->lvl_lock[j]);
	523	}
	524
	525	return 0;
	526	}
	527
88d8951e SW	528	static struct platform_driver tegra_gpio_driver = {
	529	.driver = {
	530	.name = "tegra-gpio",
8939ddc7	531	.pm = &tegra_gpio_pm_ops,
88d8951e SW	532	.of_match_table = tegra_gpio_of_match,
	533	},
	534	.probe = tegra_gpio_probe,
	535	};
	536
	537	static int __init tegra_gpio_init(void)
	538	{
	539	return platform_driver_register(&tegra_gpio_driver);
	540	}
3c92db9a EG	541	postcore_initcall(tegra_gpio_init);
	542
	543	#ifdef CONFIG_DEBUG_FS
	544
	545	#include <linux/debugfs.h>
	546	#include <linux/seq_file.h>
	547
	548	static int dbg_gpio_show(struct seq_file s, void unused)
	549	{
	550	int i;
	551	int j;
	552
4a3398ee	553	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	554	for (j = 0; j < 4; j++) {
3c92db9a EG	555	int gpio = tegra_gpio_compose(i, j, 0);
2e47b8b3 CC	556	seq_printf(s,
	557	"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
	558	i, j,
88d8951e SW	559	tegra_gpio_readl(GPIO_CNF(gpio)),
	560	tegra_gpio_readl(GPIO_OE(gpio)),
	561	tegra_gpio_readl(GPIO_OUT(gpio)),
	562	tegra_gpio_readl(GPIO_IN(gpio)),
	563	tegra_gpio_readl(GPIO_INT_STA(gpio)),
	564	tegra_gpio_readl(GPIO_INT_ENB(gpio)),
	565	tegra_gpio_readl(GPIO_INT_LVL(gpio)));
3c92db9a EG	566	}
	567	}
	568	return 0;
	569	}
	570
	571	static int dbg_gpio_open(struct inode inode, struct file file)
	572	{
	573	return single_open(file, dbg_gpio_show, &inode->i_private);
	574	}
	575
	576	static const struct file_operations debug_fops = {
	577	.open = dbg_gpio_open,
	578	.read = seq_read,
	579	.llseek = seq_lseek,
	580	.release = single_release,
	581	};
	582
	583	static int __init tegra_gpio_debuginit(void)
	584	{
	585	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
	586	NULL, NULL, &debug_fops);
	587	return 0;
	588	}
	589	late_initcall(tegra_gpio_debuginit);
	590	#endif