[linux-2.6-block.git] / drivers / gpio / gpio-tegra.c

/*
 * arch/arm/mach-tegra/gpio.c
 *
 * Copyright (c) 2010 Google, Inc
 *
 * Author:
 *	Erik Gilling <konkers@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/irqdomain.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>

#include <asm/mach/irq.h>

#define GPIO_BANK(x)		((x) >> 5)
#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
#define GPIO_BIT(x)		((x) & 0x7)

#define GPIO_REG(x)		(GPIO_BANK(x) * tegra_gpio_bank_stride + \
					GPIO_PORT(x) * 4)

#define GPIO_CNF(x)		(GPIO_REG(x) + 0x00)
#define GPIO_OE(x)		(GPIO_REG(x) + 0x10)
#define GPIO_OUT(x)		(GPIO_REG(x) + 0X20)
#define GPIO_IN(x)		(GPIO_REG(x) + 0x30)
#define GPIO_INT_STA(x)		(GPIO_REG(x) + 0x40)
#define GPIO_INT_ENB(x)		(GPIO_REG(x) + 0x50)
#define GPIO_INT_LVL(x)		(GPIO_REG(x) + 0x60)
#define GPIO_INT_CLR(x)		(GPIO_REG(x) + 0x70)

#define GPIO_MSK_CNF(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
#define GPIO_MSK_OE(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
#define GPIO_MSK_OUT(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
#define GPIO_MSK_INT_STA(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
#define GPIO_MSK_INT_ENB(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
#define GPIO_MSK_INT_LVL(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)

#define GPIO_INT_LVL_MASK		0x010101
#define GPIO_INT_LVL_EDGE_RISING	0x000101
#define GPIO_INT_LVL_EDGE_FALLING	0x000100
#define GPIO_INT_LVL_EDGE_BOTH		0x010100
#define GPIO_INT_LVL_LEVEL_HIGH		0x000001
#define GPIO_INT_LVL_LEVEL_LOW		0x000000

struct tegra_gpio_bank {
	int bank;
	int irq;
	spinlock_t lvl_lock[4];
#ifdef CONFIG_PM_SLEEP
	u32 cnf[4];
	u32 out[4];
	u32 oe[4];
	u32 int_enb[4];
	u32 int_lvl[4];
#endif
};

static struct irq_domain *irq_domain;
static void __iomem *regs;
static u32 tegra_gpio_bank_count;
static u32 tegra_gpio_bank_stride;
static u32 tegra_gpio_upper_offset;
static struct tegra_gpio_bank *tegra_gpio_banks;

static inline void tegra_gpio_writel(u32 val, u32 reg)
{
	__raw_writel(val, regs + reg);
}

static inline u32 tegra_gpio_readl(u32 reg)
{
	return __raw_readl(regs + reg);
}

static int tegra_gpio_compose(int bank, int port, int bit)
{
	return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
}

static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
{
	u32 val;

	val = 0x100 << GPIO_BIT(gpio);
	if (value)
		val |= 1 << GPIO_BIT(gpio);
	tegra_gpio_writel(val, reg);
}

static void tegra_gpio_enable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
}
EXPORT_SYMBOL_GPL(tegra_gpio_enable);

static void tegra_gpio_disable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
}
EXPORT_SYMBOL_GPL(tegra_gpio_disable);

int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	return pinctrl_request_gpio(offset);
}

void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	pinctrl_free_gpio(offset);
	tegra_gpio_disable(offset);
}

static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
}

static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
}

static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
	tegra_gpio_enable(offset);
	return 0;
}

static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
					int value)
{
	tegra_gpio_set(chip, offset, value);
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
	tegra_gpio_enable(offset);
	return 0;
}

static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return irq_find_mapping(irq_domain, offset);
}

static struct gpio_chip tegra_gpio_chip = {
	.label			= "tegra-gpio",
	.request		= tegra_gpio_request,
	.free			= tegra_gpio_free,
	.direction_input	= tegra_gpio_direction_input,
	.get			= tegra_gpio_get,
	.direction_output	= tegra_gpio_direction_output,
	.set			= tegra_gpio_set,
	.to_irq			= tegra_gpio_to_irq,
	.base			= 0,
};

static void tegra_gpio_irq_ack(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
}

static void tegra_gpio_irq_mask(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
}

static void tegra_gpio_irq_unmask(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
}

static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	int gpio = d->hwirq;
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	int port = GPIO_PORT(gpio);
	int lvl_type;
	int val;
	unsigned long flags;

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_RISING:
		lvl_type = GPIO_INT_LVL_EDGE_RISING;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		lvl_type = GPIO_INT_LVL_EDGE_FALLING;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		lvl_type = GPIO_INT_LVL_EDGE_BOTH;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		lvl_type = GPIO_INT_LVL_LEVEL_LOW;
		break;

	default:
		return -EINVAL;
	}

	spin_lock_irqsave(&bank->lvl_lock[port], flags);

	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
	val |= lvl_type << GPIO_BIT(gpio);
	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));

	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);

	tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
	tegra_gpio_enable(gpio);

	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		__irq_set_handler_locked(d->irq, handle_level_irq);
	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		__irq_set_handler_locked(d->irq, handle_edge_irq);

	return 0;
}

static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	struct tegra_gpio_bank *bank;
	int port;
	int pin;
	int unmasked = 0;
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	bank = irq_get_handler_data(irq);

	for (port = 0; port < 4; port++) {
		int gpio = tegra_gpio_compose(bank->bank, port, 0);
		unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
			tegra_gpio_readl(GPIO_INT_ENB(gpio));
		u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));

		for_each_set_bit(pin, &sta, 8) {
			tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));

			/* if gpio is edge triggered, clear condition
			 * before executing the hander so that we don't
			 * miss edges
			 */
			if (lvl & (0x100 << pin)) {
				unmasked = 1;
				chained_irq_exit(chip, desc);
			}

			generic_handle_irq(gpio_to_irq(gpio + pin));
		}
	}

	if (!unmasked)
		chained_irq_exit(chip, desc);

}

#ifdef CONFIG_PM_SLEEP
static int tegra_gpio_resume(struct device *dev)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);

	for (b = 0; b < tegra_gpio_bank_count; b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
			tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
			tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
			tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
			tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
		}
	}

	local_irq_restore(flags);
	return 0;
}

static int tegra_gpio_suspend(struct device *dev)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);
	for (b = 0; b < tegra_gpio_bank_count; b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
			bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
			bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
			bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
			bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
		}
	}
	local_irq_restore(flags);
	return 0;
}

static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
{
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	return irq_set_irq_wake(bank->irq, enable);
}
#endif

static struct irq_chip tegra_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= tegra_gpio_irq_ack,
	.irq_mask	= tegra_gpio_irq_mask,
	.irq_unmask	= tegra_gpio_irq_unmask,
	.irq_set_type	= tegra_gpio_irq_set_type,
#ifdef CONFIG_PM_SLEEP
	.irq_set_wake	= tegra_gpio_wake_enable,
#endif
};

static const struct dev_pm_ops tegra_gpio_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
};

struct tegra_gpio_soc_config {
	u32 bank_stride;
	u32 upper_offset;
};

static struct tegra_gpio_soc_config tegra20_gpio_config = {
	.bank_stride = 0x80,
	.upper_offset = 0x800,
};

static struct tegra_gpio_soc_config tegra30_gpio_config = {
	.bank_stride = 0x100,
	.upper_offset = 0x80,
};

static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
	{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
	{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
	{ },
};

/* This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

static int __devinit tegra_gpio_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct tegra_gpio_soc_config *config;
	struct resource *res;
	struct tegra_gpio_bank *bank;
	int gpio;
	int i;
	int j;

	match = of_match_device(tegra_gpio_of_match, &pdev->dev);
	if (match)
		config = (struct tegra_gpio_soc_config *)match->data;
	else
		config = &tegra20_gpio_config;

	tegra_gpio_bank_stride = config->bank_stride;
	tegra_gpio_upper_offset = config->upper_offset;

	for (;;) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
		if (!res)
			break;
		tegra_gpio_bank_count++;
	}
	if (!tegra_gpio_bank_count) {
		dev_err(&pdev->dev, "Missing IRQ resource\n");
		return -ENODEV;
	}

	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;

	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
			tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
			GFP_KERNEL);
	if (!tegra_gpio_banks) {
		dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
		return -ENODEV;
	}

	irq_domain = irq_domain_add_linear(pdev->dev.of_node,
					   tegra_gpio_chip.ngpio,
					   &irq_domain_simple_ops, NULL);
	if (!irq_domain)
		return -ENODEV;

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
		if (!res) {
			dev_err(&pdev->dev, "Missing IRQ resource\n");
			return -ENODEV;
		}

		bank = &tegra_gpio_banks[i];
		bank->bank = i;
		bank->irq = res->start;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "Missing MEM resource\n");
		return -ENODEV;
	}

	regs = devm_request_and_ioremap(&pdev->dev, res);
	if (!regs) {
		dev_err(&pdev->dev, "Couldn't ioremap regs\n");
		return -ENODEV;
	}

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
		}
	}

#ifdef CONFIG_OF_GPIO
	tegra_gpio_chip.of_node = pdev->dev.of_node;
#endif

	gpiochip_add(&tegra_gpio_chip);

	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
		int irq = irq_create_mapping(irq_domain, gpio);
		/* No validity check; all Tegra GPIOs are valid IRQs */

		bank = &tegra_gpio_banks[GPIO_BANK(gpio)];

		irq_set_lockdep_class(irq, &gpio_lock_class);
		irq_set_chip_data(irq, bank);
		irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
					 handle_simple_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		bank = &tegra_gpio_banks[i];

		irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
		irq_set_handler_data(bank->irq, bank);

		for (j = 0; j < 4; j++)
			spin_lock_init(&bank->lvl_lock[j]);
	}

	return 0;
}

static struct platform_driver tegra_gpio_driver = {
	.driver		= {
		.name	= "tegra-gpio",
		.owner	= THIS_MODULE,
		.pm	= &tegra_gpio_pm_ops,
		.of_match_table = tegra_gpio_of_match,
	},
	.probe		= tegra_gpio_probe,
};

static int __init tegra_gpio_init(void)
{
	return platform_driver_register(&tegra_gpio_driver);
}
postcore_initcall(tegra_gpio_init);

#ifdef	CONFIG_DEBUG_FS

#include <linux/debugfs.h>
#include <linux/seq_file.h>

static int dbg_gpio_show(struct seq_file *s, void *unused)
{
	int i;
	int j;

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			seq_printf(s,
				"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
				i, j,
				tegra_gpio_readl(GPIO_CNF(gpio)),
				tegra_gpio_readl(GPIO_OE(gpio)),
				tegra_gpio_readl(GPIO_OUT(gpio)),
				tegra_gpio_readl(GPIO_IN(gpio)),
				tegra_gpio_readl(GPIO_INT_STA(gpio)),
				tegra_gpio_readl(GPIO_INT_ENB(gpio)),
				tegra_gpio_readl(GPIO_INT_LVL(gpio)));
		}
	}
	return 0;
}

static int dbg_gpio_open(struct inode *inode, struct file *file)
{
	return single_open(file, dbg_gpio_show, &inode->i_private);
}

static const struct file_operations debug_fops = {
	.open		= dbg_gpio_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init tegra_gpio_debuginit(void)
{
	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
					NULL, NULL, &debug_fops);
	return 0;
}
late_initcall(tegra_gpio_debuginit);
#endif
Commit	Line	Data
3c92db9a EG	1	/*
	2	* arch/arm/mach-tegra/gpio.c
	3	*
	4	* Copyright (c) 2010 Google, Inc
	5	*
	6	* Author:
	7	* Erik Gilling <konkers@google.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/irq.h>
2e47b8b3	22	#include <linux/interrupt.h>
3c92db9a EG	23	#include <linux/io.h>
3c92db9a EG	24	#include <linux/gpio.h>
5c1e2c9d	25	#include <linux/of_device.h>
88d8951e SW	26	#include <linux/platform_device.h>
88d8951e SW	27	#include <linux/module.h>
6f74dc9b	28	#include <linux/irqdomain.h>
3e215d0a	29	#include <linux/pinctrl/consumer.h>
8939ddc7	30	#include <linux/pm.h>
3c92db9a	31
98022940 WD	32	#include <asm/mach/irq.h>
98022940 WD	33
3c92db9a EG	34	#define GPIO_BANK(x) ((x) >> 5)
	35	#define GPIO_PORT(x) (((x) >> 3) & 0x3)
	36	#define GPIO_BIT(x) ((x) & 0x7)
	37
5c1e2c9d SW	38	#define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \
5c1e2c9d SW	39	GPIO_PORT(x) * 4)
3c92db9a EG	40
	41	#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
	42	#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
	43	#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
	44	#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
	45	#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
	46	#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
	47	#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
	48	#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
	49
5c1e2c9d SW	50	#define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
	51	#define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
	52	#define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
	53	#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
	54	#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
	55	#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
3c92db9a EG	56
	57	#define GPIO_INT_LVL_MASK 0x010101
	58	#define GPIO_INT_LVL_EDGE_RISING 0x000101
	59	#define GPIO_INT_LVL_EDGE_FALLING 0x000100
	60	#define GPIO_INT_LVL_EDGE_BOTH 0x010100
	61	#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
	62	#define GPIO_INT_LVL_LEVEL_LOW 0x000000
	63
	64	struct tegra_gpio_bank {
	65	int bank;
	66	int irq;
	67	spinlock_t lvl_lock[4];
8939ddc7	68	#ifdef CONFIG_PM_SLEEP
2e47b8b3 CC	69	u32 cnf[4];
	70	u32 out[4];
	71	u32 oe[4];
	72	u32 int_enb[4];
	73	u32 int_lvl[4];
	74	#endif
3c92db9a EG	75	};
3c92db9a EG	76
bdc93a77	77	static struct irq_domain *irq_domain;
88d8951e	78	static void __iomem *regs;
3391811c	79	static u32 tegra_gpio_bank_count;
5c1e2c9d SW	80	static u32 tegra_gpio_bank_stride;
5c1e2c9d SW	81	static u32 tegra_gpio_upper_offset;
3391811c	82	static struct tegra_gpio_bank *tegra_gpio_banks;
88d8951e SW	83
	84	static inline void tegra_gpio_writel(u32 val, u32 reg)
	85	{
	86	__raw_writel(val, regs + reg);
	87	}
	88
	89	static inline u32 tegra_gpio_readl(u32 reg)
	90	{
	91	return __raw_readl(regs + reg);
	92	}
3c92db9a EG	93
	94	static int tegra_gpio_compose(int bank, int port, int bit)
	95	{
	96	return (bank << 5) \| ((port & 0x3) << 3) \| (bit & 0x7);
	97	}
	98
	99	static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
	100	{
	101	u32 val;
	102
	103	val = 0x100 << GPIO_BIT(gpio);
	104	if (value)
	105	val \|= 1 << GPIO_BIT(gpio);
88d8951e	106	tegra_gpio_writel(val, reg);
3c92db9a EG	107	}
3c92db9a EG	108
3e215d0a	109	static void tegra_gpio_enable(int gpio)
3c92db9a EG	110	{
	111	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
	112	}
691e06c0	113	EXPORT_SYMBOL_GPL(tegra_gpio_enable);
3c92db9a	114
3e215d0a	115	static void tegra_gpio_disable(int gpio)
3c92db9a EG	116	{
	117	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
	118	}
691e06c0	119	EXPORT_SYMBOL_GPL(tegra_gpio_disable);
3c92db9a	120
3e215d0a SW	121	int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
	122	{
	123	return pinctrl_request_gpio(offset);
	124	}
	125
	126	void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
	127	{
	128	pinctrl_free_gpio(offset);
	129	tegra_gpio_disable(offset);
	130	}
	131
3c92db9a EG	132	static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	133	{
	134	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
	135	}
	136
	137	static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
	138	{
88d8951e	139	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
3c92db9a EG	140	}
	141
	142	static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	143	{
	144	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
3e215d0a	145	tegra_gpio_enable(offset);
3c92db9a EG	146	return 0;
	147	}
	148
	149	static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
	150	int value)
	151	{
	152	tegra_gpio_set(chip, offset, value);
	153	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
3e215d0a	154	tegra_gpio_enable(offset);
3c92db9a EG	155	return 0;
	156	}
	157
438a99c0 SW	158	static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
438a99c0 SW	159	{
bdc93a77	160	return irq_find_mapping(irq_domain, offset);
438a99c0	161	}
3c92db9a EG	162
	163	static struct gpio_chip tegra_gpio_chip = {
	164	.label = "tegra-gpio",
3e215d0a SW	165	.request = tegra_gpio_request,
3e215d0a SW	166	.free = tegra_gpio_free,
3c92db9a EG	167	.direction_input = tegra_gpio_direction_input,
	168	.get = tegra_gpio_get,
	169	.direction_output = tegra_gpio_direction_output,
	170	.set = tegra_gpio_set,
438a99c0	171	.to_irq = tegra_gpio_to_irq,
3c92db9a	172	.base = 0,
3c92db9a EG	173	};
3c92db9a EG	174
37337a8d	175	static void tegra_gpio_irq_ack(struct irq_data *d)
3c92db9a	176	{
6f74dc9b	177	int gpio = d->hwirq;
3c92db9a	178
88d8951e	179	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
3c92db9a EG	180	}
3c92db9a EG	181
37337a8d	182	static void tegra_gpio_irq_mask(struct irq_data *d)
3c92db9a	183	{
6f74dc9b	184	int gpio = d->hwirq;
3c92db9a EG	185
	186	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
	187	}
	188
37337a8d	189	static void tegra_gpio_irq_unmask(struct irq_data *d)
3c92db9a	190	{
6f74dc9b	191	int gpio = d->hwirq;
3c92db9a EG	192
	193	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
	194	}
	195
37337a8d	196	static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
3c92db9a	197	{
6f74dc9b	198	int gpio = d->hwirq;
37337a8d	199	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
3c92db9a EG	200	int port = GPIO_PORT(gpio);
	201	int lvl_type;
	202	int val;
	203	unsigned long flags;
	204
	205	switch (type & IRQ_TYPE_SENSE_MASK) {
	206	case IRQ_TYPE_EDGE_RISING:
	207	lvl_type = GPIO_INT_LVL_EDGE_RISING;
	208	break;
	209
	210	case IRQ_TYPE_EDGE_FALLING:
	211	lvl_type = GPIO_INT_LVL_EDGE_FALLING;
	212	break;
	213
	214	case IRQ_TYPE_EDGE_BOTH:
	215	lvl_type = GPIO_INT_LVL_EDGE_BOTH;
	216	break;
	217
	218	case IRQ_TYPE_LEVEL_HIGH:
	219	lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
	220	break;
	221
	222	case IRQ_TYPE_LEVEL_LOW:
	223	lvl_type = GPIO_INT_LVL_LEVEL_LOW;
	224	break;
	225
	226	default:
	227	return -EINVAL;
	228	}
	229
	230	spin_lock_irqsave(&bank->lvl_lock[port], flags);
	231
88d8951e	232	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
3c92db9a EG	233	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
3c92db9a EG	234	val \|= lvl_type << GPIO_BIT(gpio);
88d8951e	235	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
3c92db9a EG	236
	237	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
	238
d941136f SW	239	tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
	240	tegra_gpio_enable(gpio);
	241
3c92db9a	242	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
6845664a	243	__irq_set_handler_locked(d->irq, handle_level_irq);
3c92db9a	244	else if (type & (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
6845664a	245	__irq_set_handler_locked(d->irq, handle_edge_irq);
3c92db9a EG	246
	247	return 0;
	248	}
	249
	250	static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
	251	{
	252	struct tegra_gpio_bank *bank;
	253	int port;
	254	int pin;
	255	int unmasked = 0;
98022940	256	struct irq_chip *chip = irq_desc_get_chip(desc);
3c92db9a	257
98022940	258	chained_irq_enter(chip, desc);
3c92db9a	259
6845664a	260	bank = irq_get_handler_data(irq);
3c92db9a EG	261
	262	for (port = 0; port < 4; port++) {
	263	int gpio = tegra_gpio_compose(bank->bank, port, 0);
88d8951e SW	264	unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
	265	tegra_gpio_readl(GPIO_INT_ENB(gpio));
	266	u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
3c92db9a EG	267
3c92db9a EG	268	for_each_set_bit(pin, &sta, 8) {
88d8951e	269	tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
3c92db9a EG	270
	271	/* if gpio is edge triggered, clear condition
	272	* before executing the hander so that we don't
	273	* miss edges
	274	*/
	275	if (lvl & (0x100 << pin)) {
	276	unmasked = 1;
98022940	277	chained_irq_exit(chip, desc);
3c92db9a EG	278	}
	279
	280	generic_handle_irq(gpio_to_irq(gpio + pin));
	281	}
	282	}
	283
	284	if (!unmasked)
98022940	285	chained_irq_exit(chip, desc);
3c92db9a EG	286
	287	}
	288
8939ddc7 LD	289	#ifdef CONFIG_PM_SLEEP
8939ddc7 LD	290	static int tegra_gpio_resume(struct device *dev)
2e47b8b3 CC	291	{
2e47b8b3 CC	292	unsigned long flags;
c8309ef6 CC	293	int b;
c8309ef6 CC	294	int p;
2e47b8b3 CC	295
	296	local_irq_save(flags);
	297
3391811c	298	for (b = 0; b < tegra_gpio_bank_count; b++) {
2e47b8b3 CC	299	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	300
	301	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	302	unsigned int gpio = (b<<5) \| (p<<3);
88d8951e SW	303	tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
	304	tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
	305	tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
	306	tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
	307	tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
2e47b8b3 CC	308	}
	309	}
	310
	311	local_irq_restore(flags);
8939ddc7	312	return 0;
2e47b8b3 CC	313	}
2e47b8b3 CC	314
8939ddc7	315	static int tegra_gpio_suspend(struct device *dev)
2e47b8b3 CC	316	{
2e47b8b3 CC	317	unsigned long flags;
c8309ef6 CC	318	int b;
c8309ef6 CC	319	int p;
2e47b8b3	320
2e47b8b3	321	local_irq_save(flags);
3391811c	322	for (b = 0; b < tegra_gpio_bank_count; b++) {
2e47b8b3 CC	323	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	324
	325	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	326	unsigned int gpio = (b<<5) \| (p<<3);
88d8951e SW	327	bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
	328	bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
	329	bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
	330	bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
	331	bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
2e47b8b3 CC	332	}
	333	}
	334	local_irq_restore(flags);
8939ddc7	335	return 0;
2e47b8b3 CC	336	}
2e47b8b3 CC	337
37337a8d	338	static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
2e47b8b3	339	{
37337a8d	340	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
6845664a	341	return irq_set_irq_wake(bank->irq, enable);
2e47b8b3 CC	342	}
2e47b8b3 CC	343	#endif
3c92db9a EG	344
	345	static struct irq_chip tegra_gpio_irq_chip = {
	346	.name = "GPIO",
37337a8d LB	347	.irq_ack = tegra_gpio_irq_ack,
	348	.irq_mask = tegra_gpio_irq_mask,
	349	.irq_unmask = tegra_gpio_irq_unmask,
	350	.irq_set_type = tegra_gpio_irq_set_type,
8939ddc7	351	#ifdef CONFIG_PM_SLEEP
37337a8d	352	.irq_set_wake = tegra_gpio_wake_enable,
2e47b8b3	353	#endif
3c92db9a EG	354	};
3c92db9a EG	355
8939ddc7 LD	356	static const struct dev_pm_ops tegra_gpio_pm_ops = {
	357	SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
	358	};
	359
5c1e2c9d SW	360	struct tegra_gpio_soc_config {
	361	u32 bank_stride;
	362	u32 upper_offset;
	363	};
	364
	365	static struct tegra_gpio_soc_config tegra20_gpio_config = {
	366	.bank_stride = 0x80,
	367	.upper_offset = 0x800,
	368	};
	369
	370	static struct tegra_gpio_soc_config tegra30_gpio_config = {
	371	.bank_stride = 0x100,
	372	.upper_offset = 0x80,
	373	};
	374
	375	static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
	376	{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
	377	{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
	378	{ },
	379	};
3c92db9a EG	380
	381	/* This lock class tells lockdep that GPIO irqs are in a different
	382	* category than their parents, so it won't report false recursion.
	383	*/
	384	static struct lock_class_key gpio_lock_class;
	385
88d8951e	386	static int __devinit tegra_gpio_probe(struct platform_device *pdev)
3c92db9a	387	{
5c1e2c9d SW	388	const struct of_device_id *match;
5c1e2c9d SW	389	struct tegra_gpio_soc_config *config;
88d8951e	390	struct resource *res;
3c92db9a	391	struct tegra_gpio_bank *bank;
47008001	392	int gpio;
3c92db9a EG	393	int i;
	394	int j;
	395
5c1e2c9d SW	396	match = of_match_device(tegra_gpio_of_match, &pdev->dev);
	397	if (match)
	398	config = (struct tegra_gpio_soc_config *)match->data;
	399	else
	400	config = &tegra20_gpio_config;
	401
	402	tegra_gpio_bank_stride = config->bank_stride;
	403	tegra_gpio_upper_offset = config->upper_offset;
	404
3391811c SW	405	for (;;) {
	406	res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
	407	if (!res)
	408	break;
	409	tegra_gpio_bank_count++;
	410	}
	411	if (!tegra_gpio_bank_count) {
	412	dev_err(&pdev->dev, "Missing IRQ resource\n");
	413	return -ENODEV;
	414	}
	415
	416	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
	417
	418	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
	419	tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
	420	GFP_KERNEL);
	421	if (!tegra_gpio_banks) {
	422	dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
	423	return -ENODEV;
	424	}
	425
d0235677 LW	426	irq_domain = irq_domain_add_linear(pdev->dev.of_node,
d0235677 LW	427	tegra_gpio_chip.ngpio,
bdc93a77	428	&irq_domain_simple_ops, NULL);
d0235677 LW	429	if (!irq_domain)
d0235677 LW	430	return -ENODEV;
6f74dc9b	431
3391811c	432	for (i = 0; i < tegra_gpio_bank_count; i++) {
88d8951e SW	433	res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
	434	if (!res) {
	435	dev_err(&pdev->dev, "Missing IRQ resource\n");
	436	return -ENODEV;
	437	}
	438
	439	bank = &tegra_gpio_banks[i];
	440	bank->bank = i;
	441	bank->irq = res->start;
	442	}
	443
	444	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	445	if (!res) {
	446	dev_err(&pdev->dev, "Missing MEM resource\n");
	447	return -ENODEV;
	448	}
	449
aedd4fdf	450	regs = devm_request_and_ioremap(&pdev->dev, res);
88d8951e SW	451	if (!regs) {
	452	dev_err(&pdev->dev, "Couldn't ioremap regs\n");
	453	return -ENODEV;
	454	}
	455
4a3398ee	456	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	457	for (j = 0; j < 4; j++) {
3c92db9a EG	458	int gpio = tegra_gpio_compose(i, j, 0);
88d8951e	459	tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
3c92db9a EG	460	}
	461	}
	462
df221227	463	#ifdef CONFIG_OF_GPIO
88d8951e SW	464	tegra_gpio_chip.of_node = pdev->dev.of_node;
88d8951e SW	465	#endif
df221227	466
3c92db9a EG	467	gpiochip_add(&tegra_gpio_chip);
3c92db9a EG	468
3391811c	469	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
d0235677	470	int irq = irq_create_mapping(irq_domain, gpio);
47008001	471	/* No validity check; all Tegra GPIOs are valid IRQs */
3c92db9a	472
47008001	473	bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
3c92db9a	474
47008001 SW	475	irq_set_lockdep_class(irq, &gpio_lock_class);
	476	irq_set_chip_data(irq, bank);
	477	irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
f38c02f3	478	handle_simple_irq);
47008001	479	set_irq_flags(irq, IRQF_VALID);
3c92db9a EG	480	}
3c92db9a EG	481
3391811c	482	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	483	bank = &tegra_gpio_banks[i];
3c92db9a EG	484
6845664a TG	485	irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
6845664a TG	486	irq_set_handler_data(bank->irq, bank);
3c92db9a EG	487
	488	for (j = 0; j < 4; j++)
	489	spin_lock_init(&bank->lvl_lock[j]);
	490	}
	491
	492	return 0;
	493	}
	494
88d8951e SW	495	static struct platform_driver tegra_gpio_driver = {
	496	.driver = {
	497	.name = "tegra-gpio",
	498	.owner = THIS_MODULE,
8939ddc7	499	.pm = &tegra_gpio_pm_ops,
88d8951e SW	500	.of_match_table = tegra_gpio_of_match,
	501	},
	502	.probe = tegra_gpio_probe,
	503	};
	504
	505	static int __init tegra_gpio_init(void)
	506	{
	507	return platform_driver_register(&tegra_gpio_driver);
	508	}
3c92db9a EG	509	postcore_initcall(tegra_gpio_init);
	510
	511	#ifdef CONFIG_DEBUG_FS
	512
	513	#include <linux/debugfs.h>
	514	#include <linux/seq_file.h>
	515
	516	static int dbg_gpio_show(struct seq_file s, void unused)
	517	{
	518	int i;
	519	int j;
	520
4a3398ee	521	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	522	for (j = 0; j < 4; j++) {
3c92db9a EG	523	int gpio = tegra_gpio_compose(i, j, 0);
2e47b8b3 CC	524	seq_printf(s,
	525	"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
	526	i, j,
88d8951e SW	527	tegra_gpio_readl(GPIO_CNF(gpio)),
	528	tegra_gpio_readl(GPIO_OE(gpio)),
	529	tegra_gpio_readl(GPIO_OUT(gpio)),
	530	tegra_gpio_readl(GPIO_IN(gpio)),
	531	tegra_gpio_readl(GPIO_INT_STA(gpio)),
	532	tegra_gpio_readl(GPIO_INT_ENB(gpio)),
	533	tegra_gpio_readl(GPIO_INT_LVL(gpio)));
3c92db9a EG	534	}
	535	}
	536	return 0;
	537	}
	538
	539	static int dbg_gpio_open(struct inode inode, struct file file)
	540	{
	541	return single_open(file, dbg_gpio_show, &inode->i_private);
	542	}
	543
	544	static const struct file_operations debug_fops = {
	545	.open = dbg_gpio_open,
	546	.read = seq_read,
	547	.llseek = seq_lseek,
	548	.release = single_release,
	549	};
	550
	551	static int __init tegra_gpio_debuginit(void)
	552	{
	553	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
	554	NULL, NULL, &debug_fops);
	555	return 0;
	556	}
	557	late_initcall(tegra_gpio_debuginit);
	558	#endif