[linux-2.6-block.git] / drivers / gpio / gpio-tegra.c

/*
 * arch/arm/mach-tegra/gpio.c
 *
 * Copyright (c) 2010 Google, Inc
 *
 * Author:
 *	Erik Gilling <konkers@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/irqdomain.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>

#include <asm/mach/irq.h>

#define GPIO_BANK(x)		((x) >> 5)
#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
#define GPIO_BIT(x)		((x) & 0x7)

#define GPIO_REG(x)		(GPIO_BANK(x) * tegra_gpio_bank_stride + \
					GPIO_PORT(x) * 4)

#define GPIO_CNF(x)		(GPIO_REG(x) + 0x00)
#define GPIO_OE(x)		(GPIO_REG(x) + 0x10)
#define GPIO_OUT(x)		(GPIO_REG(x) + 0X20)
#define GPIO_IN(x)		(GPIO_REG(x) + 0x30)
#define GPIO_INT_STA(x)		(GPIO_REG(x) + 0x40)
#define GPIO_INT_ENB(x)		(GPIO_REG(x) + 0x50)
#define GPIO_INT_LVL(x)		(GPIO_REG(x) + 0x60)
#define GPIO_INT_CLR(x)		(GPIO_REG(x) + 0x70)

#define GPIO_MSK_CNF(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
#define GPIO_MSK_OE(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
#define GPIO_MSK_OUT(x)		(GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
#define GPIO_MSK_INT_STA(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
#define GPIO_MSK_INT_ENB(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
#define GPIO_MSK_INT_LVL(x)	(GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)

#define GPIO_INT_LVL_MASK		0x010101
#define GPIO_INT_LVL_EDGE_RISING	0x000101
#define GPIO_INT_LVL_EDGE_FALLING	0x000100
#define GPIO_INT_LVL_EDGE_BOTH		0x010100
#define GPIO_INT_LVL_LEVEL_HIGH		0x000001
#define GPIO_INT_LVL_LEVEL_LOW		0x000000

struct tegra_gpio_bank {
	int bank;
	int irq;
	spinlock_t lvl_lock[4];
#ifdef CONFIG_PM_SLEEP
	u32 cnf[4];
	u32 out[4];
	u32 oe[4];
	u32 int_enb[4];
	u32 int_lvl[4];
#endif
};

static struct irq_domain *irq_domain;
static void __iomem *regs;
static u32 tegra_gpio_bank_count;
static u32 tegra_gpio_bank_stride;
static u32 tegra_gpio_upper_offset;
static struct tegra_gpio_bank *tegra_gpio_banks;

static inline void tegra_gpio_writel(u32 val, u32 reg)
{
	__raw_writel(val, regs + reg);
}

static inline u32 tegra_gpio_readl(u32 reg)
{
	return __raw_readl(regs + reg);
}

static int tegra_gpio_compose(int bank, int port, int bit)
{
	return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
}

static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
{
	u32 val;

	val = 0x100 << GPIO_BIT(gpio);
	if (value)
		val |= 1 << GPIO_BIT(gpio);
	tegra_gpio_writel(val, reg);
}

static void tegra_gpio_enable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
}

static void tegra_gpio_disable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
}

static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	return pinctrl_request_gpio(offset);
}

static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	pinctrl_free_gpio(offset);
	tegra_gpio_disable(offset);
}

static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
}

static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	/* If gpio is in output mode then read from the out value */
	if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
		return (tegra_gpio_readl(GPIO_OUT(offset)) >>
				GPIO_BIT(offset)) & 0x1;

	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
}

static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
	tegra_gpio_enable(offset);
	return 0;
}

static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
					int value)
{
	tegra_gpio_set(chip, offset, value);
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
	tegra_gpio_enable(offset);
	return 0;
}

static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return irq_find_mapping(irq_domain, offset);
}

static struct gpio_chip tegra_gpio_chip = {
	.label			= "tegra-gpio",
	.request		= tegra_gpio_request,
	.free			= tegra_gpio_free,
	.direction_input	= tegra_gpio_direction_input,
	.get			= tegra_gpio_get,
	.direction_output	= tegra_gpio_direction_output,
	.set			= tegra_gpio_set,
	.to_irq			= tegra_gpio_to_irq,
	.base			= 0,
};

static void tegra_gpio_irq_ack(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
}

static void tegra_gpio_irq_mask(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
}

static void tegra_gpio_irq_unmask(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
}

static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	int gpio = d->hwirq;
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	int port = GPIO_PORT(gpio);
	int lvl_type;
	int val;
	unsigned long flags;

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_RISING:
		lvl_type = GPIO_INT_LVL_EDGE_RISING;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		lvl_type = GPIO_INT_LVL_EDGE_FALLING;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		lvl_type = GPIO_INT_LVL_EDGE_BOTH;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		lvl_type = GPIO_INT_LVL_LEVEL_LOW;
		break;

	default:
		return -EINVAL;
	}

	spin_lock_irqsave(&bank->lvl_lock[port], flags);

	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
	val |= lvl_type << GPIO_BIT(gpio);
	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));

	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);

	tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
	tegra_gpio_enable(gpio);

	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		__irq_set_handler_locked(d->irq, handle_level_irq);
	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		__irq_set_handler_locked(d->irq, handle_edge_irq);

	return 0;
}

static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	struct tegra_gpio_bank *bank;
	int port;
	int pin;
	int unmasked = 0;
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	bank = irq_get_handler_data(irq);

	for (port = 0; port < 4; port++) {
		int gpio = tegra_gpio_compose(bank->bank, port, 0);
		unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
			tegra_gpio_readl(GPIO_INT_ENB(gpio));
		u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));

		for_each_set_bit(pin, &sta, 8) {
			tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));

			/* if gpio is edge triggered, clear condition
			 * before executing the hander so that we don't
			 * miss edges
			 */
			if (lvl & (0x100 << pin)) {
				unmasked = 1;
				chained_irq_exit(chip, desc);
			}

			generic_handle_irq(gpio_to_irq(gpio + pin));
		}
	}

	if (!unmasked)
		chained_irq_exit(chip, desc);

}

#ifdef CONFIG_PM_SLEEP
static int tegra_gpio_resume(struct device *dev)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);

	for (b = 0; b < tegra_gpio_bank_count; b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
			tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
			tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
			tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
			tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
		}
	}

	local_irq_restore(flags);
	return 0;
}

static int tegra_gpio_suspend(struct device *dev)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);
	for (b = 0; b < tegra_gpio_bank_count; b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
			bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
			bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
			bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
			bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
		}
	}
	local_irq_restore(flags);
	return 0;
}

static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
{
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	return irq_set_irq_wake(bank->irq, enable);
}
#endif

static struct irq_chip tegra_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= tegra_gpio_irq_ack,
	.irq_mask	= tegra_gpio_irq_mask,
	.irq_unmask	= tegra_gpio_irq_unmask,
	.irq_set_type	= tegra_gpio_irq_set_type,
#ifdef CONFIG_PM_SLEEP
	.irq_set_wake	= tegra_gpio_wake_enable,
#endif
};

static const struct dev_pm_ops tegra_gpio_pm_ops = {
	SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
};

struct tegra_gpio_soc_config {
	u32 bank_stride;
	u32 upper_offset;
};

static struct tegra_gpio_soc_config tegra20_gpio_config = {
	.bank_stride = 0x80,
	.upper_offset = 0x800,
};

static struct tegra_gpio_soc_config tegra30_gpio_config = {
	.bank_stride = 0x100,
	.upper_offset = 0x80,
};

static struct of_device_id tegra_gpio_of_match[] = {
	{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
	{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
	{ },
};

/* This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

static int tegra_gpio_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct tegra_gpio_soc_config *config;
	struct resource *res;
	struct tegra_gpio_bank *bank;
	int gpio;
	int i;
	int j;

	match = of_match_device(tegra_gpio_of_match, &pdev->dev);
	if (match)
		config = (struct tegra_gpio_soc_config *)match->data;
	else
		config = &tegra20_gpio_config;

	tegra_gpio_bank_stride = config->bank_stride;
	tegra_gpio_upper_offset = config->upper_offset;

	for (;;) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
		if (!res)
			break;
		tegra_gpio_bank_count++;
	}
	if (!tegra_gpio_bank_count) {
		dev_err(&pdev->dev, "Missing IRQ resource\n");
		return -ENODEV;
	}

	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;

	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
			tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
			GFP_KERNEL);
	if (!tegra_gpio_banks) {
		dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
		return -ENODEV;
	}

	irq_domain = irq_domain_add_linear(pdev->dev.of_node,
					   tegra_gpio_chip.ngpio,
					   &irq_domain_simple_ops, NULL);
	if (!irq_domain)
		return -ENODEV;

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
		if (!res) {
			dev_err(&pdev->dev, "Missing IRQ resource\n");
			return -ENODEV;
		}

		bank = &tegra_gpio_banks[i];
		bank->bank = i;
		bank->irq = res->start;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "Missing MEM resource\n");
		return -ENODEV;
	}

	regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(regs))
		return PTR_ERR(regs);

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
		}
	}

#ifdef CONFIG_OF_GPIO
	tegra_gpio_chip.of_node = pdev->dev.of_node;
#endif

	gpiochip_add(&tegra_gpio_chip);

	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
		int irq = irq_create_mapping(irq_domain, gpio);
		/* No validity check; all Tegra GPIOs are valid IRQs */

		bank = &tegra_gpio_banks[GPIO_BANK(gpio)];

		irq_set_lockdep_class(irq, &gpio_lock_class);
		irq_set_chip_data(irq, bank);
		irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
					 handle_simple_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		bank = &tegra_gpio_banks[i];

		irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
		irq_set_handler_data(bank->irq, bank);

		for (j = 0; j < 4; j++)
			spin_lock_init(&bank->lvl_lock[j]);
	}

	return 0;
}

static struct platform_driver tegra_gpio_driver = {
	.driver		= {
		.name	= "tegra-gpio",
		.owner	= THIS_MODULE,
		.pm	= &tegra_gpio_pm_ops,
		.of_match_table = tegra_gpio_of_match,
	},
	.probe		= tegra_gpio_probe,
};

static int __init tegra_gpio_init(void)
{
	return platform_driver_register(&tegra_gpio_driver);
}
postcore_initcall(tegra_gpio_init);

#ifdef	CONFIG_DEBUG_FS

#include <linux/debugfs.h>
#include <linux/seq_file.h>

static int dbg_gpio_show(struct seq_file *s, void *unused)
{
	int i;
	int j;

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			seq_printf(s,
				"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
				i, j,
				tegra_gpio_readl(GPIO_CNF(gpio)),
				tegra_gpio_readl(GPIO_OE(gpio)),
				tegra_gpio_readl(GPIO_OUT(gpio)),
				tegra_gpio_readl(GPIO_IN(gpio)),
				tegra_gpio_readl(GPIO_INT_STA(gpio)),
				tegra_gpio_readl(GPIO_INT_ENB(gpio)),
				tegra_gpio_readl(GPIO_INT_LVL(gpio)));
		}
	}
	return 0;
}

static int dbg_gpio_open(struct inode *inode, struct file *file)
{
	return single_open(file, dbg_gpio_show, &inode->i_private);
}

static const struct file_operations debug_fops = {
	.open		= dbg_gpio_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init tegra_gpio_debuginit(void)
{
	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
					NULL, NULL, &debug_fops);
	return 0;
}
late_initcall(tegra_gpio_debuginit);
#endif
Commit	Line	Data
3c92db9a EG	1	/*
	2	* arch/arm/mach-tegra/gpio.c
	3	*
	4	* Copyright (c) 2010 Google, Inc
	5	*
	6	* Author:
	7	* Erik Gilling <konkers@google.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
641d0342	20	#include <linux/err.h>
3c92db9a EG	21	#include <linux/init.h>
3c92db9a EG	22	#include <linux/irq.h>
2e47b8b3	23	#include <linux/interrupt.h>
3c92db9a EG	24	#include <linux/io.h>
3c92db9a EG	25	#include <linux/gpio.h>
5c1e2c9d	26	#include <linux/of_device.h>
88d8951e SW	27	#include <linux/platform_device.h>
88d8951e SW	28	#include <linux/module.h>
6f74dc9b	29	#include <linux/irqdomain.h>
3e215d0a	30	#include <linux/pinctrl/consumer.h>
8939ddc7	31	#include <linux/pm.h>
3c92db9a	32
98022940 WD	33	#include <asm/mach/irq.h>
98022940 WD	34
3c92db9a EG	35	#define GPIO_BANK(x) ((x) >> 5)
	36	#define GPIO_PORT(x) (((x) >> 3) & 0x3)
	37	#define GPIO_BIT(x) ((x) & 0x7)
	38
5c1e2c9d SW	39	#define GPIO_REG(x) (GPIO_BANK(x) * tegra_gpio_bank_stride + \
5c1e2c9d SW	40	GPIO_PORT(x) * 4)
3c92db9a EG	41
	42	#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
	43	#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
	44	#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
	45	#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
	46	#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
	47	#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
	48	#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
	49	#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
	50
5c1e2c9d SW	51	#define GPIO_MSK_CNF(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x00)
	52	#define GPIO_MSK_OE(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x10)
	53	#define GPIO_MSK_OUT(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0X20)
	54	#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x40)
	55	#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x50)
	56	#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + tegra_gpio_upper_offset + 0x60)
3c92db9a EG	57
	58	#define GPIO_INT_LVL_MASK 0x010101
	59	#define GPIO_INT_LVL_EDGE_RISING 0x000101
	60	#define GPIO_INT_LVL_EDGE_FALLING 0x000100
	61	#define GPIO_INT_LVL_EDGE_BOTH 0x010100
	62	#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
	63	#define GPIO_INT_LVL_LEVEL_LOW 0x000000
	64
	65	struct tegra_gpio_bank {
	66	int bank;
	67	int irq;
	68	spinlock_t lvl_lock[4];
8939ddc7	69	#ifdef CONFIG_PM_SLEEP
2e47b8b3 CC	70	u32 cnf[4];
	71	u32 out[4];
	72	u32 oe[4];
	73	u32 int_enb[4];
	74	u32 int_lvl[4];
	75	#endif
3c92db9a EG	76	};
3c92db9a EG	77
bdc93a77	78	static struct irq_domain *irq_domain;
88d8951e	79	static void __iomem *regs;
3391811c	80	static u32 tegra_gpio_bank_count;
5c1e2c9d SW	81	static u32 tegra_gpio_bank_stride;
5c1e2c9d SW	82	static u32 tegra_gpio_upper_offset;
3391811c	83	static struct tegra_gpio_bank *tegra_gpio_banks;
88d8951e SW	84
	85	static inline void tegra_gpio_writel(u32 val, u32 reg)
	86	{
	87	__raw_writel(val, regs + reg);
	88	}
	89
	90	static inline u32 tegra_gpio_readl(u32 reg)
	91	{
	92	return __raw_readl(regs + reg);
	93	}
3c92db9a EG	94
	95	static int tegra_gpio_compose(int bank, int port, int bit)
	96	{
	97	return (bank << 5) \| ((port & 0x3) << 3) \| (bit & 0x7);
	98	}
	99
	100	static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
	101	{
	102	u32 val;
	103
	104	val = 0x100 << GPIO_BIT(gpio);
	105	if (value)
	106	val \|= 1 << GPIO_BIT(gpio);
88d8951e	107	tegra_gpio_writel(val, reg);
3c92db9a EG	108	}
3c92db9a EG	109
3e215d0a	110	static void tegra_gpio_enable(int gpio)
3c92db9a EG	111	{
	112	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
	113	}
	114
3e215d0a	115	static void tegra_gpio_disable(int gpio)
3c92db9a EG	116	{
	117	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
	118	}
	119
924a0987	120	static int tegra_gpio_request(struct gpio_chip *chip, unsigned offset)
3e215d0a SW	121	{
	122	return pinctrl_request_gpio(offset);
	123	}
	124
924a0987	125	static void tegra_gpio_free(struct gpio_chip *chip, unsigned offset)
3e215d0a SW	126	{
	127	pinctrl_free_gpio(offset);
	128	tegra_gpio_disable(offset);
	129	}
	130
3c92db9a EG	131	static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	132	{
	133	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
	134	}
	135
	136	static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
	137	{
195812e4 LD	138	/* If gpio is in output mode then read from the out value */
	139	if ((tegra_gpio_readl(GPIO_OE(offset)) >> GPIO_BIT(offset)) & 1)
	140	return (tegra_gpio_readl(GPIO_OUT(offset)) >>
	141	GPIO_BIT(offset)) & 0x1;
	142
88d8951e	143	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
3c92db9a EG	144	}
	145
	146	static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	147	{
	148	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
3e215d0a	149	tegra_gpio_enable(offset);
3c92db9a EG	150	return 0;
	151	}
	152
	153	static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
	154	int value)
	155	{
	156	tegra_gpio_set(chip, offset, value);
	157	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
3e215d0a	158	tegra_gpio_enable(offset);
3c92db9a EG	159	return 0;
	160	}
	161
438a99c0 SW	162	static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
438a99c0 SW	163	{
bdc93a77	164	return irq_find_mapping(irq_domain, offset);
438a99c0	165	}
3c92db9a EG	166
	167	static struct gpio_chip tegra_gpio_chip = {
	168	.label = "tegra-gpio",
3e215d0a SW	169	.request = tegra_gpio_request,
3e215d0a SW	170	.free = tegra_gpio_free,
3c92db9a EG	171	.direction_input = tegra_gpio_direction_input,
	172	.get = tegra_gpio_get,
	173	.direction_output = tegra_gpio_direction_output,
	174	.set = tegra_gpio_set,
438a99c0	175	.to_irq = tegra_gpio_to_irq,
3c92db9a	176	.base = 0,
3c92db9a EG	177	};
3c92db9a EG	178
37337a8d	179	static void tegra_gpio_irq_ack(struct irq_data *d)
3c92db9a	180	{
6f74dc9b	181	int gpio = d->hwirq;
3c92db9a	182
88d8951e	183	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
3c92db9a EG	184	}
3c92db9a EG	185
37337a8d	186	static void tegra_gpio_irq_mask(struct irq_data *d)
3c92db9a	187	{
6f74dc9b	188	int gpio = d->hwirq;
3c92db9a EG	189
	190	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
	191	}
	192
37337a8d	193	static void tegra_gpio_irq_unmask(struct irq_data *d)
3c92db9a	194	{
6f74dc9b	195	int gpio = d->hwirq;
3c92db9a EG	196
	197	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
	198	}
	199
37337a8d	200	static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
3c92db9a	201	{
6f74dc9b	202	int gpio = d->hwirq;
37337a8d	203	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
3c92db9a EG	204	int port = GPIO_PORT(gpio);
	205	int lvl_type;
	206	int val;
	207	unsigned long flags;
	208
	209	switch (type & IRQ_TYPE_SENSE_MASK) {
	210	case IRQ_TYPE_EDGE_RISING:
	211	lvl_type = GPIO_INT_LVL_EDGE_RISING;
	212	break;
	213
	214	case IRQ_TYPE_EDGE_FALLING:
	215	lvl_type = GPIO_INT_LVL_EDGE_FALLING;
	216	break;
	217
	218	case IRQ_TYPE_EDGE_BOTH:
	219	lvl_type = GPIO_INT_LVL_EDGE_BOTH;
	220	break;
	221
	222	case IRQ_TYPE_LEVEL_HIGH:
	223	lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
	224	break;
	225
	226	case IRQ_TYPE_LEVEL_LOW:
	227	lvl_type = GPIO_INT_LVL_LEVEL_LOW;
	228	break;
	229
	230	default:
	231	return -EINVAL;
	232	}
	233
	234	spin_lock_irqsave(&bank->lvl_lock[port], flags);
	235
88d8951e	236	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
3c92db9a EG	237	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
3c92db9a EG	238	val \|= lvl_type << GPIO_BIT(gpio);
88d8951e	239	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
3c92db9a EG	240
	241	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
	242
d941136f SW	243	tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0);
	244	tegra_gpio_enable(gpio);
	245
3c92db9a	246	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
6845664a	247	__irq_set_handler_locked(d->irq, handle_level_irq);
3c92db9a	248	else if (type & (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
6845664a	249	__irq_set_handler_locked(d->irq, handle_edge_irq);
3c92db9a EG	250
	251	return 0;
	252	}
	253
	254	static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
	255	{
	256	struct tegra_gpio_bank *bank;
	257	int port;
	258	int pin;
	259	int unmasked = 0;
98022940	260	struct irq_chip *chip = irq_desc_get_chip(desc);
3c92db9a	261
98022940	262	chained_irq_enter(chip, desc);
3c92db9a	263
6845664a	264	bank = irq_get_handler_data(irq);
3c92db9a EG	265
	266	for (port = 0; port < 4; port++) {
	267	int gpio = tegra_gpio_compose(bank->bank, port, 0);
88d8951e SW	268	unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
	269	tegra_gpio_readl(GPIO_INT_ENB(gpio));
	270	u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
3c92db9a EG	271
3c92db9a EG	272	for_each_set_bit(pin, &sta, 8) {
88d8951e	273	tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
3c92db9a EG	274
	275	/* if gpio is edge triggered, clear condition
	276	* before executing the hander so that we don't
	277	* miss edges
	278	*/
	279	if (lvl & (0x100 << pin)) {
	280	unmasked = 1;
98022940	281	chained_irq_exit(chip, desc);
3c92db9a EG	282	}
	283
	284	generic_handle_irq(gpio_to_irq(gpio + pin));
	285	}
	286	}
	287
	288	if (!unmasked)
98022940	289	chained_irq_exit(chip, desc);
3c92db9a EG	290
	291	}
	292
8939ddc7 LD	293	#ifdef CONFIG_PM_SLEEP
8939ddc7 LD	294	static int tegra_gpio_resume(struct device *dev)
2e47b8b3 CC	295	{
2e47b8b3 CC	296	unsigned long flags;
c8309ef6 CC	297	int b;
c8309ef6 CC	298	int p;
2e47b8b3 CC	299
	300	local_irq_save(flags);
	301
3391811c	302	for (b = 0; b < tegra_gpio_bank_count; b++) {
2e47b8b3 CC	303	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	304
	305	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	306	unsigned int gpio = (b<<5) \| (p<<3);
88d8951e SW	307	tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
	308	tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
	309	tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
	310	tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
	311	tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
2e47b8b3 CC	312	}
	313	}
	314
	315	local_irq_restore(flags);
8939ddc7	316	return 0;
2e47b8b3 CC	317	}
2e47b8b3 CC	318
8939ddc7	319	static int tegra_gpio_suspend(struct device *dev)
2e47b8b3 CC	320	{
2e47b8b3 CC	321	unsigned long flags;
c8309ef6 CC	322	int b;
c8309ef6 CC	323	int p;
2e47b8b3	324
2e47b8b3	325	local_irq_save(flags);
3391811c	326	for (b = 0; b < tegra_gpio_bank_count; b++) {
2e47b8b3 CC	327	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	328
	329	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	330	unsigned int gpio = (b<<5) \| (p<<3);
88d8951e SW	331	bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
	332	bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
	333	bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
	334	bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
	335	bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
2e47b8b3 CC	336	}
	337	}
	338	local_irq_restore(flags);
8939ddc7	339	return 0;
2e47b8b3 CC	340	}
2e47b8b3 CC	341
37337a8d	342	static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
2e47b8b3	343	{
37337a8d	344	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
6845664a	345	return irq_set_irq_wake(bank->irq, enable);
2e47b8b3 CC	346	}
2e47b8b3 CC	347	#endif
3c92db9a EG	348
	349	static struct irq_chip tegra_gpio_irq_chip = {
	350	.name = "GPIO",
37337a8d LB	351	.irq_ack = tegra_gpio_irq_ack,
	352	.irq_mask = tegra_gpio_irq_mask,
	353	.irq_unmask = tegra_gpio_irq_unmask,
	354	.irq_set_type = tegra_gpio_irq_set_type,
8939ddc7	355	#ifdef CONFIG_PM_SLEEP
37337a8d	356	.irq_set_wake = tegra_gpio_wake_enable,
2e47b8b3	357	#endif
3c92db9a EG	358	};
3c92db9a EG	359
8939ddc7 LD	360	static const struct dev_pm_ops tegra_gpio_pm_ops = {
	361	SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
	362	};
	363
5c1e2c9d SW	364	struct tegra_gpio_soc_config {
	365	u32 bank_stride;
	366	u32 upper_offset;
	367	};
	368
	369	static struct tegra_gpio_soc_config tegra20_gpio_config = {
	370	.bank_stride = 0x80,
	371	.upper_offset = 0x800,
	372	};
	373
	374	static struct tegra_gpio_soc_config tegra30_gpio_config = {
	375	.bank_stride = 0x100,
	376	.upper_offset = 0x80,
	377	};
	378
aeca8ad1	379	static struct of_device_id tegra_gpio_of_match[] = {
5c1e2c9d SW	380	{ .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
	381	{ .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
	382	{ },
	383	};
3c92db9a EG	384
	385	/* This lock class tells lockdep that GPIO irqs are in a different
	386	* category than their parents, so it won't report false recursion.
	387	*/
	388	static struct lock_class_key gpio_lock_class;
	389
3836309d	390	static int tegra_gpio_probe(struct platform_device *pdev)
3c92db9a	391	{
5c1e2c9d SW	392	const struct of_device_id *match;
5c1e2c9d SW	393	struct tegra_gpio_soc_config *config;
88d8951e	394	struct resource *res;
3c92db9a	395	struct tegra_gpio_bank *bank;
47008001	396	int gpio;
3c92db9a EG	397	int i;
	398	int j;
	399
5c1e2c9d SW	400	match = of_match_device(tegra_gpio_of_match, &pdev->dev);
	401	if (match)
	402	config = (struct tegra_gpio_soc_config *)match->data;
	403	else
	404	config = &tegra20_gpio_config;
	405
	406	tegra_gpio_bank_stride = config->bank_stride;
	407	tegra_gpio_upper_offset = config->upper_offset;
	408
3391811c SW	409	for (;;) {
	410	res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
	411	if (!res)
	412	break;
	413	tegra_gpio_bank_count++;
	414	}
	415	if (!tegra_gpio_bank_count) {
	416	dev_err(&pdev->dev, "Missing IRQ resource\n");
	417	return -ENODEV;
	418	}
	419
	420	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
	421
	422	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
	423	tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
	424	GFP_KERNEL);
	425	if (!tegra_gpio_banks) {
	426	dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
	427	return -ENODEV;
	428	}
	429
d0235677 LW	430	irq_domain = irq_domain_add_linear(pdev->dev.of_node,
d0235677 LW	431	tegra_gpio_chip.ngpio,
bdc93a77	432	&irq_domain_simple_ops, NULL);
d0235677 LW	433	if (!irq_domain)
d0235677 LW	434	return -ENODEV;
6f74dc9b	435
3391811c	436	for (i = 0; i < tegra_gpio_bank_count; i++) {
88d8951e SW	437	res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
	438	if (!res) {
	439	dev_err(&pdev->dev, "Missing IRQ resource\n");
	440	return -ENODEV;
	441	}
	442
	443	bank = &tegra_gpio_banks[i];
	444	bank->bank = i;
	445	bank->irq = res->start;
	446	}
	447
	448	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	449	if (!res) {
	450	dev_err(&pdev->dev, "Missing MEM resource\n");
	451	return -ENODEV;
	452	}
	453
641d0342 TR	454	regs = devm_ioremap_resource(&pdev->dev, res);
	455	if (IS_ERR(regs))
	456	return PTR_ERR(regs);
88d8951e	457
4a3398ee	458	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	459	for (j = 0; j < 4; j++) {
3c92db9a EG	460	int gpio = tegra_gpio_compose(i, j, 0);
88d8951e	461	tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
3c92db9a EG	462	}
	463	}
	464
df221227	465	#ifdef CONFIG_OF_GPIO
88d8951e SW	466	tegra_gpio_chip.of_node = pdev->dev.of_node;
88d8951e SW	467	#endif
df221227	468
3c92db9a EG	469	gpiochip_add(&tegra_gpio_chip);
3c92db9a EG	470
3391811c	471	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
d0235677	472	int irq = irq_create_mapping(irq_domain, gpio);
47008001	473	/* No validity check; all Tegra GPIOs are valid IRQs */
3c92db9a	474
47008001	475	bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
3c92db9a	476
47008001 SW	477	irq_set_lockdep_class(irq, &gpio_lock_class);
	478	irq_set_chip_data(irq, bank);
	479	irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
f38c02f3	480	handle_simple_irq);
47008001	481	set_irq_flags(irq, IRQF_VALID);
3c92db9a EG	482	}
3c92db9a EG	483
3391811c	484	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	485	bank = &tegra_gpio_banks[i];
3c92db9a EG	486
6845664a TG	487	irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
6845664a TG	488	irq_set_handler_data(bank->irq, bank);
3c92db9a EG	489
	490	for (j = 0; j < 4; j++)
	491	spin_lock_init(&bank->lvl_lock[j]);
	492	}
	493
	494	return 0;
	495	}
	496
88d8951e SW	497	static struct platform_driver tegra_gpio_driver = {
	498	.driver = {
	499	.name = "tegra-gpio",
	500	.owner = THIS_MODULE,
8939ddc7	501	.pm = &tegra_gpio_pm_ops,
88d8951e SW	502	.of_match_table = tegra_gpio_of_match,
	503	},
	504	.probe = tegra_gpio_probe,
	505	};
	506
	507	static int __init tegra_gpio_init(void)
	508	{
	509	return platform_driver_register(&tegra_gpio_driver);
	510	}
3c92db9a EG	511	postcore_initcall(tegra_gpio_init);
	512
	513	#ifdef CONFIG_DEBUG_FS
	514
	515	#include <linux/debugfs.h>
	516	#include <linux/seq_file.h>
	517
	518	static int dbg_gpio_show(struct seq_file s, void unused)
	519	{
	520	int i;
	521	int j;
	522
4a3398ee	523	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	524	for (j = 0; j < 4; j++) {
3c92db9a EG	525	int gpio = tegra_gpio_compose(i, j, 0);
2e47b8b3 CC	526	seq_printf(s,
	527	"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
	528	i, j,
88d8951e SW	529	tegra_gpio_readl(GPIO_CNF(gpio)),
	530	tegra_gpio_readl(GPIO_OE(gpio)),
	531	tegra_gpio_readl(GPIO_OUT(gpio)),
	532	tegra_gpio_readl(GPIO_IN(gpio)),
	533	tegra_gpio_readl(GPIO_INT_STA(gpio)),
	534	tegra_gpio_readl(GPIO_INT_ENB(gpio)),
	535	tegra_gpio_readl(GPIO_INT_LVL(gpio)));
3c92db9a EG	536	}
	537	}
	538	return 0;
	539	}
	540
	541	static int dbg_gpio_open(struct inode inode, struct file file)
	542	{
	543	return single_open(file, dbg_gpio_show, &inode->i_private);
	544	}
	545
	546	static const struct file_operations debug_fops = {
	547	.open = dbg_gpio_open,
	548	.read = seq_read,
	549	.llseek = seq_lseek,
	550	.release = single_release,
	551	};
	552
	553	static int __init tegra_gpio_debuginit(void)
	554	{
	555	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
	556	NULL, NULL, &debug_fops);
	557	return 0;
	558	}
	559	late_initcall(tegra_gpio_debuginit);
	560	#endif