Commit | Line | Data |
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9c92ab61 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
3c92db9a EG |
2 | /* |
3 | * arch/arm/mach-tegra/gpio.c | |
4 | * | |
5 | * Copyright (c) 2010 Google, Inc | |
11da9054 | 6 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. |
3c92db9a EG |
7 | * |
8 | * Author: | |
9 | * Erik Gilling <konkers@google.com> | |
3c92db9a EG |
10 | */ |
11 | ||
641d0342 | 12 | #include <linux/err.h> |
3c92db9a EG |
13 | #include <linux/init.h> |
14 | #include <linux/irq.h> | |
2e47b8b3 | 15 | #include <linux/interrupt.h> |
3c92db9a | 16 | #include <linux/io.h> |
21041dab | 17 | #include <linux/gpio/driver.h> |
5c1e2c9d | 18 | #include <linux/of_device.h> |
88d8951e SW |
19 | #include <linux/platform_device.h> |
20 | #include <linux/module.h> | |
6f74dc9b | 21 | #include <linux/irqdomain.h> |
de88cbb7 | 22 | #include <linux/irqchip/chained_irq.h> |
3e215d0a | 23 | #include <linux/pinctrl/consumer.h> |
8939ddc7 | 24 | #include <linux/pm.h> |
3c92db9a | 25 | |
3c92db9a EG |
26 | #define GPIO_BANK(x) ((x) >> 5) |
27 | #define GPIO_PORT(x) (((x) >> 3) & 0x3) | |
28 | #define GPIO_BIT(x) ((x) & 0x7) | |
29 | ||
b546be0d | 30 | #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \ |
5c1e2c9d | 31 | GPIO_PORT(x) * 4) |
3c92db9a | 32 | |
b546be0d LD |
33 | #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00) |
34 | #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10) | |
35 | #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20) | |
36 | #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30) | |
37 | #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40) | |
38 | #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50) | |
39 | #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60) | |
40 | #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70) | |
3737de42 LD |
41 | #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0) |
42 | ||
b546be0d LD |
43 | |
44 | #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00) | |
45 | #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10) | |
46 | #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20) | |
3737de42 | 47 | #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30) |
b546be0d LD |
48 | #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40) |
49 | #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50) | |
50 | #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60) | |
3c92db9a EG |
51 | |
52 | #define GPIO_INT_LVL_MASK 0x010101 | |
53 | #define GPIO_INT_LVL_EDGE_RISING 0x000101 | |
54 | #define GPIO_INT_LVL_EDGE_FALLING 0x000100 | |
55 | #define GPIO_INT_LVL_EDGE_BOTH 0x010100 | |
56 | #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 | |
57 | #define GPIO_INT_LVL_LEVEL_LOW 0x000000 | |
58 | ||
b546be0d LD |
59 | struct tegra_gpio_info; |
60 | ||
3c92db9a | 61 | struct tegra_gpio_bank { |
539b7a39 TR |
62 | unsigned int bank; |
63 | unsigned int irq; | |
37174f33 DO |
64 | |
65 | /* | |
66 | * IRQ-core code uses raw locking, and thus, nested locking also | |
67 | * should be raw in order not to trip spinlock debug warnings. | |
68 | */ | |
69 | raw_spinlock_t lvl_lock[4]; | |
70 | ||
71 | /* Lock for updating debounce count register */ | |
72 | spinlock_t dbc_lock[4]; | |
73 | ||
8939ddc7 | 74 | #ifdef CONFIG_PM_SLEEP |
2e47b8b3 CC |
75 | u32 cnf[4]; |
76 | u32 out[4]; | |
77 | u32 oe[4]; | |
78 | u32 int_enb[4]; | |
79 | u32 int_lvl[4]; | |
203f31cb | 80 | u32 wake_enb[4]; |
3737de42 | 81 | u32 dbc_enb[4]; |
2e47b8b3 | 82 | #endif |
3737de42 | 83 | u32 dbc_cnt[4]; |
b546be0d | 84 | struct tegra_gpio_info *tgi; |
3c92db9a EG |
85 | }; |
86 | ||
171b92c8 | 87 | struct tegra_gpio_soc_config { |
3737de42 | 88 | bool debounce_supported; |
171b92c8 LD |
89 | u32 bank_stride; |
90 | u32 upper_offset; | |
91 | }; | |
92 | ||
b546be0d LD |
93 | struct tegra_gpio_info { |
94 | struct device *dev; | |
95 | void __iomem *regs; | |
96 | struct irq_domain *irq_domain; | |
97 | struct tegra_gpio_bank *bank_info; | |
98 | const struct tegra_gpio_soc_config *soc; | |
99 | struct gpio_chip gc; | |
100 | struct irq_chip ic; | |
b546be0d LD |
101 | u32 bank_count; |
102 | }; | |
88d8951e | 103 | |
b546be0d LD |
104 | static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi, |
105 | u32 val, u32 reg) | |
88d8951e | 106 | { |
fc782e47 | 107 | writel_relaxed(val, tgi->regs + reg); |
88d8951e SW |
108 | } |
109 | ||
b546be0d | 110 | static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg) |
88d8951e | 111 | { |
fc782e47 | 112 | return readl_relaxed(tgi->regs + reg); |
88d8951e | 113 | } |
3c92db9a | 114 | |
539b7a39 TR |
115 | static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port, |
116 | unsigned int bit) | |
3c92db9a EG |
117 | { |
118 | return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); | |
119 | } | |
120 | ||
b546be0d | 121 | static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg, |
539b7a39 | 122 | unsigned int gpio, u32 value) |
3c92db9a EG |
123 | { |
124 | u32 val; | |
125 | ||
126 | val = 0x100 << GPIO_BIT(gpio); | |
127 | if (value) | |
128 | val |= 1 << GPIO_BIT(gpio); | |
b546be0d | 129 | tegra_gpio_writel(tgi, val, reg); |
3c92db9a EG |
130 | } |
131 | ||
539b7a39 | 132 | static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio) |
3c92db9a | 133 | { |
b546be0d | 134 | tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1); |
3c92db9a EG |
135 | } |
136 | ||
539b7a39 | 137 | static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio) |
3c92db9a | 138 | { |
b546be0d | 139 | tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0); |
3c92db9a EG |
140 | } |
141 | ||
4bc17860 | 142 | static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset) |
3e215d0a | 143 | { |
11da9054 | 144 | return pinctrl_gpio_request(chip->base + offset); |
3e215d0a SW |
145 | } |
146 | ||
4bc17860 | 147 | static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset) |
3e215d0a | 148 | { |
b546be0d LD |
149 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
150 | ||
11da9054 | 151 | pinctrl_gpio_free(chip->base + offset); |
b546be0d | 152 | tegra_gpio_disable(tgi, offset); |
3e215d0a SW |
153 | } |
154 | ||
4bc17860 TR |
155 | static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset, |
156 | int value) | |
3c92db9a | 157 | { |
b546be0d LD |
158 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
159 | ||
160 | tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value); | |
3c92db9a EG |
161 | } |
162 | ||
4bc17860 | 163 | static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset) |
3c92db9a | 164 | { |
b546be0d | 165 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
539b7a39 | 166 | unsigned int bval = BIT(GPIO_BIT(offset)); |
b546be0d | 167 | |
195812e4 | 168 | /* If gpio is in output mode then read from the out value */ |
b546be0d LD |
169 | if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval) |
170 | return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval); | |
195812e4 | 171 | |
b546be0d | 172 | return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval); |
3c92db9a EG |
173 | } |
174 | ||
4bc17860 TR |
175 | static int tegra_gpio_direction_input(struct gpio_chip *chip, |
176 | unsigned int offset) | |
3c92db9a | 177 | { |
b546be0d | 178 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
11da9054 | 179 | int ret; |
b546be0d LD |
180 | |
181 | tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0); | |
182 | tegra_gpio_enable(tgi, offset); | |
11da9054 LW |
183 | |
184 | ret = pinctrl_gpio_direction_input(chip->base + offset); | |
185 | if (ret < 0) | |
186 | dev_err(tgi->dev, | |
187 | "Failed to set pinctrl input direction of GPIO %d: %d", | |
188 | chip->base + offset, ret); | |
189 | ||
190 | return ret; | |
3c92db9a EG |
191 | } |
192 | ||
4bc17860 TR |
193 | static int tegra_gpio_direction_output(struct gpio_chip *chip, |
194 | unsigned int offset, | |
195 | int value) | |
3c92db9a | 196 | { |
b546be0d | 197 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
11da9054 | 198 | int ret; |
b546be0d | 199 | |
3c92db9a | 200 | tegra_gpio_set(chip, offset, value); |
b546be0d LD |
201 | tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1); |
202 | tegra_gpio_enable(tgi, offset); | |
11da9054 LW |
203 | |
204 | ret = pinctrl_gpio_direction_output(chip->base + offset); | |
205 | if (ret < 0) | |
206 | dev_err(tgi->dev, | |
207 | "Failed to set pinctrl output direction of GPIO %d: %d", | |
208 | chip->base + offset, ret); | |
209 | ||
210 | return ret; | |
3c92db9a EG |
211 | } |
212 | ||
4bc17860 TR |
213 | static int tegra_gpio_get_direction(struct gpio_chip *chip, |
214 | unsigned int offset) | |
f002d07c LD |
215 | { |
216 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); | |
217 | u32 pin_mask = BIT(GPIO_BIT(offset)); | |
218 | u32 cnf, oe; | |
219 | ||
220 | cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset)); | |
221 | if (!(cnf & pin_mask)) | |
222 | return -EINVAL; | |
223 | ||
224 | oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)); | |
225 | ||
e42615ec MV |
226 | if (oe & pin_mask) |
227 | return GPIO_LINE_DIRECTION_OUT; | |
228 | ||
229 | return GPIO_LINE_DIRECTION_IN; | |
f002d07c LD |
230 | } |
231 | ||
3737de42 LD |
232 | static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, |
233 | unsigned int debounce) | |
234 | { | |
235 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); | |
236 | struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; | |
237 | unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000); | |
238 | unsigned long flags; | |
539b7a39 | 239 | unsigned int port; |
3737de42 LD |
240 | |
241 | if (!debounce_ms) { | |
242 | tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), | |
243 | offset, 0); | |
244 | return 0; | |
245 | } | |
246 | ||
247 | debounce_ms = min(debounce_ms, 255U); | |
248 | port = GPIO_PORT(offset); | |
249 | ||
250 | /* There is only one debounce count register per port and hence | |
251 | * set the maximum of current and requested debounce time. | |
252 | */ | |
253 | spin_lock_irqsave(&bank->dbc_lock[port], flags); | |
254 | if (bank->dbc_cnt[port] < debounce_ms) { | |
255 | tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset)); | |
256 | bank->dbc_cnt[port] = debounce_ms; | |
257 | } | |
258 | spin_unlock_irqrestore(&bank->dbc_lock[port], flags); | |
259 | ||
260 | tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1); | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
2956b5d9 MW |
265 | static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset, |
266 | unsigned long config) | |
267 | { | |
268 | u32 debounce; | |
269 | ||
270 | if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) | |
271 | return -ENOTSUPP; | |
272 | ||
273 | debounce = pinconf_to_config_argument(config); | |
274 | return tegra_gpio_set_debounce(chip, offset, debounce); | |
275 | } | |
276 | ||
4bc17860 | 277 | static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) |
438a99c0 | 278 | { |
b546be0d | 279 | struct tegra_gpio_info *tgi = gpiochip_get_data(chip); |
3c92db9a | 280 | |
b546be0d LD |
281 | return irq_find_mapping(tgi->irq_domain, offset); |
282 | } | |
3c92db9a | 283 | |
37337a8d | 284 | static void tegra_gpio_irq_ack(struct irq_data *d) |
3c92db9a | 285 | { |
b546be0d LD |
286 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
287 | struct tegra_gpio_info *tgi = bank->tgi; | |
539b7a39 | 288 | unsigned int gpio = d->hwirq; |
3c92db9a | 289 | |
b546be0d | 290 | tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio)); |
3c92db9a EG |
291 | } |
292 | ||
37337a8d | 293 | static void tegra_gpio_irq_mask(struct irq_data *d) |
3c92db9a | 294 | { |
b546be0d LD |
295 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
296 | struct tegra_gpio_info *tgi = bank->tgi; | |
539b7a39 | 297 | unsigned int gpio = d->hwirq; |
3c92db9a | 298 | |
b546be0d | 299 | tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0); |
3c92db9a EG |
300 | } |
301 | ||
37337a8d | 302 | static void tegra_gpio_irq_unmask(struct irq_data *d) |
3c92db9a | 303 | { |
b546be0d LD |
304 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
305 | struct tegra_gpio_info *tgi = bank->tgi; | |
539b7a39 | 306 | unsigned int gpio = d->hwirq; |
3c92db9a | 307 | |
b546be0d | 308 | tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1); |
3c92db9a EG |
309 | } |
310 | ||
37337a8d | 311 | static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
3c92db9a | 312 | { |
539b7a39 | 313 | unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type; |
37337a8d | 314 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
b546be0d | 315 | struct tegra_gpio_info *tgi = bank->tgi; |
3c92db9a | 316 | unsigned long flags; |
539b7a39 | 317 | u32 val; |
df231f28 | 318 | int ret; |
3c92db9a EG |
319 | |
320 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
321 | case IRQ_TYPE_EDGE_RISING: | |
322 | lvl_type = GPIO_INT_LVL_EDGE_RISING; | |
323 | break; | |
324 | ||
325 | case IRQ_TYPE_EDGE_FALLING: | |
326 | lvl_type = GPIO_INT_LVL_EDGE_FALLING; | |
327 | break; | |
328 | ||
329 | case IRQ_TYPE_EDGE_BOTH: | |
330 | lvl_type = GPIO_INT_LVL_EDGE_BOTH; | |
331 | break; | |
332 | ||
333 | case IRQ_TYPE_LEVEL_HIGH: | |
334 | lvl_type = GPIO_INT_LVL_LEVEL_HIGH; | |
335 | break; | |
336 | ||
337 | case IRQ_TYPE_LEVEL_LOW: | |
338 | lvl_type = GPIO_INT_LVL_LEVEL_LOW; | |
339 | break; | |
340 | ||
341 | default: | |
342 | return -EINVAL; | |
343 | } | |
344 | ||
37174f33 | 345 | raw_spin_lock_irqsave(&bank->lvl_lock[port], flags); |
3c92db9a | 346 | |
b546be0d | 347 | val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); |
3c92db9a EG |
348 | val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); |
349 | val |= lvl_type << GPIO_BIT(gpio); | |
b546be0d | 350 | tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio)); |
3c92db9a | 351 | |
37174f33 | 352 | raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags); |
3c92db9a | 353 | |
b546be0d LD |
354 | tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0); |
355 | tegra_gpio_enable(tgi, gpio); | |
d941136f | 356 | |
f78709a5 DO |
357 | ret = gpiochip_lock_as_irq(&tgi->gc, gpio); |
358 | if (ret) { | |
359 | dev_err(tgi->dev, | |
360 | "unable to lock Tegra GPIO %u as IRQ\n", gpio); | |
361 | tegra_gpio_disable(tgi, gpio); | |
362 | return ret; | |
363 | } | |
364 | ||
3c92db9a | 365 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
f170d71e | 366 | irq_set_handler_locked(d, handle_level_irq); |
3c92db9a | 367 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
f170d71e | 368 | irq_set_handler_locked(d, handle_edge_irq); |
3c92db9a EG |
369 | |
370 | return 0; | |
371 | } | |
372 | ||
df231f28 SW |
373 | static void tegra_gpio_irq_shutdown(struct irq_data *d) |
374 | { | |
b546be0d LD |
375 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
376 | struct tegra_gpio_info *tgi = bank->tgi; | |
539b7a39 | 377 | unsigned int gpio = d->hwirq; |
df231f28 | 378 | |
0cf253ee | 379 | tegra_gpio_irq_mask(d); |
b546be0d | 380 | gpiochip_unlock_as_irq(&tgi->gc, gpio); |
df231f28 SW |
381 | } |
382 | ||
bd0b9ac4 | 383 | static void tegra_gpio_irq_handler(struct irq_desc *desc) |
3c92db9a | 384 | { |
539b7a39 | 385 | unsigned int port, pin, gpio; |
9e9509e3 | 386 | bool unmasked = false; |
b546be0d LD |
387 | u32 lvl; |
388 | unsigned long sta; | |
98022940 | 389 | struct irq_chip *chip = irq_desc_get_chip(desc); |
476f8b4c | 390 | struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc); |
b546be0d | 391 | struct tegra_gpio_info *tgi = bank->tgi; |
3c92db9a | 392 | |
98022940 | 393 | chained_irq_enter(chip, desc); |
3c92db9a | 394 | |
3c92db9a | 395 | for (port = 0; port < 4; port++) { |
b546be0d LD |
396 | gpio = tegra_gpio_compose(bank->bank, port, 0); |
397 | sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) & | |
398 | tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)); | |
399 | lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)); | |
3c92db9a EG |
400 | |
401 | for_each_set_bit(pin, &sta, 8) { | |
b546be0d LD |
402 | tegra_gpio_writel(tgi, 1 << pin, |
403 | GPIO_INT_CLR(tgi, gpio)); | |
3c92db9a EG |
404 | |
405 | /* if gpio is edge triggered, clear condition | |
20a8a968 | 406 | * before executing the handler so that we don't |
3c92db9a EG |
407 | * miss edges |
408 | */ | |
9e9509e3 MM |
409 | if (!unmasked && lvl & (0x100 << pin)) { |
410 | unmasked = true; | |
98022940 | 411 | chained_irq_exit(chip, desc); |
3c92db9a EG |
412 | } |
413 | ||
c0debb3d GS |
414 | generic_handle_irq(irq_find_mapping(tgi->irq_domain, |
415 | gpio + pin)); | |
3c92db9a EG |
416 | } |
417 | } | |
418 | ||
419 | if (!unmasked) | |
98022940 | 420 | chained_irq_exit(chip, desc); |
3c92db9a EG |
421 | |
422 | } | |
423 | ||
8939ddc7 LD |
424 | #ifdef CONFIG_PM_SLEEP |
425 | static int tegra_gpio_resume(struct device *dev) | |
2e47b8b3 | 426 | { |
7ddb7dce | 427 | struct tegra_gpio_info *tgi = dev_get_drvdata(dev); |
539b7a39 | 428 | unsigned int b, p; |
2e47b8b3 | 429 | |
b546be0d LD |
430 | for (b = 0; b < tgi->bank_count; b++) { |
431 | struct tegra_gpio_bank *bank = &tgi->bank_info[b]; | |
2e47b8b3 CC |
432 | |
433 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
4bc17860 TR |
434 | unsigned int gpio = (b << 5) | (p << 3); |
435 | ||
b546be0d LD |
436 | tegra_gpio_writel(tgi, bank->cnf[p], |
437 | GPIO_CNF(tgi, gpio)); | |
3737de42 LD |
438 | |
439 | if (tgi->soc->debounce_supported) { | |
440 | tegra_gpio_writel(tgi, bank->dbc_cnt[p], | |
441 | GPIO_DBC_CNT(tgi, gpio)); | |
442 | tegra_gpio_writel(tgi, bank->dbc_enb[p], | |
443 | GPIO_MSK_DBC_EN(tgi, gpio)); | |
444 | } | |
445 | ||
b546be0d LD |
446 | tegra_gpio_writel(tgi, bank->out[p], |
447 | GPIO_OUT(tgi, gpio)); | |
448 | tegra_gpio_writel(tgi, bank->oe[p], | |
449 | GPIO_OE(tgi, gpio)); | |
450 | tegra_gpio_writel(tgi, bank->int_lvl[p], | |
451 | GPIO_INT_LVL(tgi, gpio)); | |
452 | tegra_gpio_writel(tgi, bank->int_enb[p], | |
453 | GPIO_INT_ENB(tgi, gpio)); | |
2e47b8b3 CC |
454 | } |
455 | } | |
456 | ||
8939ddc7 | 457 | return 0; |
2e47b8b3 CC |
458 | } |
459 | ||
8939ddc7 | 460 | static int tegra_gpio_suspend(struct device *dev) |
2e47b8b3 | 461 | { |
7ddb7dce | 462 | struct tegra_gpio_info *tgi = dev_get_drvdata(dev); |
539b7a39 | 463 | unsigned int b, p; |
2e47b8b3 | 464 | |
b546be0d LD |
465 | for (b = 0; b < tgi->bank_count; b++) { |
466 | struct tegra_gpio_bank *bank = &tgi->bank_info[b]; | |
2e47b8b3 CC |
467 | |
468 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
4bc17860 TR |
469 | unsigned int gpio = (b << 5) | (p << 3); |
470 | ||
b546be0d LD |
471 | bank->cnf[p] = tegra_gpio_readl(tgi, |
472 | GPIO_CNF(tgi, gpio)); | |
473 | bank->out[p] = tegra_gpio_readl(tgi, | |
474 | GPIO_OUT(tgi, gpio)); | |
475 | bank->oe[p] = tegra_gpio_readl(tgi, | |
476 | GPIO_OE(tgi, gpio)); | |
3737de42 LD |
477 | if (tgi->soc->debounce_supported) { |
478 | bank->dbc_enb[p] = tegra_gpio_readl(tgi, | |
479 | GPIO_MSK_DBC_EN(tgi, gpio)); | |
480 | bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) | | |
481 | bank->dbc_enb[p]; | |
482 | } | |
483 | ||
b546be0d LD |
484 | bank->int_enb[p] = tegra_gpio_readl(tgi, |
485 | GPIO_INT_ENB(tgi, gpio)); | |
486 | bank->int_lvl[p] = tegra_gpio_readl(tgi, | |
487 | GPIO_INT_LVL(tgi, gpio)); | |
203f31cb JL |
488 | |
489 | /* Enable gpio irq for wake up source */ | |
b546be0d LD |
490 | tegra_gpio_writel(tgi, bank->wake_enb[p], |
491 | GPIO_INT_ENB(tgi, gpio)); | |
2e47b8b3 CC |
492 | } |
493 | } | |
9ccaf106 | 494 | |
8939ddc7 | 495 | return 0; |
2e47b8b3 CC |
496 | } |
497 | ||
203f31cb | 498 | static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) |
2e47b8b3 | 499 | { |
37337a8d | 500 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
539b7a39 | 501 | unsigned int gpio = d->hwirq; |
203f31cb | 502 | u32 port, bit, mask; |
f56d979c DO |
503 | int err; |
504 | ||
505 | err = irq_set_irq_wake(bank->irq, enable); | |
506 | if (err) | |
507 | return err; | |
203f31cb JL |
508 | |
509 | port = GPIO_PORT(gpio); | |
510 | bit = GPIO_BIT(gpio); | |
511 | mask = BIT(bit); | |
512 | ||
513 | if (enable) | |
514 | bank->wake_enb[port] |= mask; | |
515 | else | |
516 | bank->wake_enb[port] &= ~mask; | |
517 | ||
f56d979c | 518 | return 0; |
2e47b8b3 CC |
519 | } |
520 | #endif | |
3c92db9a | 521 | |
b59d5fb7 SP |
522 | #ifdef CONFIG_DEBUG_FS |
523 | ||
524 | #include <linux/debugfs.h> | |
525 | #include <linux/seq_file.h> | |
526 | ||
2773eb2f | 527 | static int tegra_dbg_gpio_show(struct seq_file *s, void *unused) |
b59d5fb7 | 528 | { |
b546be0d | 529 | struct tegra_gpio_info *tgi = s->private; |
539b7a39 | 530 | unsigned int i, j; |
b59d5fb7 | 531 | |
b546be0d | 532 | for (i = 0; i < tgi->bank_count; i++) { |
b59d5fb7 | 533 | for (j = 0; j < 4; j++) { |
539b7a39 | 534 | unsigned int gpio = tegra_gpio_compose(i, j, 0); |
4bc17860 | 535 | |
b59d5fb7 | 536 | seq_printf(s, |
539b7a39 | 537 | "%u:%u %02x %02x %02x %02x %02x %02x %06x\n", |
b59d5fb7 | 538 | i, j, |
b546be0d LD |
539 | tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)), |
540 | tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)), | |
541 | tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)), | |
542 | tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)), | |
543 | tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)), | |
544 | tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)), | |
545 | tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio))); | |
b59d5fb7 SP |
546 | } |
547 | } | |
548 | return 0; | |
549 | } | |
550 | ||
2773eb2f | 551 | DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio); |
b59d5fb7 | 552 | |
b546be0d | 553 | static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) |
b59d5fb7 | 554 | { |
9b3b6238 LW |
555 | debugfs_create_file("tegra_gpio", 0444, NULL, tgi, |
556 | &tegra_dbg_gpio_fops); | |
b59d5fb7 SP |
557 | } |
558 | ||
559 | #else | |
560 | ||
b546be0d | 561 | static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi) |
b59d5fb7 SP |
562 | { |
563 | } | |
564 | ||
565 | #endif | |
566 | ||
8939ddc7 | 567 | static const struct dev_pm_ops tegra_gpio_pm_ops = { |
9ccaf106 | 568 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume) |
8939ddc7 LD |
569 | }; |
570 | ||
6ea68fc0 DO |
571 | static struct lock_class_key gpio_lock_class; |
572 | static struct lock_class_key gpio_request_class; | |
573 | ||
3836309d | 574 | static int tegra_gpio_probe(struct platform_device *pdev) |
3c92db9a | 575 | { |
b546be0d | 576 | struct tegra_gpio_info *tgi; |
3c92db9a | 577 | struct tegra_gpio_bank *bank; |
539b7a39 | 578 | unsigned int gpio, i, j; |
f57f98a6 | 579 | int ret; |
3c92db9a | 580 | |
b546be0d LD |
581 | tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL); |
582 | if (!tgi) | |
583 | return -ENODEV; | |
584 | ||
20133bd5 | 585 | tgi->soc = of_device_get_match_data(&pdev->dev); |
b546be0d | 586 | tgi->dev = &pdev->dev; |
5c1e2c9d | 587 | |
56420903 TR |
588 | ret = platform_irq_count(pdev); |
589 | if (ret < 0) | |
590 | return ret; | |
591 | ||
592 | tgi->bank_count = ret; | |
593 | ||
b546be0d | 594 | if (!tgi->bank_count) { |
3391811c SW |
595 | dev_err(&pdev->dev, "Missing IRQ resource\n"); |
596 | return -ENODEV; | |
597 | } | |
598 | ||
b546be0d LD |
599 | tgi->gc.label = "tegra-gpio"; |
600 | tgi->gc.request = tegra_gpio_request; | |
601 | tgi->gc.free = tegra_gpio_free; | |
602 | tgi->gc.direction_input = tegra_gpio_direction_input; | |
603 | tgi->gc.get = tegra_gpio_get; | |
604 | tgi->gc.direction_output = tegra_gpio_direction_output; | |
605 | tgi->gc.set = tegra_gpio_set; | |
f002d07c | 606 | tgi->gc.get_direction = tegra_gpio_get_direction; |
b546be0d LD |
607 | tgi->gc.to_irq = tegra_gpio_to_irq; |
608 | tgi->gc.base = 0; | |
609 | tgi->gc.ngpio = tgi->bank_count * 32; | |
610 | tgi->gc.parent = &pdev->dev; | |
611 | tgi->gc.of_node = pdev->dev.of_node; | |
612 | ||
613 | tgi->ic.name = "GPIO"; | |
614 | tgi->ic.irq_ack = tegra_gpio_irq_ack; | |
615 | tgi->ic.irq_mask = tegra_gpio_irq_mask; | |
616 | tgi->ic.irq_unmask = tegra_gpio_irq_unmask; | |
617 | tgi->ic.irq_set_type = tegra_gpio_irq_set_type; | |
618 | tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown; | |
619 | #ifdef CONFIG_PM_SLEEP | |
620 | tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake; | |
621 | #endif | |
622 | ||
623 | platform_set_drvdata(pdev, tgi); | |
3391811c | 624 | |
20133bd5 | 625 | if (tgi->soc->debounce_supported) |
2956b5d9 | 626 | tgi->gc.set_config = tegra_gpio_set_config; |
3737de42 | 627 | |
9b882269 | 628 | tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count, |
b546be0d LD |
629 | sizeof(*tgi->bank_info), GFP_KERNEL); |
630 | if (!tgi->bank_info) | |
9b882269 | 631 | return -ENOMEM; |
3391811c | 632 | |
b546be0d LD |
633 | tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node, |
634 | tgi->gc.ngpio, | |
635 | &irq_domain_simple_ops, NULL); | |
636 | if (!tgi->irq_domain) | |
d0235677 | 637 | return -ENODEV; |
6f74dc9b | 638 | |
b546be0d | 639 | for (i = 0; i < tgi->bank_count; i++) { |
9c07409c | 640 | ret = platform_get_irq(pdev, i); |
15bddb7d | 641 | if (ret < 0) |
9c07409c | 642 | return ret; |
88d8951e | 643 | |
b546be0d | 644 | bank = &tgi->bank_info[i]; |
88d8951e | 645 | bank->bank = i; |
9c07409c | 646 | bank->irq = ret; |
b546be0d | 647 | bank->tgi = tgi; |
88d8951e SW |
648 | } |
649 | ||
a0b81f1c | 650 | tgi->regs = devm_platform_ioremap_resource(pdev, 0); |
b546be0d LD |
651 | if (IS_ERR(tgi->regs)) |
652 | return PTR_ERR(tgi->regs); | |
88d8951e | 653 | |
b546be0d | 654 | for (i = 0; i < tgi->bank_count; i++) { |
3c92db9a EG |
655 | for (j = 0; j < 4; j++) { |
656 | int gpio = tegra_gpio_compose(i, j, 0); | |
4bc17860 | 657 | |
b546be0d | 658 | tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio)); |
3c92db9a EG |
659 | } |
660 | } | |
661 | ||
b546be0d | 662 | ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi); |
f57f98a6 | 663 | if (ret < 0) { |
b546be0d | 664 | irq_domain_remove(tgi->irq_domain); |
f57f98a6 SW |
665 | return ret; |
666 | } | |
3c92db9a | 667 | |
b546be0d LD |
668 | for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) { |
669 | int irq = irq_create_mapping(tgi->irq_domain, gpio); | |
47008001 | 670 | /* No validity check; all Tegra GPIOs are valid IRQs */ |
3c92db9a | 671 | |
b546be0d | 672 | bank = &tgi->bank_info[GPIO_BANK(gpio)]; |
3c92db9a | 673 | |
47008001 | 674 | irq_set_chip_data(irq, bank); |
6ea68fc0 | 675 | irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class); |
b546be0d | 676 | irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq); |
3c92db9a EG |
677 | } |
678 | ||
b546be0d LD |
679 | for (i = 0; i < tgi->bank_count; i++) { |
680 | bank = &tgi->bank_info[i]; | |
3c92db9a | 681 | |
e88d251d RK |
682 | irq_set_chained_handler_and_data(bank->irq, |
683 | tegra_gpio_irq_handler, bank); | |
3c92db9a | 684 | |
3737de42 | 685 | for (j = 0; j < 4; j++) { |
37174f33 | 686 | raw_spin_lock_init(&bank->lvl_lock[j]); |
3737de42 LD |
687 | spin_lock_init(&bank->dbc_lock[j]); |
688 | } | |
3c92db9a EG |
689 | } |
690 | ||
b546be0d | 691 | tegra_gpio_debuginit(tgi); |
b59d5fb7 | 692 | |
3c92db9a EG |
693 | return 0; |
694 | } | |
695 | ||
804f5680 | 696 | static const struct tegra_gpio_soc_config tegra20_gpio_config = { |
171b92c8 LD |
697 | .bank_stride = 0x80, |
698 | .upper_offset = 0x800, | |
699 | }; | |
700 | ||
804f5680 | 701 | static const struct tegra_gpio_soc_config tegra30_gpio_config = { |
171b92c8 LD |
702 | .bank_stride = 0x100, |
703 | .upper_offset = 0x80, | |
704 | }; | |
705 | ||
3737de42 LD |
706 | static const struct tegra_gpio_soc_config tegra210_gpio_config = { |
707 | .debounce_supported = true, | |
708 | .bank_stride = 0x100, | |
709 | .upper_offset = 0x80, | |
710 | }; | |
711 | ||
171b92c8 | 712 | static const struct of_device_id tegra_gpio_of_match[] = { |
3737de42 | 713 | { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config }, |
171b92c8 LD |
714 | { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config }, |
715 | { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config }, | |
716 | { }, | |
717 | }; | |
718 | ||
88d8951e SW |
719 | static struct platform_driver tegra_gpio_driver = { |
720 | .driver = { | |
721 | .name = "tegra-gpio", | |
8939ddc7 | 722 | .pm = &tegra_gpio_pm_ops, |
88d8951e SW |
723 | .of_match_table = tegra_gpio_of_match, |
724 | }, | |
725 | .probe = tegra_gpio_probe, | |
726 | }; | |
727 | ||
728 | static int __init tegra_gpio_init(void) | |
729 | { | |
730 | return platform_driver_register(&tegra_gpio_driver); | |
731 | } | |
40b25bce | 732 | subsys_initcall(tegra_gpio_init); |