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Merge tag 'gfs2-v6.3-fix' of git://git.kernel.org/pub/scm/linux/kernel/git/gfs2/linux...
[linux-block.git] / drivers / gpio / gpio-tegra.c
CommitLineData
9c92ab61 1// SPDX-License-Identifier: GPL-2.0-only
3c92db9a
EG		 2/*
3 * arch/arm/mach-tegra/gpio.c
4 *
5 * Copyright (c) 2010 Google, Inc
11da9054 6 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
3c92db9a
EG		 7 *
8 * Author:
9 * Erik Gilling <konkers@google.com>
3c92db9a
EG		 10 */
11
641d0342 12#include <linux/err.h>
3c92db9a
EG		 13#include <linux/init.h>
14#include <linux/irq.h>
2e47b8b3 15#include <linux/interrupt.h>
3c92db9a 16#include <linux/io.h>
21041dab 17#include <linux/gpio/driver.h>
5c1e2c9d 18#include <linux/of_device.h>
88d8951e
SW		 19#include <linux/platform_device.h>
20#include <linux/module.h>
7d1aa08a 21#include <linux/seq_file.h>
6f74dc9b 22#include <linux/irqdomain.h>
de88cbb7 23#include <linux/irqchip/chained_irq.h>
3e215d0a 24#include <linux/pinctrl/consumer.h>
8939ddc7 25#include <linux/pm.h>
3c92db9a 26
3c92db9a
EG		 27#define GPIO_BANK(x) ((x) >> 5)
28#define GPIO_PORT(x) (((x) >> 3) & 0x3)
29#define GPIO_BIT(x) ((x) & 0x7)
30
b546be0d 31#define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
5c1e2c9d 32 GPIO_PORT(x) * 4)
3c92db9a 33
b546be0d
LD		 34#define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
35#define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
36#define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
37#define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
38#define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
39#define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
40#define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
41#define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
3737de42
LD		 42#define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
43
b546be0d
LD		 44
45#define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
46#define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
47#define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
3737de42 48#define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
b546be0d
LD		 49#define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
50#define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
51#define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
3c92db9a
EG		 52
53#define GPIO_INT_LVL_MASK 0x010101
54#define GPIO_INT_LVL_EDGE_RISING 0x000101
55#define GPIO_INT_LVL_EDGE_FALLING 0x000100
56#define GPIO_INT_LVL_EDGE_BOTH 0x010100
57#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
58#define GPIO_INT_LVL_LEVEL_LOW 0x000000
59
b546be0d
LD		 60struct tegra_gpio_info;
61
3c92db9a 62struct tegra_gpio_bank {
539b7a39 63 unsigned int bank;
37174f33
DO		 64
65 /*
66 * IRQ-core code uses raw locking, and thus, nested locking also
67 * should be raw in order not to trip spinlock debug warnings.
68 */
69 raw_spinlock_t lvl_lock[4];
70
71 /* Lock for updating debounce count register */
72 spinlock_t dbc_lock[4];
73
8939ddc7 74#ifdef CONFIG_PM_SLEEP
2e47b8b3
CC		 75 u32 cnf[4];
76 u32 out[4];
77 u32 oe[4];
78 u32 int_enb[4];
79 u32 int_lvl[4];
203f31cb 80 u32 wake_enb[4];
3737de42 81 u32 dbc_enb[4];
2e47b8b3 82#endif
3737de42 83 u32 dbc_cnt[4];
3c92db9a
EG		 84};
85
171b92c8 86struct tegra_gpio_soc_config {
3737de42 87 bool debounce_supported;
171b92c8
LD		 88 u32 bank_stride;
89 u32 upper_offset;
90};
91
b546be0d
LD		 92struct tegra_gpio_info {
93 struct device *dev;
94 void __iomem *regs;
b546be0d
LD		 95 struct tegra_gpio_bank *bank_info;
96 const struct tegra_gpio_soc_config *soc;
97 struct gpio_chip gc;
b546be0d 98 u32 bank_count;
66fecef5 99 unsigned int *irqs;
b546be0d 100};
88d8951e 101
b546be0d
LD		 102static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
103 u32 val, u32 reg)
88d8951e 104{
fc782e47 105 writel_relaxed(val, tgi->regs + reg);
88d8951e
SW		 106}
107
b546be0d 108static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
88d8951e 109{
fc782e47 110 return readl_relaxed(tgi->regs + reg);
88d8951e 111}
3c92db9a 112
539b7a39
TR		 113static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
114 unsigned int bit)
3c92db9a
EG		 115{
116 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
117}
118
b546be0d 119static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
539b7a39 120 unsigned int gpio, u32 value)
3c92db9a
EG		 121{
122 u32 val;
123
124 val = 0x100 << GPIO_BIT(gpio);
125 if (value)
126 val |= 1 << GPIO_BIT(gpio);
b546be0d 127 tegra_gpio_writel(tgi, val, reg);
3c92db9a
EG		 128}
129
539b7a39 130static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
3c92db9a 131{
b546be0d 132 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
3c92db9a
EG		 133}
134
539b7a39 135static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
3c92db9a 136{
b546be0d 137 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
3c92db9a
EG		 138}
139
4bc17860 140static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
3e215d0a 141{
11da9054 142 return pinctrl_gpio_request(chip->base + offset);
3e215d0a
SW		 143}
144
4bc17860 145static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
3e215d0a 146{
b546be0d
LD		 147 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
148
11da9054 149 pinctrl_gpio_free(chip->base + offset);
b546be0d 150 tegra_gpio_disable(tgi, offset);
3e215d0a
SW		 151}
152
4bc17860
TR		 153static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
154 int value)
3c92db9a 155{
b546be0d
LD		 156 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
157
158 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
3c92db9a
EG		 159}
160
4bc17860 161static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
3c92db9a 162{
b546be0d 163 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
539b7a39 164 unsigned int bval = BIT(GPIO_BIT(offset));
b546be0d 165
195812e4 166 /* If gpio is in output mode then read from the out value */
b546be0d
LD		 167 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
168 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
195812e4 169
b546be0d 170 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
3c92db9a
EG		 171}
172
4bc17860
TR		 173static int tegra_gpio_direction_input(struct gpio_chip *chip,
174 unsigned int offset)
3c92db9a 175{
b546be0d 176 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
11da9054 177 int ret;
b546be0d
LD		 178
179 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
180 tegra_gpio_enable(tgi, offset);
11da9054
LW		 181
182 ret = pinctrl_gpio_direction_input(chip->base + offset);
183 if (ret < 0)
184 dev_err(tgi->dev,
185 "Failed to set pinctrl input direction of GPIO %d: %d",
186 chip->base + offset, ret);
187
188 return ret;
3c92db9a
EG		 189}
190
4bc17860
TR		 191static int tegra_gpio_direction_output(struct gpio_chip *chip,
192 unsigned int offset,
193 int value)
3c92db9a 194{
b546be0d 195 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
11da9054 196 int ret;
b546be0d 197
3c92db9a 198 tegra_gpio_set(chip, offset, value);
b546be0d
LD		 199 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
200 tegra_gpio_enable(tgi, offset);
11da9054
LW		 201
202 ret = pinctrl_gpio_direction_output(chip->base + offset);
203 if (ret < 0)
204 dev_err(tgi->dev,
205 "Failed to set pinctrl output direction of GPIO %d: %d",
206 chip->base + offset, ret);
207
208 return ret;
3c92db9a
EG		 209}
210
4bc17860
TR		 211static int tegra_gpio_get_direction(struct gpio_chip *chip,
212 unsigned int offset)
f002d07c
LD		 213{
214 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
215 u32 pin_mask = BIT(GPIO_BIT(offset));
216 u32 cnf, oe;
217
218 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
219 if (!(cnf & pin_mask))
220 return -EINVAL;
221
222 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
223
e42615ec
MV		 224 if (oe & pin_mask)
225 return GPIO_LINE_DIRECTION_OUT;
226
227 return GPIO_LINE_DIRECTION_IN;
f002d07c
LD		 228}
229
3737de42
LD		 230static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
231 unsigned int debounce)
232{
233 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
234 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
235 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
236 unsigned long flags;
539b7a39 237 unsigned int port;
3737de42
LD		 238
239 if (!debounce_ms) {
240 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
241 offset, 0);
242 return 0;
243 }
244
245 debounce_ms = min(debounce_ms, 255U);
246 port = GPIO_PORT(offset);
247
248 /* There is only one debounce count register per port and hence
249 * set the maximum of current and requested debounce time.
250 */
251 spin_lock_irqsave(&bank->dbc_lock[port], flags);
252 if (bank->dbc_cnt[port] < debounce_ms) {
253 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
254 bank->dbc_cnt[port] = debounce_ms;
255 }
256 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
257
258 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
259
260 return 0;
261}
262
2956b5d9
MW		 263static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
264 unsigned long config)
265{
266 u32 debounce;
267
268 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
269 return -ENOTSUPP;
270
271 debounce = pinconf_to_config_argument(config);
272 return tegra_gpio_set_debounce(chip, offset, debounce);
273}
274
37337a8d 275static void tegra_gpio_irq_ack(struct irq_data *d)
3c92db9a 276{
66fecef5
TR		 277 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
278 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
539b7a39 279 unsigned int gpio = d->hwirq;
3c92db9a 280
b546be0d 281 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
3c92db9a
EG		 282}
283
37337a8d 284static void tegra_gpio_irq_mask(struct irq_data *d)
3c92db9a 285{
66fecef5
TR		 286 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
287 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
539b7a39 288 unsigned int gpio = d->hwirq;
3c92db9a 289
b546be0d 290 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
7d1aa08a 291 gpiochip_disable_irq(chip, gpio);
3c92db9a
EG		 292}
293
37337a8d 294static void tegra_gpio_irq_unmask(struct irq_data *d)
3c92db9a 295{
66fecef5
TR		 296 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
297 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
539b7a39 298 unsigned int gpio = d->hwirq;
3c92db9a 299
7d1aa08a 300 gpiochip_enable_irq(chip, gpio);
b546be0d 301 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
3c92db9a
EG		 302}
303
37337a8d 304static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
3c92db9a 305{
539b7a39 306 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
66fecef5
TR		 307 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
308 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
309 struct tegra_gpio_bank *bank;
3c92db9a 310 unsigned long flags;
df231f28 311 int ret;
66fecef5
TR		 312 u32 val;
313
314 bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
3c92db9a
EG		 315
316 switch (type & IRQ_TYPE_SENSE_MASK) {
317 case IRQ_TYPE_EDGE_RISING:
318 lvl_type = GPIO_INT_LVL_EDGE_RISING;
319 break;
320
321 case IRQ_TYPE_EDGE_FALLING:
322 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
323 break;
324
325 case IRQ_TYPE_EDGE_BOTH:
326 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
327 break;
328
329 case IRQ_TYPE_LEVEL_HIGH:
330 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
331 break;
332
333 case IRQ_TYPE_LEVEL_LOW:
334 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
335 break;
336
337 default:
338 return -EINVAL;
339 }
340
37174f33 341 raw_spin_lock_irqsave(&bank->lvl_lock[port], flags);
3c92db9a 342
b546be0d 343 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
3c92db9a
EG		 344 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
345 val |= lvl_type << GPIO_BIT(gpio);
b546be0d 346 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
3c92db9a 347
37174f33 348 raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
3c92db9a 349
b546be0d
LD		 350 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
351 tegra_gpio_enable(tgi, gpio);
d941136f 352
f78709a5
DO		 353 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
354 if (ret) {
355 dev_err(tgi->dev,
356 "unable to lock Tegra GPIO %u as IRQ\n", gpio);
357 tegra_gpio_disable(tgi, gpio);
358 return ret;
359 }
360
3c92db9a 361 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
f170d71e 362 irq_set_handler_locked(d, handle_level_irq);
3c92db9a 363 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
f170d71e 364 irq_set_handler_locked(d, handle_edge_irq);
3c92db9a 365
66fecef5
TR		 366 if (d->parent_data)
367 ret = irq_chip_set_type_parent(d, type);
368
369 return ret;
3c92db9a
EG		 370}
371
df231f28
SW		 372static void tegra_gpio_irq_shutdown(struct irq_data *d)
373{
66fecef5
TR		 374 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
375 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
539b7a39 376 unsigned int gpio = d->hwirq;
df231f28 377
0cf253ee 378 tegra_gpio_irq_mask(d);
b546be0d 379 gpiochip_unlock_as_irq(&tgi->gc, gpio);
df231f28
SW		 380}
381
bd0b9ac4 382static void tegra_gpio_irq_handler(struct irq_desc *desc)
3c92db9a 383{
66fecef5
TR		 384 struct tegra_gpio_info *tgi = irq_desc_get_handler_data(desc);
385 struct irq_chip *chip = irq_desc_get_chip(desc);
386 struct irq_domain *domain = tgi->gc.irq.domain;
387 unsigned int irq = irq_desc_get_irq(desc);
388 struct tegra_gpio_bank *bank = NULL;
389 unsigned int port, pin, gpio, i;
9e9509e3 390 bool unmasked = false;
b546be0d 391 unsigned long sta;
66fecef5
TR		 392 u32 lvl;
393
394 for (i = 0; i < tgi->bank_count; i++) {
395 if (tgi->irqs[i] == irq) {
396 bank = &tgi->bank_info[i];
397 break;
398 }
399 }
400
401 if (WARN_ON(bank == NULL))
402 return;
3c92db9a 403
98022940 404 chained_irq_enter(chip, desc);
3c92db9a 405
3c92db9a 406 for (port = 0; port < 4; port++) {
b546be0d
LD		 407 gpio = tegra_gpio_compose(bank->bank, port, 0);
408 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
409 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
410 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
3c92db9a
EG		 411
412 for_each_set_bit(pin, &sta, 8) {
dbd1c54f
MZ		 413 int ret;
414
b546be0d
LD		 415 tegra_gpio_writel(tgi, 1 << pin,
416 GPIO_INT_CLR(tgi, gpio));
3c92db9a
EG		 417
418 /* if gpio is edge triggered, clear condition
20a8a968 419 * before executing the handler so that we don't
3c92db9a
EG		 420 * miss edges
421 */
9e9509e3
MM		 422 if (!unmasked && lvl & (0x100 << pin)) {
423 unmasked = true;
98022940 424 chained_irq_exit(chip, desc);
3c92db9a
EG		 425 }
426
dbd1c54f
MZ		 427 ret = generic_handle_domain_irq(domain, gpio + pin);
428 WARN_RATELIMIT(ret, "hwirq = %d", gpio + pin);
3c92db9a
EG		 429 }
430 }
431
432 if (!unmasked)
98022940 433 chained_irq_exit(chip, desc);
66fecef5
TR		 434}
435
718ff946
DO		 436static int tegra_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
437 unsigned int hwirq,
438 unsigned int type,
439 unsigned int *parent_hwirq,
66fecef5
TR		 440 unsigned int *parent_type)
441{
442 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq);
443 *parent_type = type;
3c92db9a 444
66fecef5
TR		 445 return 0;
446}
447
91a29af4
MZ		 448static int tegra_gpio_populate_parent_fwspec(struct gpio_chip *chip,
449 union gpio_irq_fwspec *gfwspec,
450 unsigned int parent_hwirq,
451 unsigned int parent_type)
66fecef5 452{
91a29af4 453 struct irq_fwspec *fwspec = &gfwspec->fwspec;
66fecef5
TR		 454
455 fwspec->fwnode = chip->irq.parent_domain->fwnode;
456 fwspec->param_count = 3;
457 fwspec->param[0] = 0;
458 fwspec->param[1] = parent_hwirq;
459 fwspec->param[2] = parent_type;
460
91a29af4 461 return 0;
3c92db9a
EG		 462}
463
8939ddc7
LD		 464#ifdef CONFIG_PM_SLEEP
465static int tegra_gpio_resume(struct device *dev)
2e47b8b3 466{
7ddb7dce 467 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
539b7a39 468 unsigned int b, p;
2e47b8b3 469
b546be0d
LD		 470 for (b = 0; b < tgi->bank_count; b++) {
471 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
2e47b8b3
CC		 472
473 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
4bc17860
TR		 474 unsigned int gpio = (b << 5) | (p << 3);
475
b546be0d
LD		 476 tegra_gpio_writel(tgi, bank->cnf[p],
477 GPIO_CNF(tgi, gpio));
3737de42
LD		 478
479 if (tgi->soc->debounce_supported) {
480 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
481 GPIO_DBC_CNT(tgi, gpio));
482 tegra_gpio_writel(tgi, bank->dbc_enb[p],
483 GPIO_MSK_DBC_EN(tgi, gpio));
484 }
485
b546be0d
LD		 486 tegra_gpio_writel(tgi, bank->out[p],
487 GPIO_OUT(tgi, gpio));
488 tegra_gpio_writel(tgi, bank->oe[p],
489 GPIO_OE(tgi, gpio));
490 tegra_gpio_writel(tgi, bank->int_lvl[p],
491 GPIO_INT_LVL(tgi, gpio));
492 tegra_gpio_writel(tgi, bank->int_enb[p],
493 GPIO_INT_ENB(tgi, gpio));
2e47b8b3
CC		 494 }
495 }
496
8939ddc7 497 return 0;
2e47b8b3
CC		 498}
499
8939ddc7 500static int tegra_gpio_suspend(struct device *dev)
2e47b8b3 501{
7ddb7dce 502 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
539b7a39 503 unsigned int b, p;
2e47b8b3 504
b546be0d
LD		 505 for (b = 0; b < tgi->bank_count; b++) {
506 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
2e47b8b3
CC		 507
508 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
4bc17860
TR		 509 unsigned int gpio = (b << 5) | (p << 3);
510
b546be0d
LD		 511 bank->cnf[p] = tegra_gpio_readl(tgi,
512 GPIO_CNF(tgi, gpio));
513 bank->out[p] = tegra_gpio_readl(tgi,
514 GPIO_OUT(tgi, gpio));
515 bank->oe[p] = tegra_gpio_readl(tgi,
516 GPIO_OE(tgi, gpio));
3737de42
LD		 517 if (tgi->soc->debounce_supported) {
518 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
519 GPIO_MSK_DBC_EN(tgi, gpio));
520 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
521 bank->dbc_enb[p];
522 }
523
b546be0d
LD		 524 bank->int_enb[p] = tegra_gpio_readl(tgi,
525 GPIO_INT_ENB(tgi, gpio));
526 bank->int_lvl[p] = tegra_gpio_readl(tgi,
527 GPIO_INT_LVL(tgi, gpio));
203f31cb
JL		 528
529 /* Enable gpio irq for wake up source */
b546be0d
LD		 530 tegra_gpio_writel(tgi, bank->wake_enb[p],
531 GPIO_INT_ENB(tgi, gpio));
2e47b8b3
CC		 532 }
533 }
9ccaf106 534
8939ddc7 535 return 0;
2e47b8b3
CC		 536}
537
203f31cb 538static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
2e47b8b3 539{
66fecef5
TR		 540 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
541 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
542 struct tegra_gpio_bank *bank;
539b7a39 543 unsigned int gpio = d->hwirq;
203f31cb 544 u32 port, bit, mask;
27f8feea 545 int err;
f56d979c 546
66fecef5 547 bank = &tgi->bank_info[GPIO_BANK(d->hwirq)];
203f31cb
JL		 548
549 port = GPIO_PORT(gpio);
550 bit = GPIO_BIT(gpio);
551 mask = BIT(bit);
552
27f8feea
DO		 553 err = irq_set_irq_wake(tgi->irqs[bank->bank], enable);
554 if (err)
555 return err;
556
557 if (d->parent_data) {
558 err = irq_chip_set_wake_parent(d, enable);
559 if (err) {
560 irq_set_irq_wake(tgi->irqs[bank->bank], !enable);
561 return err;
562 }
563 }
564
203f31cb
JL		 565 if (enable)
566 bank->wake_enb[port] |= mask;
567 else
568 bank->wake_enb[port] &= ~mask;
569
f56d979c 570 return 0;
2e47b8b3
CC		 571}
572#endif
3c92db9a 573
718ff946
DO		 574static int tegra_gpio_irq_set_affinity(struct irq_data *data,
575 const struct cpumask *dest,
66fecef5
TR		 576 bool force)
577{
578 if (data->parent_data)
579 return irq_chip_set_affinity_parent(data, dest, force);
580
581 return -EINVAL;
582}
583
584static int tegra_gpio_irq_request_resources(struct irq_data *d)
585{
586 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
587 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
588
589 tegra_gpio_enable(tgi, d->hwirq);
590
591 return gpiochip_reqres_irq(chip, d->hwirq);
592}
593
594static void tegra_gpio_irq_release_resources(struct irq_data *d)
595{
596 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
597 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
598
599 gpiochip_relres_irq(chip, d->hwirq);
600 tegra_gpio_enable(tgi, d->hwirq);
601}
602
7d1aa08a
SR		 603static void tegra_gpio_irq_print_chip(struct irq_data *d, struct seq_file *s)
604{
605 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
606
607 seq_printf(s, dev_name(chip->parent));
608}
609
610static const struct irq_chip tegra_gpio_irq_chip = {
611 .irq_shutdown = tegra_gpio_irq_shutdown,
612 .irq_ack = tegra_gpio_irq_ack,
613 .irq_mask = tegra_gpio_irq_mask,
614 .irq_unmask = tegra_gpio_irq_unmask,
615 .irq_set_type = tegra_gpio_irq_set_type,
616#ifdef CONFIG_PM_SLEEP
617 .irq_set_wake = tegra_gpio_irq_set_wake,
618#endif
619 .irq_print_chip = tegra_gpio_irq_print_chip,
620 .irq_request_resources = tegra_gpio_irq_request_resources,
621 .irq_release_resources = tegra_gpio_irq_release_resources,
622 .flags = IRQCHIP_IMMUTABLE,
623};
624
625static const struct irq_chip tegra210_gpio_irq_chip = {
626 .irq_shutdown = tegra_gpio_irq_shutdown,
627 .irq_ack = tegra_gpio_irq_ack,
628 .irq_mask = tegra_gpio_irq_mask,
629 .irq_unmask = tegra_gpio_irq_unmask,
630 .irq_set_affinity = tegra_gpio_irq_set_affinity,
631 .irq_set_type = tegra_gpio_irq_set_type,
632#ifdef CONFIG_PM_SLEEP
633 .irq_set_wake = tegra_gpio_irq_set_wake,
634#endif
635 .irq_print_chip = tegra_gpio_irq_print_chip,
636 .irq_request_resources = tegra_gpio_irq_request_resources,
637 .irq_release_resources = tegra_gpio_irq_release_resources,
638 .flags = IRQCHIP_IMMUTABLE,
639};
640
b59d5fb7
SP		 641#ifdef CONFIG_DEBUG_FS
642
643#include <linux/debugfs.h>
b59d5fb7 644
2773eb2f 645static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
b59d5fb7 646{
b2a6115f 647 struct tegra_gpio_info *tgi = dev_get_drvdata(s->private);
539b7a39 648 unsigned int i, j;
b59d5fb7 649
b546be0d 650 for (i = 0; i < tgi->bank_count; i++) {
b59d5fb7 651 for (j = 0; j < 4; j++) {
539b7a39 652 unsigned int gpio = tegra_gpio_compose(i, j, 0);
4bc17860 653
b59d5fb7 654 seq_printf(s,
539b7a39 655 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
b59d5fb7 656 i, j,
b546be0d
LD		 657 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
658 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
659 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
660 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
661 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
662 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
663 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
b59d5fb7
SP		 664 }
665 }
666 return 0;
667}
668
b546be0d 669static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
b59d5fb7 670{
b2a6115f
DO		 671 debugfs_create_devm_seqfile(tgi->dev, "tegra_gpio", NULL,
672 tegra_dbg_gpio_show);
b59d5fb7
SP		 673}
674
675#else
676
b546be0d 677static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
b59d5fb7
SP		 678{
679}
680
681#endif
682
8939ddc7 683static const struct dev_pm_ops tegra_gpio_pm_ops = {
9ccaf106 684 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
8939ddc7
LD		 685};
686
66fecef5
TR		 687static const struct of_device_id tegra_pmc_of_match[] = {
688 { .compatible = "nvidia,tegra210-pmc", },
689 { /* sentinel */ },
690};
6ea68fc0 691
3836309d 692static int tegra_gpio_probe(struct platform_device *pdev)
3c92db9a
EG		 693{
694 struct tegra_gpio_bank *bank;
66fecef5
TR		 695 struct tegra_gpio_info *tgi;
696 struct gpio_irq_chip *irq;
697 struct device_node *np;
698 unsigned int i, j;
f57f98a6 699 int ret;
3c92db9a 700
b546be0d
LD		 701 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
702 if (!tgi)
703 return -ENODEV;
704
20133bd5 705 tgi->soc = of_device_get_match_data(&pdev->dev);
b546be0d 706 tgi->dev = &pdev->dev;
5c1e2c9d 707
56420903
TR		 708 ret = platform_irq_count(pdev);
709 if (ret < 0)
710 return ret;
711
712 tgi->bank_count = ret;
713
b546be0d 714 if (!tgi->bank_count) {
3391811c
SW		 715 dev_err(&pdev->dev, "Missing IRQ resource\n");
716 return -ENODEV;
717 }
718
b546be0d
LD		 719 tgi->gc.label = "tegra-gpio";
720 tgi->gc.request = tegra_gpio_request;
721 tgi->gc.free = tegra_gpio_free;
722 tgi->gc.direction_input = tegra_gpio_direction_input;
723 tgi->gc.get = tegra_gpio_get;
724 tgi->gc.direction_output = tegra_gpio_direction_output;
725 tgi->gc.set = tegra_gpio_set;
f002d07c 726 tgi->gc.get_direction = tegra_gpio_get_direction;
b546be0d
LD		 727 tgi->gc.base = 0;
728 tgi->gc.ngpio = tgi->bank_count * 32;
729 tgi->gc.parent = &pdev->dev;
b546be0d 730
b546be0d 731 platform_set_drvdata(pdev, tgi);
3391811c 732
20133bd5 733 if (tgi->soc->debounce_supported)
2956b5d9 734 tgi->gc.set_config = tegra_gpio_set_config;
3737de42 735
9b882269 736 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
b546be0d
LD		 737 sizeof(*tgi->bank_info), GFP_KERNEL);
738 if (!tgi->bank_info)
9b882269 739 return -ENOMEM;
3391811c 740
718ff946
DO		 741 tgi->irqs = devm_kcalloc(&pdev->dev, tgi->bank_count,
742 sizeof(*tgi->irqs), GFP_KERNEL);
66fecef5
TR		 743 if (!tgi->irqs)
744 return -ENOMEM;
6f74dc9b 745
b546be0d 746 for (i = 0; i < tgi->bank_count; i++) {
9c07409c 747 ret = platform_get_irq(pdev, i);
15bddb7d 748 if (ret < 0)
9c07409c 749 return ret;
88d8951e 750
b546be0d 751 bank = &tgi->bank_info[i];
88d8951e 752 bank->bank = i;
66fecef5
TR		 753
754 tgi->irqs[i] = ret;
755
756 for (j = 0; j < 4; j++) {
757 raw_spin_lock_init(&bank->lvl_lock[j]);
758 spin_lock_init(&bank->dbc_lock[j]);
759 }
760 }
761
762 irq = &tgi->gc.irq;
66fecef5
TR		 763 irq->fwnode = of_node_to_fwnode(pdev->dev.of_node);
764 irq->child_to_parent_hwirq = tegra_gpio_child_to_parent_hwirq;
765 irq->populate_parent_alloc_arg = tegra_gpio_populate_parent_fwspec;
766 irq->handler = handle_simple_irq;
767 irq->default_type = IRQ_TYPE_NONE;
768 irq->parent_handler = tegra_gpio_irq_handler;
769 irq->parent_handler_data = tgi;
770 irq->num_parents = tgi->bank_count;
771 irq->parents = tgi->irqs;
772
773 np = of_find_matching_node(NULL, tegra_pmc_of_match);
774 if (np) {
775 irq->parent_domain = irq_find_host(np);
776 of_node_put(np);
777
778 if (!irq->parent_domain)
779 return -EPROBE_DEFER;
94de03cc 780
7d1aa08a
SR		 781 gpio_irq_chip_set_chip(irq, &tegra210_gpio_irq_chip);
782 } else {
783 gpio_irq_chip_set_chip(irq, &tegra_gpio_irq_chip);
88d8951e
SW		 784 }
785
a0b81f1c 786 tgi->regs = devm_platform_ioremap_resource(pdev, 0);
b546be0d
LD		 787 if (IS_ERR(tgi->regs))
788 return PTR_ERR(tgi->regs);
88d8951e 789
b546be0d 790 for (i = 0; i < tgi->bank_count; i++) {
3c92db9a
EG		 791 for (j = 0; j < 4; j++) {
792 int gpio = tegra_gpio_compose(i, j, 0);
4bc17860 793
b546be0d 794 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
3c92db9a
EG		 795 }
796 }
797
b546be0d 798 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
66fecef5 799 if (ret < 0)
f57f98a6 800 return ret;
3c92db9a 801
b546be0d 802 tegra_gpio_debuginit(tgi);
b59d5fb7 803
3c92db9a
EG		 804 return 0;
805}
806
804f5680 807static const struct tegra_gpio_soc_config tegra20_gpio_config = {
171b92c8
LD		 808 .bank_stride = 0x80,
809 .upper_offset = 0x800,
810};
811
804f5680 812static const struct tegra_gpio_soc_config tegra30_gpio_config = {
171b92c8
LD		 813 .bank_stride = 0x100,
814 .upper_offset = 0x80,
815};
816
3737de42
LD		 817static const struct tegra_gpio_soc_config tegra210_gpio_config = {
818 .debounce_supported = true,
819 .bank_stride = 0x100,
820 .upper_offset = 0x80,
821};
822
171b92c8 823static const struct of_device_id tegra_gpio_of_match[] = {
3737de42 824 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
171b92c8
LD		 825 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
826 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
827 { },
828};
4a6eac2b 829MODULE_DEVICE_TABLE(of, tegra_gpio_of_match);
171b92c8 830
88d8951e 831static struct platform_driver tegra_gpio_driver = {
66f7aaa4
DO		 832 .driver = {
833 .name = "tegra-gpio",
834 .pm = &tegra_gpio_pm_ops,
88d8951e
SW		 835 .of_match_table = tegra_gpio_of_match,
836 },
66f7aaa4 837 .probe = tegra_gpio_probe,
88d8951e 838};
4a6eac2b
DO		 839module_platform_driver(tegra_gpio_driver);
840
841MODULE_DESCRIPTION("NVIDIA Tegra GPIO controller driver");
842MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
843MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
844MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
845MODULE_AUTHOR("Erik Gilling <konkers@google.com>");
846MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)