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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / drivers / gpio / gpio-tegra.c
CommitLineData
3c92db9a
EG		 1/*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
641d0342 20#include <linux/err.h>
3c92db9a
EG		 21#include <linux/init.h>
22#include <linux/irq.h>
2e47b8b3 23#include <linux/interrupt.h>
3c92db9a 24#include <linux/io.h>
21041dab 25#include <linux/gpio/driver.h>
5c1e2c9d 26#include <linux/of_device.h>
88d8951e
SW		 27#include <linux/platform_device.h>
28#include <linux/module.h>
6f74dc9b 29#include <linux/irqdomain.h>
de88cbb7 30#include <linux/irqchip/chained_irq.h>
3e215d0a 31#include <linux/pinctrl/consumer.h>
8939ddc7 32#include <linux/pm.h>
3c92db9a 33
3c92db9a
EG		 34#define GPIO_BANK(x) ((x) >> 5)
35#define GPIO_PORT(x) (((x) >> 3) & 0x3)
36#define GPIO_BIT(x) ((x) & 0x7)
37
b546be0d 38#define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
5c1e2c9d 39 GPIO_PORT(x) * 4)
3c92db9a 40
b546be0d
LD		 41#define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
42#define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
43#define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
44#define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
45#define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
46#define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
47#define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
48#define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
3737de42
LD		 49#define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
50
b546be0d
LD		 51
52#define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
53#define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
54#define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
3737de42 55#define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
b546be0d
LD		 56#define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
57#define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
58#define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
3c92db9a
EG		 59
60#define GPIO_INT_LVL_MASK 0x010101
61#define GPIO_INT_LVL_EDGE_RISING 0x000101
62#define GPIO_INT_LVL_EDGE_FALLING 0x000100
63#define GPIO_INT_LVL_EDGE_BOTH 0x010100
64#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
65#define GPIO_INT_LVL_LEVEL_LOW 0x000000
66
b546be0d
LD		 67struct tegra_gpio_info;
68
3c92db9a 69struct tegra_gpio_bank {
539b7a39
TR		 70 unsigned int bank;
71 unsigned int irq;
3c92db9a 72 spinlock_t lvl_lock[4];
3737de42 73 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
8939ddc7 74#ifdef CONFIG_PM_SLEEP
2e47b8b3
CC		 75 u32 cnf[4];
76 u32 out[4];
77 u32 oe[4];
78 u32 int_enb[4];
79 u32 int_lvl[4];
203f31cb 80 u32 wake_enb[4];
3737de42 81 u32 dbc_enb[4];
2e47b8b3 82#endif
3737de42 83 u32 dbc_cnt[4];
b546be0d 84 struct tegra_gpio_info *tgi;
3c92db9a
EG		 85};
86
171b92c8 87struct tegra_gpio_soc_config {
3737de42 88 bool debounce_supported;
171b92c8
LD		 89 u32 bank_stride;
90 u32 upper_offset;
91};
92
b546be0d
LD		 93struct tegra_gpio_info {
94 struct device *dev;
95 void __iomem *regs;
96 struct irq_domain *irq_domain;
97 struct tegra_gpio_bank *bank_info;
98 const struct tegra_gpio_soc_config *soc;
99 struct gpio_chip gc;
100 struct irq_chip ic;
b546be0d
LD		 101 u32 bank_count;
102};
88d8951e 103
b546be0d
LD		 104static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
105 u32 val, u32 reg)
88d8951e 106{
b546be0d 107 __raw_writel(val, tgi->regs + reg);
88d8951e
SW		 108}
109
b546be0d 110static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
88d8951e 111{
b546be0d 112 return __raw_readl(tgi->regs + reg);
88d8951e 113}
3c92db9a 114
539b7a39
TR		 115static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
116 unsigned int bit)
3c92db9a
EG		 117{
118 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
119}
120
b546be0d 121static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
539b7a39 122 unsigned int gpio, u32 value)
3c92db9a
EG		 123{
124 u32 val;
125
126 val = 0x100 << GPIO_BIT(gpio);
127 if (value)
128 val |= 1 << GPIO_BIT(gpio);
b546be0d 129 tegra_gpio_writel(tgi, val, reg);
3c92db9a
EG		 130}
131
539b7a39 132static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
3c92db9a 133{
b546be0d 134 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
3c92db9a
EG		 135}
136
539b7a39 137static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
3c92db9a 138{
b546be0d 139 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
3c92db9a
EG		 140}
141
4bc17860 142static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
3e215d0a 143{
a9a1d2a7 144 return pinctrl_gpio_request(offset);
3e215d0a
SW		 145}
146
4bc17860 147static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
3e215d0a 148{
b546be0d
LD		 149 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
150
a9a1d2a7 151 pinctrl_gpio_free(offset);
b546be0d 152 tegra_gpio_disable(tgi, offset);
3e215d0a
SW		 153}
154
4bc17860
TR		 155static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
156 int value)
3c92db9a 157{
b546be0d
LD		 158 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
159
160 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
3c92db9a
EG		 161}
162
4bc17860 163static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
3c92db9a 164{
b546be0d 165 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
539b7a39 166 unsigned int bval = BIT(GPIO_BIT(offset));
b546be0d 167
195812e4 168 /* If gpio is in output mode then read from the out value */
b546be0d
LD		 169 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
170 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
195812e4 171
b546be0d 172 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
3c92db9a
EG		 173}
174
4bc17860
TR		 175static int tegra_gpio_direction_input(struct gpio_chip *chip,
176 unsigned int offset)
3c92db9a 177{
b546be0d
LD		 178 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
179
180 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
181 tegra_gpio_enable(tgi, offset);
3c92db9a
EG		 182 return 0;
183}
184
4bc17860
TR		 185static int tegra_gpio_direction_output(struct gpio_chip *chip,
186 unsigned int offset,
187 int value)
3c92db9a 188{
b546be0d
LD		 189 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
190
3c92db9a 191 tegra_gpio_set(chip, offset, value);
b546be0d
LD		 192 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
193 tegra_gpio_enable(tgi, offset);
3c92db9a
EG		 194 return 0;
195}
196
4bc17860
TR		 197static int tegra_gpio_get_direction(struct gpio_chip *chip,
198 unsigned int offset)
f002d07c
LD		 199{
200 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
201 u32 pin_mask = BIT(GPIO_BIT(offset));
202 u32 cnf, oe;
203
204 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
205 if (!(cnf & pin_mask))
206 return -EINVAL;
207
208 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
209
21041dab 210 return !(oe & pin_mask);
f002d07c
LD		 211}
212
3737de42
LD		 213static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
214 unsigned int debounce)
215{
216 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
217 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
218 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
219 unsigned long flags;
539b7a39 220 unsigned int port;
3737de42
LD		 221
222 if (!debounce_ms) {
223 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
224 offset, 0);
225 return 0;
226 }
227
228 debounce_ms = min(debounce_ms, 255U);
229 port = GPIO_PORT(offset);
230
231 /* There is only one debounce count register per port and hence
232 * set the maximum of current and requested debounce time.
233 */
234 spin_lock_irqsave(&bank->dbc_lock[port], flags);
235 if (bank->dbc_cnt[port] < debounce_ms) {
236 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
237 bank->dbc_cnt[port] = debounce_ms;
238 }
239 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
240
241 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
242
243 return 0;
244}
245
2956b5d9
MW		 246static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
247 unsigned long config)
248{
249 u32 debounce;
250
251 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
252 return -ENOTSUPP;
253
254 debounce = pinconf_to_config_argument(config);
255 return tegra_gpio_set_debounce(chip, offset, debounce);
256}
257
4bc17860 258static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
438a99c0 259{
b546be0d 260 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
3c92db9a 261
b546be0d
LD		 262 return irq_find_mapping(tgi->irq_domain, offset);
263}
3c92db9a 264
37337a8d 265static void tegra_gpio_irq_ack(struct irq_data *d)
3c92db9a 266{
b546be0d
LD		 267 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
268 struct tegra_gpio_info *tgi = bank->tgi;
539b7a39 269 unsigned int gpio = d->hwirq;
3c92db9a 270
b546be0d 271 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
3c92db9a
EG		 272}
273
37337a8d 274static void tegra_gpio_irq_mask(struct irq_data *d)
3c92db9a 275{
b546be0d
LD		 276 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
277 struct tegra_gpio_info *tgi = bank->tgi;
539b7a39 278 unsigned int gpio = d->hwirq;
3c92db9a 279
b546be0d 280 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
3c92db9a
EG		 281}
282
37337a8d 283static void tegra_gpio_irq_unmask(struct irq_data *d)
3c92db9a 284{
b546be0d
LD		 285 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
286 struct tegra_gpio_info *tgi = bank->tgi;
539b7a39 287 unsigned int gpio = d->hwirq;
3c92db9a 288
b546be0d 289 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
3c92db9a
EG		 290}
291
37337a8d 292static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
3c92db9a 293{
539b7a39 294 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
37337a8d 295 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
b546be0d 296 struct tegra_gpio_info *tgi = bank->tgi;
3c92db9a 297 unsigned long flags;
539b7a39 298 u32 val;
df231f28 299 int ret;
3c92db9a
EG		 300
301 switch (type & IRQ_TYPE_SENSE_MASK) {
302 case IRQ_TYPE_EDGE_RISING:
303 lvl_type = GPIO_INT_LVL_EDGE_RISING;
304 break;
305
306 case IRQ_TYPE_EDGE_FALLING:
307 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
308 break;
309
310 case IRQ_TYPE_EDGE_BOTH:
311 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
312 break;
313
314 case IRQ_TYPE_LEVEL_HIGH:
315 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
316 break;
317
318 case IRQ_TYPE_LEVEL_LOW:
319 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
320 break;
321
322 default:
323 return -EINVAL;
324 }
325
326 spin_lock_irqsave(&bank->lvl_lock[port], flags);
327
b546be0d 328 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
3c92db9a
EG		 329 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
330 val |= lvl_type << GPIO_BIT(gpio);
b546be0d 331 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
3c92db9a
EG		 332
333 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
334
b546be0d
LD		 335 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
336 tegra_gpio_enable(tgi, gpio);
d941136f 337
f78709a5
DO		 338 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
339 if (ret) {
340 dev_err(tgi->dev,
341 "unable to lock Tegra GPIO %u as IRQ\n", gpio);
342 tegra_gpio_disable(tgi, gpio);
343 return ret;
344 }
345
3c92db9a 346 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
f170d71e 347 irq_set_handler_locked(d, handle_level_irq);
3c92db9a 348 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
f170d71e 349 irq_set_handler_locked(d, handle_edge_irq);
3c92db9a
EG		 350
351 return 0;
352}
353
df231f28
SW		 354static void tegra_gpio_irq_shutdown(struct irq_data *d)
355{
b546be0d
LD		 356 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
357 struct tegra_gpio_info *tgi = bank->tgi;
539b7a39 358 unsigned int gpio = d->hwirq;
df231f28 359
b546be0d 360 gpiochip_unlock_as_irq(&tgi->gc, gpio);
df231f28
SW		 361}
362
bd0b9ac4 363static void tegra_gpio_irq_handler(struct irq_desc *desc)
3c92db9a 364{
539b7a39 365 unsigned int port, pin, gpio;
9e9509e3 366 bool unmasked = false;
b546be0d
LD		 367 u32 lvl;
368 unsigned long sta;
98022940 369 struct irq_chip *chip = irq_desc_get_chip(desc);
476f8b4c 370 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
b546be0d 371 struct tegra_gpio_info *tgi = bank->tgi;
3c92db9a 372
98022940 373 chained_irq_enter(chip, desc);
3c92db9a 374
3c92db9a 375 for (port = 0; port < 4; port++) {
b546be0d
LD		 376 gpio = tegra_gpio_compose(bank->bank, port, 0);
377 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
378 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
379 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
3c92db9a
EG		 380
381 for_each_set_bit(pin, &sta, 8) {
b546be0d
LD		 382 tegra_gpio_writel(tgi, 1 << pin,
383 GPIO_INT_CLR(tgi, gpio));
3c92db9a
EG		 384
385 /* if gpio is edge triggered, clear condition
20a8a968 386 * before executing the handler so that we don't
3c92db9a
EG		 387 * miss edges
388 */
9e9509e3
MM		 389 if (!unmasked && lvl & (0x100 << pin)) {
390 unmasked = true;
98022940 391 chained_irq_exit(chip, desc);
3c92db9a
EG		 392 }
393
c0debb3d
GS		 394 generic_handle_irq(irq_find_mapping(tgi->irq_domain,
395 gpio + pin));
3c92db9a
EG		 396 }
397 }
398
399 if (!unmasked)
98022940 400 chained_irq_exit(chip, desc);
3c92db9a
EG		 401
402}
403
8939ddc7
LD		 404#ifdef CONFIG_PM_SLEEP
405static int tegra_gpio_resume(struct device *dev)
2e47b8b3 406{
7ddb7dce 407 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
2e47b8b3 408 unsigned long flags;
539b7a39 409 unsigned int b, p;
2e47b8b3
CC		 410
411 local_irq_save(flags);
412
b546be0d
LD		 413 for (b = 0; b < tgi->bank_count; b++) {
414 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
2e47b8b3
CC		 415
416 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
4bc17860
TR		 417 unsigned int gpio = (b << 5) | (p << 3);
418
b546be0d
LD		 419 tegra_gpio_writel(tgi, bank->cnf[p],
420 GPIO_CNF(tgi, gpio));
3737de42
LD		 421
422 if (tgi->soc->debounce_supported) {
423 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
424 GPIO_DBC_CNT(tgi, gpio));
425 tegra_gpio_writel(tgi, bank->dbc_enb[p],
426 GPIO_MSK_DBC_EN(tgi, gpio));
427 }
428
b546be0d
LD		 429 tegra_gpio_writel(tgi, bank->out[p],
430 GPIO_OUT(tgi, gpio));
431 tegra_gpio_writel(tgi, bank->oe[p],
432 GPIO_OE(tgi, gpio));
433 tegra_gpio_writel(tgi, bank->int_lvl[p],
434 GPIO_INT_LVL(tgi, gpio));
435 tegra_gpio_writel(tgi, bank->int_enb[p],
436 GPIO_INT_ENB(tgi, gpio));
2e47b8b3
CC		 437 }
438 }
439
440 local_irq_restore(flags);
8939ddc7 441 return 0;
2e47b8b3
CC		 442}
443
8939ddc7 444static int tegra_gpio_suspend(struct device *dev)
2e47b8b3 445{
7ddb7dce 446 struct tegra_gpio_info *tgi = dev_get_drvdata(dev);
2e47b8b3 447 unsigned long flags;
539b7a39 448 unsigned int b, p;
2e47b8b3 449
2e47b8b3 450 local_irq_save(flags);
b546be0d
LD		 451 for (b = 0; b < tgi->bank_count; b++) {
452 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
2e47b8b3
CC		 453
454 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
4bc17860
TR		 455 unsigned int gpio = (b << 5) | (p << 3);
456
b546be0d
LD		 457 bank->cnf[p] = tegra_gpio_readl(tgi,
458 GPIO_CNF(tgi, gpio));
459 bank->out[p] = tegra_gpio_readl(tgi,
460 GPIO_OUT(tgi, gpio));
461 bank->oe[p] = tegra_gpio_readl(tgi,
462 GPIO_OE(tgi, gpio));
3737de42
LD		 463 if (tgi->soc->debounce_supported) {
464 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
465 GPIO_MSK_DBC_EN(tgi, gpio));
466 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
467 bank->dbc_enb[p];
468 }
469
b546be0d
LD		 470 bank->int_enb[p] = tegra_gpio_readl(tgi,
471 GPIO_INT_ENB(tgi, gpio));
472 bank->int_lvl[p] = tegra_gpio_readl(tgi,
473 GPIO_INT_LVL(tgi, gpio));
203f31cb
JL		 474
475 /* Enable gpio irq for wake up source */
b546be0d
LD		 476 tegra_gpio_writel(tgi, bank->wake_enb[p],
477 GPIO_INT_ENB(tgi, gpio));
2e47b8b3
CC		 478 }
479 }
480 local_irq_restore(flags);
8939ddc7 481 return 0;
2e47b8b3
CC		 482}
483
203f31cb 484static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
2e47b8b3 485{
37337a8d 486 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
539b7a39 487 unsigned int gpio = d->hwirq;
203f31cb
JL		 488 u32 port, bit, mask;
489
490 port = GPIO_PORT(gpio);
491 bit = GPIO_BIT(gpio);
492 mask = BIT(bit);
493
494 if (enable)
495 bank->wake_enb[port] |= mask;
496 else
497 bank->wake_enb[port] &= ~mask;
498
6845664a 499 return irq_set_irq_wake(bank->irq, enable);
2e47b8b3
CC		 500}
501#endif
3c92db9a 502
b59d5fb7
SP		 503#ifdef CONFIG_DEBUG_FS
504
505#include <linux/debugfs.h>
506#include <linux/seq_file.h>
507
2773eb2f 508static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
b59d5fb7 509{
b546be0d 510 struct tegra_gpio_info *tgi = s->private;
539b7a39 511 unsigned int i, j;
b59d5fb7 512
b546be0d 513 for (i = 0; i < tgi->bank_count; i++) {
b59d5fb7 514 for (j = 0; j < 4; j++) {
539b7a39 515 unsigned int gpio = tegra_gpio_compose(i, j, 0);
4bc17860 516
b59d5fb7 517 seq_printf(s,
539b7a39 518 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
b59d5fb7 519 i, j,
b546be0d
LD		 520 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
521 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
522 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
523 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
524 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
525 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
526 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
b59d5fb7
SP		 527 }
528 }
529 return 0;
530}
531
2773eb2f 532DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio);
b59d5fb7 533
b546be0d 534static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
b59d5fb7 535{
4bc17860 536 (void) debugfs_create_file("tegra_gpio", 0444,
2773eb2f 537 NULL, tgi, &tegra_dbg_gpio_fops);
b59d5fb7
SP		 538}
539
540#else
541
b546be0d 542static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
b59d5fb7
SP		 543{
544}
545
546#endif
547
8939ddc7
LD		 548static const struct dev_pm_ops tegra_gpio_pm_ops = {
549 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
550};
551
3836309d 552static int tegra_gpio_probe(struct platform_device *pdev)
3c92db9a 553{
b546be0d 554 struct tegra_gpio_info *tgi;
88d8951e 555 struct resource *res;
3c92db9a 556 struct tegra_gpio_bank *bank;
539b7a39 557 unsigned int gpio, i, j;
f57f98a6 558 int ret;
3c92db9a 559
b546be0d
LD		 560 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
561 if (!tgi)
562 return -ENODEV;
563
20133bd5 564 tgi->soc = of_device_get_match_data(&pdev->dev);
b546be0d 565 tgi->dev = &pdev->dev;
5c1e2c9d 566
56420903
TR		 567 ret = platform_irq_count(pdev);
568 if (ret < 0)
569 return ret;
570
571 tgi->bank_count = ret;
572
b546be0d 573 if (!tgi->bank_count) {
3391811c
SW		 574 dev_err(&pdev->dev, "Missing IRQ resource\n");
575 return -ENODEV;
576 }
577
b546be0d
LD		 578 tgi->gc.label = "tegra-gpio";
579 tgi->gc.request = tegra_gpio_request;
580 tgi->gc.free = tegra_gpio_free;
581 tgi->gc.direction_input = tegra_gpio_direction_input;
582 tgi->gc.get = tegra_gpio_get;
583 tgi->gc.direction_output = tegra_gpio_direction_output;
584 tgi->gc.set = tegra_gpio_set;
f002d07c 585 tgi->gc.get_direction = tegra_gpio_get_direction;
b546be0d
LD		 586 tgi->gc.to_irq = tegra_gpio_to_irq;
587 tgi->gc.base = 0;
588 tgi->gc.ngpio = tgi->bank_count * 32;
589 tgi->gc.parent = &pdev->dev;
590 tgi->gc.of_node = pdev->dev.of_node;
591
592 tgi->ic.name = "GPIO";
593 tgi->ic.irq_ack = tegra_gpio_irq_ack;
594 tgi->ic.irq_mask = tegra_gpio_irq_mask;
595 tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
596 tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
597 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
598#ifdef CONFIG_PM_SLEEP
599 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
600#endif
601
602 platform_set_drvdata(pdev, tgi);
3391811c 603
20133bd5 604 if (tgi->soc->debounce_supported)
2956b5d9 605 tgi->gc.set_config = tegra_gpio_set_config;
3737de42 606
9b882269 607 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
b546be0d
LD		 608 sizeof(*tgi->bank_info), GFP_KERNEL);
609 if (!tgi->bank_info)
9b882269 610 return -ENOMEM;
3391811c 611
b546be0d
LD		 612 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
613 tgi->gc.ngpio,
614 &irq_domain_simple_ops, NULL);
615 if (!tgi->irq_domain)
d0235677 616 return -ENODEV;
6f74dc9b 617
b546be0d 618 for (i = 0; i < tgi->bank_count; i++) {
9c07409c
TR		 619 ret = platform_get_irq(pdev, i);
620 if (ret < 0) {
621 dev_err(&pdev->dev, "Missing IRQ resource: %d\n", ret);
622 return ret;
88d8951e
SW		 623 }
624
b546be0d 625 bank = &tgi->bank_info[i];
88d8951e 626 bank->bank = i;
9c07409c 627 bank->irq = ret;
b546be0d 628 bank->tgi = tgi;
88d8951e
SW		 629 }
630
631 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b546be0d
LD		 632 tgi->regs = devm_ioremap_resource(&pdev->dev, res);
633 if (IS_ERR(tgi->regs))
634 return PTR_ERR(tgi->regs);
88d8951e 635
b546be0d 636 for (i = 0; i < tgi->bank_count; i++) {
3c92db9a
EG		 637 for (j = 0; j < 4; j++) {
638 int gpio = tegra_gpio_compose(i, j, 0);
4bc17860 639
b546be0d 640 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
3c92db9a
EG		 641 }
642 }
643
b546be0d 644 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
f57f98a6 645 if (ret < 0) {
b546be0d 646 irq_domain_remove(tgi->irq_domain);
f57f98a6
SW		 647 return ret;
648 }
3c92db9a 649
b546be0d
LD		 650 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
651 int irq = irq_create_mapping(tgi->irq_domain, gpio);
47008001 652 /* No validity check; all Tegra GPIOs are valid IRQs */
3c92db9a 653
b546be0d 654 bank = &tgi->bank_info[GPIO_BANK(gpio)];
3c92db9a 655
47008001 656 irq_set_chip_data(irq, bank);
b546be0d 657 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
3c92db9a
EG		 658 }
659
b546be0d
LD		 660 for (i = 0; i < tgi->bank_count; i++) {
661 bank = &tgi->bank_info[i];
3c92db9a 662
e88d251d
RK		 663 irq_set_chained_handler_and_data(bank->irq,
664 tegra_gpio_irq_handler, bank);
3c92db9a 665
3737de42 666 for (j = 0; j < 4; j++) {
3c92db9a 667 spin_lock_init(&bank->lvl_lock[j]);
3737de42
LD		 668 spin_lock_init(&bank->dbc_lock[j]);
669 }
3c92db9a
EG		 670 }
671
b546be0d 672 tegra_gpio_debuginit(tgi);
b59d5fb7 673
3c92db9a
EG		 674 return 0;
675}
676
804f5680 677static const struct tegra_gpio_soc_config tegra20_gpio_config = {
171b92c8
LD		 678 .bank_stride = 0x80,
679 .upper_offset = 0x800,
680};
681
804f5680 682static const struct tegra_gpio_soc_config tegra30_gpio_config = {
171b92c8
LD		 683 .bank_stride = 0x100,
684 .upper_offset = 0x80,
685};
686
3737de42
LD		 687static const struct tegra_gpio_soc_config tegra210_gpio_config = {
688 .debounce_supported = true,
689 .bank_stride = 0x100,
690 .upper_offset = 0x80,
691};
692
171b92c8 693static const struct of_device_id tegra_gpio_of_match[] = {
3737de42 694 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
171b92c8
LD		 695 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
696 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
697 { },
698};
699
88d8951e
SW		 700static struct platform_driver tegra_gpio_driver = {
701 .driver = {
702 .name = "tegra-gpio",
8939ddc7 703 .pm = &tegra_gpio_pm_ops,
88d8951e
SW		 704 .of_match_table = tegra_gpio_of_match,
705 },
706 .probe = tegra_gpio_probe,
707};
708
709static int __init tegra_gpio_init(void)
710{
711 return platform_driver_register(&tegra_gpio_driver);
712}
40b25bce 713subsys_initcall(tegra_gpio_init);
Linux 6.x block layer and io_uring tree(s)