Commit | Line | Data |
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1f67b599 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
d88b25be RV |
2 | /* |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
4 | * | |
d88b25be RV |
5 | * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson |
6 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | |
7 | */ | |
8 | ||
d88b25be RV |
9 | #include <linux/init.h> |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/slab.h> | |
cee1b40d | 12 | #include <linux/gpio/driver.h> |
3113e679 | 13 | #include <linux/of.h> |
d88b25be | 14 | #include <linux/interrupt.h> |
c6eda6c5 | 15 | #include <linux/mfd/tc3589x.h> |
cee1b40d | 16 | #include <linux/bitops.h> |
d88b25be RV |
17 | |
18 | /* | |
19 | * These registers are modified under the irq bus lock and cached to avoid | |
20 | * unnecessary writes in bus_sync_unlock. | |
21 | */ | |
22 | enum { REG_IBE, REG_IEV, REG_IS, REG_IE }; | |
23 | ||
24 | #define CACHE_NR_REGS 4 | |
25 | #define CACHE_NR_BANKS 3 | |
26 | ||
20406ebf | 27 | struct tc3589x_gpio { |
d88b25be | 28 | struct gpio_chip chip; |
20406ebf | 29 | struct tc3589x *tc3589x; |
d88b25be RV |
30 | struct device *dev; |
31 | struct mutex irq_lock; | |
d88b25be RV |
32 | /* Caches of interrupt control registers for bus_lock */ |
33 | u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
34 | u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
35 | }; | |
36 | ||
0e4011eb | 37 | static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned int offset) |
d88b25be | 38 | { |
b0d38473 | 39 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); |
20406ebf SI |
40 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
41 | u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2; | |
cee1b40d | 42 | u8 mask = BIT(offset % 8); |
d88b25be RV |
43 | int ret; |
44 | ||
20406ebf | 45 | ret = tc3589x_reg_read(tc3589x, reg); |
d88b25be RV |
46 | if (ret < 0) |
47 | return ret; | |
48 | ||
27ca2267 | 49 | return !!(ret & mask); |
d88b25be RV |
50 | } |
51 | ||
0e4011eb | 52 | static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val) |
d88b25be | 53 | { |
b0d38473 | 54 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); |
20406ebf SI |
55 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
56 | u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2; | |
0e4011eb | 57 | unsigned int pos = offset % 8; |
cee1b40d | 58 | u8 data[] = {val ? BIT(pos) : 0, BIT(pos)}; |
d88b25be | 59 | |
20406ebf | 60 | tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data); |
d88b25be RV |
61 | } |
62 | ||
20406ebf | 63 | static int tc3589x_gpio_direction_output(struct gpio_chip *chip, |
0e4011eb | 64 | unsigned int offset, int val) |
d88b25be | 65 | { |
b0d38473 | 66 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); |
20406ebf SI |
67 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
68 | u8 reg = TC3589x_GPIODIR0 + offset / 8; | |
0e4011eb | 69 | unsigned int pos = offset % 8; |
d88b25be | 70 | |
20406ebf | 71 | tc3589x_gpio_set(chip, offset, val); |
d88b25be | 72 | |
cee1b40d | 73 | return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos)); |
d88b25be RV |
74 | } |
75 | ||
20406ebf | 76 | static int tc3589x_gpio_direction_input(struct gpio_chip *chip, |
0e4011eb | 77 | unsigned int offset) |
d88b25be | 78 | { |
b0d38473 | 79 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); |
20406ebf SI |
80 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
81 | u8 reg = TC3589x_GPIODIR0 + offset / 8; | |
0e4011eb | 82 | unsigned int pos = offset % 8; |
d88b25be | 83 | |
cee1b40d | 84 | return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0); |
d88b25be RV |
85 | } |
86 | ||
14063d71 | 87 | static int tc3589x_gpio_get_direction(struct gpio_chip *chip, |
0e4011eb | 88 | unsigned int offset) |
14063d71 LW |
89 | { |
90 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); | |
91 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; | |
92 | u8 reg = TC3589x_GPIODIR0 + offset / 8; | |
0e4011eb | 93 | unsigned int pos = offset % 8; |
14063d71 LW |
94 | int ret; |
95 | ||
96 | ret = tc3589x_reg_read(tc3589x, reg); | |
97 | if (ret < 0) | |
98 | return ret; | |
99 | ||
e42615ec MV |
100 | if (ret & BIT(pos)) |
101 | return GPIO_LINE_DIRECTION_OUT; | |
102 | ||
103 | return GPIO_LINE_DIRECTION_IN; | |
14063d71 LW |
104 | } |
105 | ||
2956b5d9 MW |
106 | static int tc3589x_gpio_set_config(struct gpio_chip *chip, unsigned int offset, |
107 | unsigned long config) | |
8b866b06 LW |
108 | { |
109 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip); | |
110 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; | |
111 | /* | |
112 | * These registers are alterated at each second address | |
113 | * ODM bit 0 = drive to GND or Hi-Z (open drain) | |
114 | * ODM bit 1 = drive to VDD or Hi-Z (open source) | |
115 | */ | |
116 | u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2; | |
117 | u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2; | |
0e4011eb | 118 | unsigned int pos = offset % 8; |
8b866b06 LW |
119 | int ret; |
120 | ||
2956b5d9 MW |
121 | switch (pinconf_to_config_param(config)) { |
122 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
8b866b06 LW |
123 | /* Set open drain mode */ |
124 | ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0); | |
125 | if (ret) | |
126 | return ret; | |
127 | /* Enable open drain/source mode */ | |
128 | return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos)); | |
2956b5d9 | 129 | case PIN_CONFIG_DRIVE_OPEN_SOURCE: |
8b866b06 LW |
130 | /* Set open source mode */ |
131 | ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos)); | |
132 | if (ret) | |
133 | return ret; | |
134 | /* Enable open drain/source mode */ | |
135 | return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos)); | |
2956b5d9 | 136 | case PIN_CONFIG_DRIVE_PUSH_PULL: |
8b866b06 LW |
137 | /* Disable open drain/source mode */ |
138 | return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0); | |
139 | default: | |
140 | break; | |
141 | } | |
142 | return -ENOTSUPP; | |
143 | } | |
144 | ||
e35b5ab0 | 145 | static const struct gpio_chip template_chip = { |
20406ebf | 146 | .label = "tc3589x", |
d88b25be | 147 | .owner = THIS_MODULE, |
20406ebf | 148 | .get = tc3589x_gpio_get, |
20406ebf | 149 | .set = tc3589x_gpio_set, |
14063d71 LW |
150 | .direction_output = tc3589x_gpio_direction_output, |
151 | .direction_input = tc3589x_gpio_direction_input, | |
152 | .get_direction = tc3589x_gpio_get_direction, | |
2956b5d9 | 153 | .set_config = tc3589x_gpio_set_config, |
9fb1f39e | 154 | .can_sleep = true, |
d88b25be RV |
155 | }; |
156 | ||
33fcc1b8 | 157 | static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
d88b25be | 158 | { |
cf42f1cf | 159 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 160 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
efe4c949 | 161 | int offset = d->hwirq; |
d88b25be | 162 | int regoffset = offset / 8; |
cee1b40d | 163 | int mask = BIT(offset % 8); |
d88b25be RV |
164 | |
165 | if (type == IRQ_TYPE_EDGE_BOTH) { | |
20406ebf | 166 | tc3589x_gpio->regs[REG_IBE][regoffset] |= mask; |
d88b25be RV |
167 | return 0; |
168 | } | |
169 | ||
20406ebf | 170 | tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask; |
d88b25be RV |
171 | |
172 | if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) | |
20406ebf | 173 | tc3589x_gpio->regs[REG_IS][regoffset] |= mask; |
d88b25be | 174 | else |
20406ebf | 175 | tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask; |
d88b25be RV |
176 | |
177 | if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) | |
20406ebf | 178 | tc3589x_gpio->regs[REG_IEV][regoffset] |= mask; |
d88b25be | 179 | else |
20406ebf | 180 | tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask; |
d88b25be RV |
181 | |
182 | return 0; | |
183 | } | |
184 | ||
33fcc1b8 | 185 | static void tc3589x_gpio_irq_lock(struct irq_data *d) |
d88b25be | 186 | { |
cf42f1cf | 187 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 188 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
d88b25be | 189 | |
20406ebf | 190 | mutex_lock(&tc3589x_gpio->irq_lock); |
d88b25be RV |
191 | } |
192 | ||
33fcc1b8 | 193 | static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d) |
d88b25be | 194 | { |
cf42f1cf | 195 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 196 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
20406ebf | 197 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
d88b25be | 198 | static const u8 regmap[] = { |
20406ebf SI |
199 | [REG_IBE] = TC3589x_GPIOIBE0, |
200 | [REG_IEV] = TC3589x_GPIOIEV0, | |
201 | [REG_IS] = TC3589x_GPIOIS0, | |
202 | [REG_IE] = TC3589x_GPIOIE0, | |
d88b25be RV |
203 | }; |
204 | int i, j; | |
205 | ||
206 | for (i = 0; i < CACHE_NR_REGS; i++) { | |
207 | for (j = 0; j < CACHE_NR_BANKS; j++) { | |
20406ebf SI |
208 | u8 old = tc3589x_gpio->oldregs[i][j]; |
209 | u8 new = tc3589x_gpio->regs[i][j]; | |
d88b25be RV |
210 | |
211 | if (new == old) | |
212 | continue; | |
213 | ||
20406ebf SI |
214 | tc3589x_gpio->oldregs[i][j] = new; |
215 | tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new); | |
d88b25be RV |
216 | } |
217 | } | |
218 | ||
20406ebf | 219 | mutex_unlock(&tc3589x_gpio->irq_lock); |
d88b25be RV |
220 | } |
221 | ||
33fcc1b8 | 222 | static void tc3589x_gpio_irq_mask(struct irq_data *d) |
d88b25be | 223 | { |
cf42f1cf | 224 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 225 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
efe4c949 | 226 | int offset = d->hwirq; |
d88b25be | 227 | int regoffset = offset / 8; |
cee1b40d | 228 | int mask = BIT(offset % 8); |
d88b25be | 229 | |
20406ebf | 230 | tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask; |
d88b25be RV |
231 | } |
232 | ||
33fcc1b8 | 233 | static void tc3589x_gpio_irq_unmask(struct irq_data *d) |
d88b25be | 234 | { |
cf42f1cf | 235 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
b0d38473 | 236 | struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc); |
efe4c949 | 237 | int offset = d->hwirq; |
d88b25be | 238 | int regoffset = offset / 8; |
cee1b40d | 239 | int mask = BIT(offset % 8); |
d88b25be | 240 | |
20406ebf | 241 | tc3589x_gpio->regs[REG_IE][regoffset] |= mask; |
d88b25be RV |
242 | } |
243 | ||
20406ebf SI |
244 | static struct irq_chip tc3589x_gpio_irq_chip = { |
245 | .name = "tc3589x-gpio", | |
33fcc1b8 LB |
246 | .irq_bus_lock = tc3589x_gpio_irq_lock, |
247 | .irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock, | |
248 | .irq_mask = tc3589x_gpio_irq_mask, | |
249 | .irq_unmask = tc3589x_gpio_irq_unmask, | |
250 | .irq_set_type = tc3589x_gpio_irq_set_type, | |
d88b25be RV |
251 | }; |
252 | ||
20406ebf | 253 | static irqreturn_t tc3589x_gpio_irq(int irq, void *dev) |
d88b25be | 254 | { |
20406ebf SI |
255 | struct tc3589x_gpio *tc3589x_gpio = dev; |
256 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; | |
d88b25be RV |
257 | u8 status[CACHE_NR_BANKS]; |
258 | int ret; | |
259 | int i; | |
260 | ||
20406ebf | 261 | ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0, |
d88b25be RV |
262 | ARRAY_SIZE(status), status); |
263 | if (ret < 0) | |
264 | return IRQ_NONE; | |
265 | ||
266 | for (i = 0; i < ARRAY_SIZE(status); i++) { | |
267 | unsigned int stat = status[i]; | |
268 | if (!stat) | |
269 | continue; | |
270 | ||
271 | while (stat) { | |
272 | int bit = __ffs(stat); | |
273 | int line = i * 8 + bit; | |
f0fbe7bc | 274 | int irq = irq_find_mapping(tc3589x_gpio->chip.irq.domain, |
cf42f1cf | 275 | line); |
d88b25be | 276 | |
e300376d | 277 | handle_nested_irq(irq); |
d88b25be RV |
278 | stat &= ~(1 << bit); |
279 | } | |
280 | ||
20406ebf | 281 | tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]); |
d88b25be RV |
282 | } |
283 | ||
284 | return IRQ_HANDLED; | |
285 | } | |
286 | ||
3836309d | 287 | static int tc3589x_gpio_probe(struct platform_device *pdev) |
d88b25be | 288 | { |
20406ebf | 289 | struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent); |
3113e679 | 290 | struct device_node *np = pdev->dev.of_node; |
20406ebf | 291 | struct tc3589x_gpio *tc3589x_gpio; |
d88b25be RV |
292 | int ret; |
293 | int irq; | |
294 | ||
53e41f55 LW |
295 | if (!np) { |
296 | dev_err(&pdev->dev, "No Device Tree node found\n"); | |
3113e679 LJ |
297 | return -EINVAL; |
298 | } | |
d88b25be RV |
299 | |
300 | irq = platform_get_irq(pdev, 0); | |
301 | if (irq < 0) | |
302 | return irq; | |
303 | ||
033f2752 LW |
304 | tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio), |
305 | GFP_KERNEL); | |
20406ebf | 306 | if (!tc3589x_gpio) |
d88b25be RV |
307 | return -ENOMEM; |
308 | ||
20406ebf | 309 | mutex_init(&tc3589x_gpio->irq_lock); |
d88b25be | 310 | |
20406ebf SI |
311 | tc3589x_gpio->dev = &pdev->dev; |
312 | tc3589x_gpio->tc3589x = tc3589x; | |
d88b25be | 313 | |
20406ebf SI |
314 | tc3589x_gpio->chip = template_chip; |
315 | tc3589x_gpio->chip.ngpio = tc3589x->num_gpio; | |
58383c78 | 316 | tc3589x_gpio->chip.parent = &pdev->dev; |
90f2d0f7 | 317 | tc3589x_gpio->chip.base = -1; |
e90c636b | 318 | tc3589x_gpio->chip.of_node = np; |
d88b25be RV |
319 | |
320 | /* Bring the GPIO module out of reset */ | |
20406ebf SI |
321 | ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL, |
322 | TC3589x_RSTCTRL_GPIRST, 0); | |
d88b25be | 323 | if (ret < 0) |
033f2752 | 324 | return ret; |
d88b25be | 325 | |
033f2752 LW |
326 | ret = devm_request_threaded_irq(&pdev->dev, |
327 | irq, NULL, tc3589x_gpio_irq, | |
328 | IRQF_ONESHOT, "tc3589x-gpio", | |
329 | tc3589x_gpio); | |
d88b25be RV |
330 | if (ret) { |
331 | dev_err(&pdev->dev, "unable to get irq: %d\n", ret); | |
033f2752 | 332 | return ret; |
d88b25be RV |
333 | } |
334 | ||
f3378b6a LD |
335 | ret = devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip, |
336 | tc3589x_gpio); | |
d88b25be RV |
337 | if (ret) { |
338 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); | |
033f2752 | 339 | return ret; |
d88b25be RV |
340 | } |
341 | ||
d245b3f9 LW |
342 | ret = gpiochip_irqchip_add_nested(&tc3589x_gpio->chip, |
343 | &tc3589x_gpio_irq_chip, | |
344 | 0, | |
345 | handle_simple_irq, | |
346 | IRQ_TYPE_NONE); | |
cf42f1cf LW |
347 | if (ret) { |
348 | dev_err(&pdev->dev, | |
349 | "could not connect irqchip to gpiochip\n"); | |
350 | return ret; | |
351 | } | |
352 | ||
d245b3f9 LW |
353 | gpiochip_set_nested_irqchip(&tc3589x_gpio->chip, |
354 | &tc3589x_gpio_irq_chip, | |
355 | irq); | |
3f97d5fc | 356 | |
20406ebf | 357 | platform_set_drvdata(pdev, tc3589x_gpio); |
d88b25be RV |
358 | |
359 | return 0; | |
d88b25be RV |
360 | } |
361 | ||
20406ebf SI |
362 | static struct platform_driver tc3589x_gpio_driver = { |
363 | .driver.name = "tc3589x-gpio", | |
20406ebf | 364 | .probe = tc3589x_gpio_probe, |
d88b25be RV |
365 | }; |
366 | ||
20406ebf | 367 | static int __init tc3589x_gpio_init(void) |
d88b25be | 368 | { |
20406ebf | 369 | return platform_driver_register(&tc3589x_gpio_driver); |
d88b25be | 370 | } |
20406ebf | 371 | subsys_initcall(tc3589x_gpio_init); |