[linux-block.git] / drivers / gpio / gpio-tc3589x.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
 */

#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
#include <linux/of.h>
#include <linux/interrupt.h>
#include <linux/mfd/tc3589x.h>
#include <linux/bitops.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_IBE, REG_IEV, REG_IS, REG_IE, REG_DIRECT };

#define CACHE_NR_REGS	5
#define CACHE_NR_BANKS	3

struct tc3589x_gpio {
	struct gpio_chip chip;
	struct tc3589x *tc3589x;
	struct device *dev;
	struct mutex irq_lock;
	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
	u8 mask = BIT(offset % 8);
	int ret;

	ret = tc3589x_reg_read(tc3589x, reg);
	if (ret < 0)
		return ret;

	return !!(ret & mask);
}

static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
	unsigned int pos = offset % 8;
	u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};

	tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
}

static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
					 unsigned int offset, int val)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODIR0 + offset / 8;
	unsigned int pos = offset % 8;

	tc3589x_gpio_set(chip, offset, val);

	return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
}

static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
					unsigned int offset)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODIR0 + offset / 8;
	unsigned int pos = offset % 8;

	return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
}

static int tc3589x_gpio_get_direction(struct gpio_chip *chip,
				      unsigned int offset)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 reg = TC3589x_GPIODIR0 + offset / 8;
	unsigned int pos = offset % 8;
	int ret;

	ret = tc3589x_reg_read(tc3589x, reg);
	if (ret < 0)
		return ret;

	if (ret & BIT(pos))
		return GPIO_LINE_DIRECTION_OUT;

	return GPIO_LINE_DIRECTION_IN;
}

static int tc3589x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
				   unsigned long config)
{
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	/*
	 * These registers are alterated at each second address
	 * ODM bit 0 = drive to GND or Hi-Z (open drain)
	 * ODM bit 1 = drive to VDD or Hi-Z (open source)
	 */
	u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2;
	u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2;
	unsigned int pos = offset % 8;
	int ret;

	switch (pinconf_to_config_param(config)) {
	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
		/* Set open drain mode */
		ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0);
		if (ret)
			return ret;
		/* Enable open drain/source mode */
		return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
		/* Set open source mode */
		ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos));
		if (ret)
			return ret;
		/* Enable open drain/source mode */
		return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
	case PIN_CONFIG_DRIVE_PUSH_PULL:
		/* Disable open drain/source mode */
		return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0);
	default:
		break;
	}
	return -ENOTSUPP;
}

static const struct gpio_chip template_chip = {
	.label			= "tc3589x",
	.owner			= THIS_MODULE,
	.get			= tc3589x_gpio_get,
	.set			= tc3589x_gpio_set,
	.direction_output	= tc3589x_gpio_direction_output,
	.direction_input	= tc3589x_gpio_direction_input,
	.get_direction		= tc3589x_gpio_get_direction,
	.set_config		= tc3589x_gpio_set_config,
	.can_sleep		= true,
};

static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	if (type == IRQ_TYPE_EDGE_BOTH) {
		tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
		return 0;
	}

	tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;

	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
		tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
	else
		tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;

	if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
		tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
	else
		tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;

	return 0;
}

static void tc3589x_gpio_irq_lock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);

	mutex_lock(&tc3589x_gpio->irq_lock);
}

static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	static const u8 regmap[] = {
		[REG_IBE]	= TC3589x_GPIOIBE0,
		[REG_IEV]	= TC3589x_GPIOIEV0,
		[REG_IS]	= TC3589x_GPIOIS0,
		[REG_IE]	= TC3589x_GPIOIE0,
		[REG_DIRECT]	= TC3589x_DIRECT0,
	};
	int i, j;

	for (i = 0; i < CACHE_NR_REGS; i++) {
		for (j = 0; j < CACHE_NR_BANKS; j++) {
			u8 old = tc3589x_gpio->oldregs[i][j];
			u8 new = tc3589x_gpio->regs[i][j];

			if (new == old)
				continue;

			tc3589x_gpio->oldregs[i][j] = new;
			tc3589x_reg_write(tc3589x, regmap[i] + j, new);
		}
	}

	mutex_unlock(&tc3589x_gpio->irq_lock);
}

static void tc3589x_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
	tc3589x_gpio->regs[REG_DIRECT][regoffset] |= mask;
	gpiochip_disable_irq(gc, offset);
}

static void tc3589x_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	gpiochip_enable_irq(gc, offset);
	tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
	tc3589x_gpio->regs[REG_DIRECT][regoffset] &= ~mask;
}

static const struct irq_chip tc3589x_gpio_irq_chip = {
	.name			= "tc3589x-gpio",
	.irq_bus_lock		= tc3589x_gpio_irq_lock,
	.irq_bus_sync_unlock	= tc3589x_gpio_irq_sync_unlock,
	.irq_mask		= tc3589x_gpio_irq_mask,
	.irq_unmask		= tc3589x_gpio_irq_unmask,
	.irq_set_type		= tc3589x_gpio_irq_set_type,
	.flags =		IRQCHIP_IMMUTABLE,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
{
	struct tc3589x_gpio *tc3589x_gpio = dev;
	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	u8 status[CACHE_NR_BANKS];
	int ret;
	int i;

	ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
				 ARRAY_SIZE(status), status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < ARRAY_SIZE(status); i++) {
		unsigned int stat = status[i];
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = i * 8 + bit;
			int irq = irq_find_mapping(tc3589x_gpio->chip.irq.domain,
						   line);

			handle_nested_irq(irq);
			stat &= ~(1 << bit);
		}

		tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
	}

	return IRQ_HANDLED;
}

static int tc3589x_gpio_probe(struct platform_device *pdev)
{
	struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
	struct device_node *np = pdev->dev.of_node;
	struct tc3589x_gpio *tc3589x_gpio;
	struct gpio_irq_chip *girq;
	int ret;
	int irq;

	if (!np) {
		dev_err(&pdev->dev, "No Device Tree node found\n");
		return -EINVAL;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
				    GFP_KERNEL);
	if (!tc3589x_gpio)
		return -ENOMEM;

	mutex_init(&tc3589x_gpio->irq_lock);

	tc3589x_gpio->dev = &pdev->dev;
	tc3589x_gpio->tc3589x = tc3589x;

	tc3589x_gpio->chip = template_chip;
	tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
	tc3589x_gpio->chip.parent = &pdev->dev;
	tc3589x_gpio->chip.base = -1;

	girq = &tc3589x_gpio->chip.irq;
	gpio_irq_chip_set_chip(girq, &tc3589x_gpio_irq_chip);
	/* This will let us handle the parent IRQ in the driver */
	girq->parent_handler = NULL;
	girq->num_parents = 0;
	girq->parents = NULL;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_simple_irq;
	girq->threaded = true;

	/* Bring the GPIO module out of reset */
	ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
			       TC3589x_RSTCTRL_GPIRST, 0);
	if (ret < 0)
		return ret;

	 /* For tc35894, have to disable Direct KBD interrupts,
	  * else IRQST will always be 0x20, IRQN low level, can't
	  * clear the irq status.
	  * TODO: need more test on other tc3589x chip.
	  *
	  */
	ret = tc3589x_reg_write(tc3589x, TC3589x_DKBDMSK,
			TC3589x_DKBDMSK_ELINT | TC3589x_DKBDMSK_EINT);
	if (ret < 0)
		return ret;

	ret = devm_request_threaded_irq(&pdev->dev,
					irq, NULL, tc3589x_gpio_irq,
					IRQF_ONESHOT, "tc3589x-gpio",
					tc3589x_gpio);
	if (ret) {
		dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
		return ret;
	}

	return devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip, tc3589x_gpio);
}

static struct platform_driver tc3589x_gpio_driver = {
	.driver.name	= "tc3589x-gpio",
	.probe		= tc3589x_gpio_probe,
};

static int __init tc3589x_gpio_init(void)
{
	return platform_driver_register(&tc3589x_gpio_driver);
}
subsys_initcall(tc3589x_gpio_init);
Commit	Line	Data
1f67b599	1	// SPDX-License-Identifier: GPL-2.0-only
d88b25be RV	2	/*
	3	* Copyright (C) ST-Ericsson SA 2010
	4	*
d88b25be RV	5	* Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
	6	* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	7	*/
	8
d88b25be RV	9	#include <linux/init.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/slab.h>
cee1b40d	12	#include <linux/gpio/driver.h>
3113e679	13	#include <linux/of.h>
d88b25be	14	#include <linux/interrupt.h>
c6eda6c5	15	#include <linux/mfd/tc3589x.h>
cee1b40d	16	#include <linux/bitops.h>
d88b25be RV	17
	18	/*
	19	* These registers are modified under the irq bus lock and cached to avoid
	20	* unnecessary writes in bus_sync_unlock.
	21	*/
d284c16f	22	enum { REG_IBE, REG_IEV, REG_IS, REG_IE, REG_DIRECT };
d88b25be	23
d284c16f	24	#define CACHE_NR_REGS 5
d88b25be RV	25	#define CACHE_NR_BANKS 3
d88b25be RV	26
20406ebf	27	struct tc3589x_gpio {
d88b25be	28	struct gpio_chip chip;
20406ebf	29	struct tc3589x *tc3589x;
d88b25be RV	30	struct device *dev;
d88b25be RV	31	struct mutex irq_lock;
d88b25be RV	32	/* Caches of interrupt control registers for bus_lock */
	33	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	34	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	35	};
	36
0e4011eb	37	static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned int offset)
d88b25be	38	{
b0d38473	39	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
20406ebf SI	40	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
20406ebf SI	41	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
cee1b40d	42	u8 mask = BIT(offset % 8);
d88b25be RV	43	int ret;
d88b25be RV	44
20406ebf	45	ret = tc3589x_reg_read(tc3589x, reg);
d88b25be RV	46	if (ret < 0)
	47	return ret;
	48
27ca2267	49	return !!(ret & mask);
d88b25be RV	50	}
d88b25be RV	51
0e4011eb	52	static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
d88b25be	53	{
b0d38473	54	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
20406ebf SI	55	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
20406ebf SI	56	u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
0e4011eb	57	unsigned int pos = offset % 8;
cee1b40d	58	u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};
d88b25be	59
20406ebf	60	tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
d88b25be RV	61	}
d88b25be RV	62
20406ebf	63	static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
0e4011eb	64	unsigned int offset, int val)
d88b25be	65	{
b0d38473	66	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
20406ebf SI	67	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
20406ebf SI	68	u8 reg = TC3589x_GPIODIR0 + offset / 8;
0e4011eb	69	unsigned int pos = offset % 8;
d88b25be	70
20406ebf	71	tc3589x_gpio_set(chip, offset, val);
d88b25be	72
cee1b40d	73	return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
d88b25be RV	74	}
d88b25be RV	75
20406ebf	76	static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
0e4011eb	77	unsigned int offset)
d88b25be	78	{
b0d38473	79	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
20406ebf SI	80	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
20406ebf SI	81	u8 reg = TC3589x_GPIODIR0 + offset / 8;
0e4011eb	82	unsigned int pos = offset % 8;
d88b25be	83
cee1b40d	84	return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
d88b25be RV	85	}
d88b25be RV	86
14063d71	87	static int tc3589x_gpio_get_direction(struct gpio_chip *chip,
0e4011eb	88	unsigned int offset)
14063d71 LW	89	{
	90	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	91	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	92	u8 reg = TC3589x_GPIODIR0 + offset / 8;
0e4011eb	93	unsigned int pos = offset % 8;
14063d71 LW	94	int ret;
	95
	96	ret = tc3589x_reg_read(tc3589x, reg);
	97	if (ret < 0)
	98	return ret;
	99
e42615ec MV	100	if (ret & BIT(pos))
	101	return GPIO_LINE_DIRECTION_OUT;
	102
	103	return GPIO_LINE_DIRECTION_IN;
14063d71 LW	104	}
14063d71 LW	105
2956b5d9 MW	106	static int tc3589x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
2956b5d9 MW	107	unsigned long config)
8b866b06 LW	108	{
	109	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
	110	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
	111	/*
	112	* These registers are alterated at each second address
	113	* ODM bit 0 = drive to GND or Hi-Z (open drain)
	114	* ODM bit 1 = drive to VDD or Hi-Z (open source)
	115	*/
	116	u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2;
	117	u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2;
0e4011eb	118	unsigned int pos = offset % 8;
8b866b06 LW	119	int ret;
8b866b06 LW	120
2956b5d9 MW	121	switch (pinconf_to_config_param(config)) {
2956b5d9 MW	122	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
8b866b06 LW	123	/* Set open drain mode */
	124	ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0);
	125	if (ret)
	126	return ret;
	127	/* Enable open drain/source mode */
	128	return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
2956b5d9	129	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
8b866b06 LW	130	/* Set open source mode */
	131	ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos));
	132	if (ret)
	133	return ret;
	134	/* Enable open drain/source mode */
	135	return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
2956b5d9	136	case PIN_CONFIG_DRIVE_PUSH_PULL:
8b866b06 LW	137	/* Disable open drain/source mode */
	138	return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0);
	139	default:
	140	break;
	141	}
	142	return -ENOTSUPP;
	143	}
	144
e35b5ab0	145	static const struct gpio_chip template_chip = {
20406ebf	146	.label = "tc3589x",
d88b25be	147	.owner = THIS_MODULE,
20406ebf	148	.get = tc3589x_gpio_get,
20406ebf	149	.set = tc3589x_gpio_set,
14063d71 LW	150	.direction_output = tc3589x_gpio_direction_output,
	151	.direction_input = tc3589x_gpio_direction_input,
	152	.get_direction = tc3589x_gpio_get_direction,
2956b5d9	153	.set_config = tc3589x_gpio_set_config,
9fb1f39e	154	.can_sleep = true,
d88b25be RV	155	};
d88b25be RV	156
33fcc1b8	157	static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
d88b25be	158	{
cf42f1cf	159	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	160	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
efe4c949	161	int offset = d->hwirq;
d88b25be	162	int regoffset = offset / 8;
cee1b40d	163	int mask = BIT(offset % 8);
d88b25be RV	164
d88b25be RV	165	if (type == IRQ_TYPE_EDGE_BOTH) {
20406ebf	166	tc3589x_gpio->regs[REG_IBE][regoffset] \|= mask;
d88b25be RV	167	return 0;
	168	}
	169
20406ebf	170	tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
d88b25be RV	171
d88b25be RV	172	if (type == IRQ_TYPE_LEVEL_LOW \|\| type == IRQ_TYPE_LEVEL_HIGH)
20406ebf	173	tc3589x_gpio->regs[REG_IS][regoffset] \|= mask;
d88b25be	174	else
20406ebf	175	tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
d88b25be RV	176
d88b25be RV	177	if (type == IRQ_TYPE_EDGE_RISING \|\| type == IRQ_TYPE_LEVEL_HIGH)
20406ebf	178	tc3589x_gpio->regs[REG_IEV][regoffset] \|= mask;
d88b25be	179	else
20406ebf	180	tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
d88b25be RV	181
	182	return 0;
	183	}
	184
33fcc1b8	185	static void tc3589x_gpio_irq_lock(struct irq_data *d)
d88b25be	186	{
cf42f1cf	187	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	188	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
d88b25be	189
20406ebf	190	mutex_lock(&tc3589x_gpio->irq_lock);
d88b25be RV	191	}
d88b25be RV	192
33fcc1b8	193	static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
d88b25be	194	{
cf42f1cf	195	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	196	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
20406ebf	197	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
d88b25be	198	static const u8 regmap[] = {
20406ebf SI	199	[REG_IBE] = TC3589x_GPIOIBE0,
	200	[REG_IEV] = TC3589x_GPIOIEV0,
	201	[REG_IS] = TC3589x_GPIOIS0,
	202	[REG_IE] = TC3589x_GPIOIE0,
d284c16f	203	[REG_DIRECT] = TC3589x_DIRECT0,
d88b25be RV	204	};
	205	int i, j;
	206
	207	for (i = 0; i < CACHE_NR_REGS; i++) {
	208	for (j = 0; j < CACHE_NR_BANKS; j++) {
20406ebf SI	209	u8 old = tc3589x_gpio->oldregs[i][j];
20406ebf SI	210	u8 new = tc3589x_gpio->regs[i][j];
d88b25be RV	211
	212	if (new == old)
	213	continue;
	214
20406ebf	215	tc3589x_gpio->oldregs[i][j] = new;
214b0e1a	216	tc3589x_reg_write(tc3589x, regmap[i] + j, new);
d88b25be RV	217	}
	218	}
	219
20406ebf	220	mutex_unlock(&tc3589x_gpio->irq_lock);
d88b25be RV	221	}
d88b25be RV	222
33fcc1b8	223	static void tc3589x_gpio_irq_mask(struct irq_data *d)
d88b25be	224	{
cf42f1cf	225	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	226	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
efe4c949	227	int offset = d->hwirq;
d88b25be	228	int regoffset = offset / 8;
cee1b40d	229	int mask = BIT(offset % 8);
d88b25be	230
20406ebf	231	tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
d284c16f	232	tc3589x_gpio->regs[REG_DIRECT][regoffset] \|= mask;
3c92506d	233	gpiochip_disable_irq(gc, offset);
d88b25be RV	234	}
d88b25be RV	235
33fcc1b8	236	static void tc3589x_gpio_irq_unmask(struct irq_data *d)
d88b25be	237	{
cf42f1cf	238	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b0d38473	239	struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
efe4c949	240	int offset = d->hwirq;
d88b25be	241	int regoffset = offset / 8;
cee1b40d	242	int mask = BIT(offset % 8);
d88b25be	243
3c92506d	244	gpiochip_enable_irq(gc, offset);
20406ebf	245	tc3589x_gpio->regs[REG_IE][regoffset] \|= mask;
d284c16f	246	tc3589x_gpio->regs[REG_DIRECT][regoffset] &= ~mask;
d88b25be RV	247	}
d88b25be RV	248
3c92506d	249	static const struct irq_chip tc3589x_gpio_irq_chip = {
20406ebf	250	.name = "tc3589x-gpio",
33fcc1b8 LB	251	.irq_bus_lock = tc3589x_gpio_irq_lock,
	252	.irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
	253	.irq_mask = tc3589x_gpio_irq_mask,
	254	.irq_unmask = tc3589x_gpio_irq_unmask,
	255	.irq_set_type = tc3589x_gpio_irq_set_type,
3c92506d LW	256	.flags = IRQCHIP_IMMUTABLE,
3c92506d LW	257	GPIOCHIP_IRQ_RESOURCE_HELPERS,
d88b25be RV	258	};
d88b25be RV	259
20406ebf	260	static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
d88b25be	261	{
20406ebf SI	262	struct tc3589x_gpio *tc3589x_gpio = dev;
20406ebf SI	263	struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
d88b25be RV	264	u8 status[CACHE_NR_BANKS];
	265	int ret;
	266	int i;
	267
20406ebf	268	ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
d88b25be RV	269	ARRAY_SIZE(status), status);
	270	if (ret < 0)
	271	return IRQ_NONE;
	272
	273	for (i = 0; i < ARRAY_SIZE(status); i++) {
	274	unsigned int stat = status[i];
	275	if (!stat)
	276	continue;
	277
	278	while (stat) {
	279	int bit = __ffs(stat);
	280	int line = i * 8 + bit;
f0fbe7bc	281	int irq = irq_find_mapping(tc3589x_gpio->chip.irq.domain,
cf42f1cf	282	line);
d88b25be	283
e300376d	284	handle_nested_irq(irq);
d88b25be RV	285	stat &= ~(1 << bit);
	286	}
	287
20406ebf	288	tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
d88b25be RV	289	}
	290
	291	return IRQ_HANDLED;
	292	}
	293
3836309d	294	static int tc3589x_gpio_probe(struct platform_device *pdev)
d88b25be	295	{
20406ebf	296	struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
3113e679	297	struct device_node *np = pdev->dev.of_node;
20406ebf	298	struct tc3589x_gpio *tc3589x_gpio;
0fcfd9aa	299	struct gpio_irq_chip *girq;
d88b25be RV	300	int ret;
	301	int irq;
	302
53e41f55 LW	303	if (!np) {
53e41f55 LW	304	dev_err(&pdev->dev, "No Device Tree node found\n");
3113e679 LJ	305	return -EINVAL;
3113e679 LJ	306	}
d88b25be RV	307
	308	irq = platform_get_irq(pdev, 0);
	309	if (irq < 0)
	310	return irq;
	311
033f2752 LW	312	tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
033f2752 LW	313	GFP_KERNEL);
20406ebf	314	if (!tc3589x_gpio)
d88b25be RV	315	return -ENOMEM;
d88b25be RV	316
20406ebf	317	mutex_init(&tc3589x_gpio->irq_lock);
d88b25be	318
20406ebf SI	319	tc3589x_gpio->dev = &pdev->dev;
20406ebf SI	320	tc3589x_gpio->tc3589x = tc3589x;
d88b25be	321
20406ebf SI	322	tc3589x_gpio->chip = template_chip;
20406ebf SI	323	tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
58383c78	324	tc3589x_gpio->chip.parent = &pdev->dev;
90f2d0f7	325	tc3589x_gpio->chip.base = -1;
d88b25be	326
0fcfd9aa	327	girq = &tc3589x_gpio->chip.irq;
3c92506d	328	gpio_irq_chip_set_chip(girq, &tc3589x_gpio_irq_chip);
0fcfd9aa LW	329	/* This will let us handle the parent IRQ in the driver */
	330	girq->parent_handler = NULL;
	331	girq->num_parents = 0;
	332	girq->parents = NULL;
	333	girq->default_type = IRQ_TYPE_NONE;
	334	girq->handler = handle_simple_irq;
	335	girq->threaded = true;
	336
d88b25be	337	/* Bring the GPIO module out of reset */
20406ebf SI	338	ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
20406ebf SI	339	TC3589x_RSTCTRL_GPIRST, 0);
d88b25be	340	if (ret < 0)
033f2752	341	return ret;
d88b25be	342
d284c16f	343	/* For tc35894, have to disable Direct KBD interrupts,
	344	* else IRQST will always be 0x20, IRQN low level, can't
	345	* clear the irq status.
	346	* TODO: need more test on other tc3589x chip.
	347	*
	348	*/
	349	ret = tc3589x_reg_write(tc3589x, TC3589x_DKBDMSK,
	350	TC3589x_DKBDMSK_ELINT \| TC3589x_DKBDMSK_EINT);
	351	if (ret < 0)
	352	return ret;
	353
033f2752 LW	354	ret = devm_request_threaded_irq(&pdev->dev,
	355	irq, NULL, tc3589x_gpio_irq,
	356	IRQF_ONESHOT, "tc3589x-gpio",
	357	tc3589x_gpio);
d88b25be RV	358	if (ret) {
d88b25be RV	359	dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
033f2752	360	return ret;
d88b25be RV	361	}
d88b25be RV	362
3660660a	363	return devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip, tc3589x_gpio);
d88b25be RV	364	}
d88b25be RV	365
20406ebf SI	366	static struct platform_driver tc3589x_gpio_driver = {
20406ebf SI	367	.driver.name = "tc3589x-gpio",
20406ebf	368	.probe = tc3589x_gpio_probe,
d88b25be RV	369	};
d88b25be RV	370
20406ebf	371	static int __init tc3589x_gpio_init(void)
d88b25be	372	{
20406ebf	373	return platform_driver_register(&tc3589x_gpio_driver);
d88b25be	374	}
20406ebf	375	subsys_initcall(tc3589x_gpio_init);