Commit | Line | Data |
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d88b25be RV |
1 | /* |
2 | * Copyright (C) ST-Ericsson SA 2010 | |
3 | * | |
4 | * License Terms: GNU General Public License, version 2 | |
5 | * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson | |
6 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson | |
7 | */ | |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/init.h> | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/gpio.h> | |
3113e679 | 14 | #include <linux/of.h> |
d88b25be | 15 | #include <linux/interrupt.h> |
c6eda6c5 | 16 | #include <linux/mfd/tc3589x.h> |
d88b25be RV |
17 | |
18 | /* | |
19 | * These registers are modified under the irq bus lock and cached to avoid | |
20 | * unnecessary writes in bus_sync_unlock. | |
21 | */ | |
22 | enum { REG_IBE, REG_IEV, REG_IS, REG_IE }; | |
23 | ||
24 | #define CACHE_NR_REGS 4 | |
25 | #define CACHE_NR_BANKS 3 | |
26 | ||
20406ebf | 27 | struct tc3589x_gpio { |
d88b25be | 28 | struct gpio_chip chip; |
20406ebf | 29 | struct tc3589x *tc3589x; |
d88b25be RV |
30 | struct device *dev; |
31 | struct mutex irq_lock; | |
d88b25be RV |
32 | /* Caches of interrupt control registers for bus_lock */ |
33 | u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
34 | u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS]; | |
35 | }; | |
36 | ||
20406ebf | 37 | static inline struct tc3589x_gpio *to_tc3589x_gpio(struct gpio_chip *chip) |
d88b25be | 38 | { |
20406ebf | 39 | return container_of(chip, struct tc3589x_gpio, chip); |
d88b25be RV |
40 | } |
41 | ||
20406ebf | 42 | static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset) |
d88b25be | 43 | { |
20406ebf SI |
44 | struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip); |
45 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; | |
46 | u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2; | |
d88b25be RV |
47 | u8 mask = 1 << (offset % 8); |
48 | int ret; | |
49 | ||
20406ebf | 50 | ret = tc3589x_reg_read(tc3589x, reg); |
d88b25be RV |
51 | if (ret < 0) |
52 | return ret; | |
53 | ||
54 | return ret & mask; | |
55 | } | |
56 | ||
20406ebf | 57 | static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val) |
d88b25be | 58 | { |
20406ebf SI |
59 | struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip); |
60 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; | |
61 | u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2; | |
d88b25be RV |
62 | unsigned pos = offset % 8; |
63 | u8 data[] = {!!val << pos, 1 << pos}; | |
64 | ||
20406ebf | 65 | tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data); |
d88b25be RV |
66 | } |
67 | ||
20406ebf | 68 | static int tc3589x_gpio_direction_output(struct gpio_chip *chip, |
d88b25be RV |
69 | unsigned offset, int val) |
70 | { | |
20406ebf SI |
71 | struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip); |
72 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; | |
73 | u8 reg = TC3589x_GPIODIR0 + offset / 8; | |
d88b25be RV |
74 | unsigned pos = offset % 8; |
75 | ||
20406ebf | 76 | tc3589x_gpio_set(chip, offset, val); |
d88b25be | 77 | |
20406ebf | 78 | return tc3589x_set_bits(tc3589x, reg, 1 << pos, 1 << pos); |
d88b25be RV |
79 | } |
80 | ||
20406ebf | 81 | static int tc3589x_gpio_direction_input(struct gpio_chip *chip, |
d88b25be RV |
82 | unsigned offset) |
83 | { | |
20406ebf SI |
84 | struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip); |
85 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; | |
86 | u8 reg = TC3589x_GPIODIR0 + offset / 8; | |
d88b25be RV |
87 | unsigned pos = offset % 8; |
88 | ||
20406ebf | 89 | return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0); |
d88b25be RV |
90 | } |
91 | ||
d88b25be | 92 | static struct gpio_chip template_chip = { |
20406ebf | 93 | .label = "tc3589x", |
d88b25be | 94 | .owner = THIS_MODULE, |
20406ebf SI |
95 | .direction_input = tc3589x_gpio_direction_input, |
96 | .get = tc3589x_gpio_get, | |
97 | .direction_output = tc3589x_gpio_direction_output, | |
98 | .set = tc3589x_gpio_set, | |
9fb1f39e | 99 | .can_sleep = true, |
d88b25be RV |
100 | }; |
101 | ||
33fcc1b8 | 102 | static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
d88b25be | 103 | { |
cf42f1cf LW |
104 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
105 | struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip); | |
efe4c949 | 106 | int offset = d->hwirq; |
d88b25be RV |
107 | int regoffset = offset / 8; |
108 | int mask = 1 << (offset % 8); | |
109 | ||
110 | if (type == IRQ_TYPE_EDGE_BOTH) { | |
20406ebf | 111 | tc3589x_gpio->regs[REG_IBE][regoffset] |= mask; |
d88b25be RV |
112 | return 0; |
113 | } | |
114 | ||
20406ebf | 115 | tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask; |
d88b25be RV |
116 | |
117 | if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH) | |
20406ebf | 118 | tc3589x_gpio->regs[REG_IS][regoffset] |= mask; |
d88b25be | 119 | else |
20406ebf | 120 | tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask; |
d88b25be RV |
121 | |
122 | if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) | |
20406ebf | 123 | tc3589x_gpio->regs[REG_IEV][regoffset] |= mask; |
d88b25be | 124 | else |
20406ebf | 125 | tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask; |
d88b25be RV |
126 | |
127 | return 0; | |
128 | } | |
129 | ||
33fcc1b8 | 130 | static void tc3589x_gpio_irq_lock(struct irq_data *d) |
d88b25be | 131 | { |
cf42f1cf LW |
132 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
133 | struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip); | |
d88b25be | 134 | |
20406ebf | 135 | mutex_lock(&tc3589x_gpio->irq_lock); |
d88b25be RV |
136 | } |
137 | ||
33fcc1b8 | 138 | static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d) |
d88b25be | 139 | { |
cf42f1cf LW |
140 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
141 | struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip); | |
20406ebf | 142 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; |
d88b25be | 143 | static const u8 regmap[] = { |
20406ebf SI |
144 | [REG_IBE] = TC3589x_GPIOIBE0, |
145 | [REG_IEV] = TC3589x_GPIOIEV0, | |
146 | [REG_IS] = TC3589x_GPIOIS0, | |
147 | [REG_IE] = TC3589x_GPIOIE0, | |
d88b25be RV |
148 | }; |
149 | int i, j; | |
150 | ||
151 | for (i = 0; i < CACHE_NR_REGS; i++) { | |
152 | for (j = 0; j < CACHE_NR_BANKS; j++) { | |
20406ebf SI |
153 | u8 old = tc3589x_gpio->oldregs[i][j]; |
154 | u8 new = tc3589x_gpio->regs[i][j]; | |
d88b25be RV |
155 | |
156 | if (new == old) | |
157 | continue; | |
158 | ||
20406ebf SI |
159 | tc3589x_gpio->oldregs[i][j] = new; |
160 | tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new); | |
d88b25be RV |
161 | } |
162 | } | |
163 | ||
20406ebf | 164 | mutex_unlock(&tc3589x_gpio->irq_lock); |
d88b25be RV |
165 | } |
166 | ||
33fcc1b8 | 167 | static void tc3589x_gpio_irq_mask(struct irq_data *d) |
d88b25be | 168 | { |
cf42f1cf LW |
169 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
170 | struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip); | |
efe4c949 | 171 | int offset = d->hwirq; |
d88b25be RV |
172 | int regoffset = offset / 8; |
173 | int mask = 1 << (offset % 8); | |
174 | ||
20406ebf | 175 | tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask; |
d88b25be RV |
176 | } |
177 | ||
33fcc1b8 | 178 | static void tc3589x_gpio_irq_unmask(struct irq_data *d) |
d88b25be | 179 | { |
cf42f1cf LW |
180 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
181 | struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip); | |
efe4c949 | 182 | int offset = d->hwirq; |
d88b25be RV |
183 | int regoffset = offset / 8; |
184 | int mask = 1 << (offset % 8); | |
185 | ||
20406ebf | 186 | tc3589x_gpio->regs[REG_IE][regoffset] |= mask; |
d88b25be RV |
187 | } |
188 | ||
20406ebf SI |
189 | static struct irq_chip tc3589x_gpio_irq_chip = { |
190 | .name = "tc3589x-gpio", | |
33fcc1b8 LB |
191 | .irq_bus_lock = tc3589x_gpio_irq_lock, |
192 | .irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock, | |
193 | .irq_mask = tc3589x_gpio_irq_mask, | |
194 | .irq_unmask = tc3589x_gpio_irq_unmask, | |
195 | .irq_set_type = tc3589x_gpio_irq_set_type, | |
d88b25be RV |
196 | }; |
197 | ||
20406ebf | 198 | static irqreturn_t tc3589x_gpio_irq(int irq, void *dev) |
d88b25be | 199 | { |
20406ebf SI |
200 | struct tc3589x_gpio *tc3589x_gpio = dev; |
201 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; | |
d88b25be RV |
202 | u8 status[CACHE_NR_BANKS]; |
203 | int ret; | |
204 | int i; | |
205 | ||
20406ebf | 206 | ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0, |
d88b25be RV |
207 | ARRAY_SIZE(status), status); |
208 | if (ret < 0) | |
209 | return IRQ_NONE; | |
210 | ||
211 | for (i = 0; i < ARRAY_SIZE(status); i++) { | |
212 | unsigned int stat = status[i]; | |
213 | if (!stat) | |
214 | continue; | |
215 | ||
216 | while (stat) { | |
217 | int bit = __ffs(stat); | |
218 | int line = i * 8 + bit; | |
cf42f1cf LW |
219 | int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain, |
220 | line); | |
d88b25be | 221 | |
e300376d | 222 | handle_nested_irq(irq); |
d88b25be RV |
223 | stat &= ~(1 << bit); |
224 | } | |
225 | ||
20406ebf | 226 | tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]); |
d88b25be RV |
227 | } |
228 | ||
229 | return IRQ_HANDLED; | |
230 | } | |
231 | ||
3836309d | 232 | static int tc3589x_gpio_probe(struct platform_device *pdev) |
d88b25be | 233 | { |
20406ebf SI |
234 | struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent); |
235 | struct tc3589x_gpio_platform_data *pdata; | |
3113e679 | 236 | struct device_node *np = pdev->dev.of_node; |
20406ebf | 237 | struct tc3589x_gpio *tc3589x_gpio; |
d88b25be RV |
238 | int ret; |
239 | int irq; | |
240 | ||
20406ebf | 241 | pdata = tc3589x->pdata->gpio; |
3113e679 LJ |
242 | |
243 | if (!(pdata || np)) { | |
244 | dev_err(&pdev->dev, "No platform data or Device Tree found\n"); | |
245 | return -EINVAL; | |
246 | } | |
d88b25be RV |
247 | |
248 | irq = platform_get_irq(pdev, 0); | |
249 | if (irq < 0) | |
250 | return irq; | |
251 | ||
033f2752 LW |
252 | tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio), |
253 | GFP_KERNEL); | |
20406ebf | 254 | if (!tc3589x_gpio) |
d88b25be RV |
255 | return -ENOMEM; |
256 | ||
20406ebf | 257 | mutex_init(&tc3589x_gpio->irq_lock); |
d88b25be | 258 | |
20406ebf SI |
259 | tc3589x_gpio->dev = &pdev->dev; |
260 | tc3589x_gpio->tc3589x = tc3589x; | |
d88b25be | 261 | |
20406ebf SI |
262 | tc3589x_gpio->chip = template_chip; |
263 | tc3589x_gpio->chip.ngpio = tc3589x->num_gpio; | |
264 | tc3589x_gpio->chip.dev = &pdev->dev; | |
3113e679 | 265 | tc3589x_gpio->chip.base = (pdata) ? pdata->gpio_base : -1; |
d88b25be | 266 | |
3113e679 | 267 | #ifdef CONFIG_OF_GPIO |
e90c636b | 268 | tc3589x_gpio->chip.of_node = np; |
3113e679 | 269 | #endif |
d88b25be RV |
270 | |
271 | /* Bring the GPIO module out of reset */ | |
20406ebf SI |
272 | ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL, |
273 | TC3589x_RSTCTRL_GPIRST, 0); | |
d88b25be | 274 | if (ret < 0) |
033f2752 | 275 | return ret; |
d88b25be | 276 | |
033f2752 LW |
277 | ret = devm_request_threaded_irq(&pdev->dev, |
278 | irq, NULL, tc3589x_gpio_irq, | |
279 | IRQF_ONESHOT, "tc3589x-gpio", | |
280 | tc3589x_gpio); | |
d88b25be RV |
281 | if (ret) { |
282 | dev_err(&pdev->dev, "unable to get irq: %d\n", ret); | |
033f2752 | 283 | return ret; |
d88b25be RV |
284 | } |
285 | ||
20406ebf | 286 | ret = gpiochip_add(&tc3589x_gpio->chip); |
d88b25be RV |
287 | if (ret) { |
288 | dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret); | |
033f2752 | 289 | return ret; |
d88b25be RV |
290 | } |
291 | ||
cf42f1cf LW |
292 | ret = gpiochip_irqchip_add(&tc3589x_gpio->chip, |
293 | &tc3589x_gpio_irq_chip, | |
294 | 0, | |
295 | handle_simple_irq, | |
296 | IRQ_TYPE_NONE); | |
297 | if (ret) { | |
298 | dev_err(&pdev->dev, | |
299 | "could not connect irqchip to gpiochip\n"); | |
300 | return ret; | |
301 | } | |
302 | ||
3113e679 | 303 | if (pdata && pdata->setup) |
20406ebf | 304 | pdata->setup(tc3589x, tc3589x_gpio->chip.base); |
f0a7a98d | 305 | |
20406ebf | 306 | platform_set_drvdata(pdev, tc3589x_gpio); |
d88b25be RV |
307 | |
308 | return 0; | |
d88b25be RV |
309 | } |
310 | ||
206210ce | 311 | static int tc3589x_gpio_remove(struct platform_device *pdev) |
d88b25be | 312 | { |
20406ebf SI |
313 | struct tc3589x_gpio *tc3589x_gpio = platform_get_drvdata(pdev); |
314 | struct tc3589x *tc3589x = tc3589x_gpio->tc3589x; | |
315 | struct tc3589x_gpio_platform_data *pdata = tc3589x->pdata->gpio; | |
d88b25be RV |
316 | int ret; |
317 | ||
3113e679 | 318 | if (pdata && pdata->remove) |
20406ebf | 319 | pdata->remove(tc3589x, tc3589x_gpio->chip.base); |
f0a7a98d | 320 | |
20406ebf | 321 | ret = gpiochip_remove(&tc3589x_gpio->chip); |
d88b25be | 322 | if (ret < 0) { |
20406ebf | 323 | dev_err(tc3589x_gpio->dev, |
d88b25be RV |
324 | "unable to remove gpiochip: %d\n", ret); |
325 | return ret; | |
326 | } | |
327 | ||
d88b25be RV |
328 | return 0; |
329 | } | |
330 | ||
20406ebf SI |
331 | static struct platform_driver tc3589x_gpio_driver = { |
332 | .driver.name = "tc3589x-gpio", | |
d88b25be | 333 | .driver.owner = THIS_MODULE, |
20406ebf | 334 | .probe = tc3589x_gpio_probe, |
8283c4ff | 335 | .remove = tc3589x_gpio_remove, |
d88b25be RV |
336 | }; |
337 | ||
20406ebf | 338 | static int __init tc3589x_gpio_init(void) |
d88b25be | 339 | { |
20406ebf | 340 | return platform_driver_register(&tc3589x_gpio_driver); |
d88b25be | 341 | } |
20406ebf | 342 | subsys_initcall(tc3589x_gpio_init); |
d88b25be | 343 | |
20406ebf | 344 | static void __exit tc3589x_gpio_exit(void) |
d88b25be | 345 | { |
20406ebf | 346 | platform_driver_unregister(&tc3589x_gpio_driver); |
d88b25be | 347 | } |
20406ebf | 348 | module_exit(tc3589x_gpio_exit); |
d88b25be RV |
349 | |
350 | MODULE_LICENSE("GPL v2"); | |
20406ebf | 351 | MODULE_DESCRIPTION("TC3589x GPIO driver"); |
d88b25be | 352 | MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent"); |