[linux-2.6-block.git] / drivers / gpio / gpio-tb10x.c

/* Abilis Systems MODULE DESCRIPTION
 *
 * Copyright (C) Abilis Systems 2013
 *
 * Authors: Sascha Leuenberger <sascha.leuenberger@abilis.com>
 *          Christian Ruppert <christian.ruppert@abilis.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/gpio/driver.h>
#include <linux/slab.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/spinlock.h>
#include <linux/bitops.h>
#include <linux/pinctrl/consumer.h>

#define TB10X_GPIO_DIR_IN	(0x00000000)
#define TB10X_GPIO_DIR_OUT	(0x00000001)
#define OFFSET_TO_REG_DDR	(0x00)
#define OFFSET_TO_REG_DATA	(0x04)
#define OFFSET_TO_REG_INT_EN	(0x08)
#define OFFSET_TO_REG_CHANGE	(0x0C)
#define OFFSET_TO_REG_WRMASK	(0x10)
#define OFFSET_TO_REG_INT_TYPE	(0x14)


/**
 * @spinlock: used for atomic read/modify/write of registers
 * @base: register base address
 * @domain: IRQ domain of GPIO generated interrupts managed by this controller
 * @irq: Interrupt line of parent interrupt controller
 * @gc: gpio_chip structure associated to this GPIO controller
 */
struct tb10x_gpio {
	spinlock_t spinlock;
	void __iomem *base;
	struct irq_domain *domain;
	int irq;
	struct gpio_chip gc;
};

static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs)
{
	return ioread32(gpio->base + offs);
}

static inline void tb10x_reg_write(struct tb10x_gpio *gpio, unsigned int offs,
				u32 val)
{
	iowrite32(val, gpio->base + offs);
}

static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
				u32 mask, u32 val)
{
	u32 r;
	unsigned long flags;

	spin_lock_irqsave(&gpio->spinlock, flags);

	r = tb10x_reg_read(gpio, offs);
	r = (r & ~mask) | (val & mask);

	tb10x_reg_write(gpio, offs, r);

	spin_unlock_irqrestore(&gpio->spinlock, flags);
}

static int tb10x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
{
	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
	int mask = BIT(offset);
	int val = TB10X_GPIO_DIR_IN << offset;

	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);

	return 0;
}

static int tb10x_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
	int val;

	val = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_DATA);

	if (val & BIT(offset))
		return 1;
	else
		return 0;
}

static void tb10x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
	int mask = BIT(offset);
	int val = value << offset;

	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DATA, mask, val);
}

static int tb10x_gpio_direction_out(struct gpio_chip *chip,
					unsigned offset, int value)
{
	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
	int mask = BIT(offset);
	int val = TB10X_GPIO_DIR_OUT << offset;

	tb10x_gpio_set(chip, offset, value);
	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);

	return 0;
}

static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);

	return irq_create_mapping(tb10x_gpio->domain, offset);
}

static int tb10x_gpio_irq_set_type(struct irq_data *data, unsigned int type)
{
	if ((type & IRQF_TRIGGER_MASK) != IRQ_TYPE_EDGE_BOTH) {
		pr_err("Only (both) edge triggered interrupts supported.\n");
		return -EINVAL;
	}

	irqd_set_trigger_type(data, type);

	return IRQ_SET_MASK_OK;
}

static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
{
	struct tb10x_gpio *tb10x_gpio = data;
	u32 r = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_CHANGE);
	u32 m = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_INT_EN);
	const unsigned long bits = r & m;
	int i;

	for_each_set_bit(i, &bits, 32)
		generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));

	return IRQ_HANDLED;
}

static int tb10x_gpio_probe(struct platform_device *pdev)
{
	struct tb10x_gpio *tb10x_gpio;
	struct resource *mem;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	int ret = -EBUSY;
	u32 ngpio;

	if (!np)
		return -EINVAL;

	if (of_property_read_u32(np, "abilis,ngpio", &ngpio))
		return -EINVAL;

	tb10x_gpio = devm_kzalloc(dev, sizeof(*tb10x_gpio), GFP_KERNEL);
	if (tb10x_gpio == NULL)
		return -ENOMEM;

	spin_lock_init(&tb10x_gpio->spinlock);

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	tb10x_gpio->base = devm_ioremap_resource(dev, mem);
	if (IS_ERR(tb10x_gpio->base))
		return PTR_ERR(tb10x_gpio->base);

	tb10x_gpio->gc.label =
		devm_kasprintf(dev, GFP_KERNEL, "%pOF", pdev->dev.of_node);
	if (!tb10x_gpio->gc.label)
		return -ENOMEM;

	tb10x_gpio->gc.parent		= &pdev->dev;
	tb10x_gpio->gc.owner		= THIS_MODULE;
	tb10x_gpio->gc.direction_input	= tb10x_gpio_direction_in;
	tb10x_gpio->gc.get		= tb10x_gpio_get;
	tb10x_gpio->gc.direction_output	= tb10x_gpio_direction_out;
	tb10x_gpio->gc.set		= tb10x_gpio_set;
	tb10x_gpio->gc.request		= gpiochip_generic_request;
	tb10x_gpio->gc.free		= gpiochip_generic_free;
	tb10x_gpio->gc.base		= -1;
	tb10x_gpio->gc.ngpio		= ngpio;
	tb10x_gpio->gc.can_sleep	= false;


	ret = devm_gpiochip_add_data(&pdev->dev, &tb10x_gpio->gc, tb10x_gpio);
	if (ret < 0) {
		dev_err(dev, "Could not add gpiochip.\n");
		return ret;
	}

	platform_set_drvdata(pdev, tb10x_gpio);

	if (of_find_property(np, "interrupt-controller", NULL)) {
		struct irq_chip_generic *gc;

		ret = platform_get_irq(pdev, 0);
		if (ret < 0) {
			dev_err(dev, "No interrupt specified.\n");
			return ret;
		}

		tb10x_gpio->gc.to_irq	= tb10x_gpio_to_irq;
		tb10x_gpio->irq		= ret;

		ret = devm_request_irq(dev, ret, tb10x_gpio_irq_cascade,
				IRQF_TRIGGER_NONE | IRQF_SHARED,
				dev_name(dev), tb10x_gpio);
		if (ret != 0)
			return ret;

		tb10x_gpio->domain = irq_domain_add_linear(np,
						tb10x_gpio->gc.ngpio,
						&irq_generic_chip_ops, NULL);
		if (!tb10x_gpio->domain) {
			return -ENOMEM;
		}

		ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
				tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
				handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
				IRQ_GC_INIT_MASK_CACHE);
		if (ret)
			return ret;

		gc = tb10x_gpio->domain->gc->gc[0];
		gc->reg_base                         = tb10x_gpio->base;
		gc->chip_types[0].type               = IRQ_TYPE_EDGE_BOTH;
		gc->chip_types[0].chip.irq_ack       = irq_gc_ack_set_bit;
		gc->chip_types[0].chip.irq_mask      = irq_gc_mask_clr_bit;
		gc->chip_types[0].chip.irq_unmask    = irq_gc_mask_set_bit;
		gc->chip_types[0].chip.irq_set_type  = tb10x_gpio_irq_set_type;
		gc->chip_types[0].regs.ack           = OFFSET_TO_REG_CHANGE;
		gc->chip_types[0].regs.mask          = OFFSET_TO_REG_INT_EN;
	}

	return 0;
}

static int tb10x_gpio_remove(struct platform_device *pdev)
{
	struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);

	if (tb10x_gpio->gc.to_irq) {
		irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
					BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
		kfree(tb10x_gpio->domain->gc);
		irq_domain_remove(tb10x_gpio->domain);
	}

	return 0;
}

static const struct of_device_id tb10x_gpio_dt_ids[] = {
	{ .compatible = "abilis,tb10x-gpio" },
	{ }
};
MODULE_DEVICE_TABLE(of, tb10x_gpio_dt_ids);

static struct platform_driver tb10x_gpio_driver = {
	.probe		= tb10x_gpio_probe,
	.remove		= tb10x_gpio_remove,
	.driver = {
		.name	= "tb10x-gpio",
		.of_match_table = tb10x_gpio_dt_ids,
	}
};

module_platform_driver(tb10x_gpio_driver);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("tb10x gpio.");
MODULE_VERSION("0.0.1");
Commit	Line	Data
c6ce2b6b CR	1	/* Abilis Systems MODULE DESCRIPTION
	2	*
	3	* Copyright (C) Abilis Systems 2013
	4	*
	5	* Authors: Sascha Leuenberger <sascha.leuenberger@abilis.com>
	6	* Christian Ruppert <christian.ruppert@abilis.com>
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
	22	#include <linux/kernel.h>
	23	#include <linux/module.h>
	24	#include <linux/platform_device.h>
32e49b9a	25	#include <linux/gpio/driver.h>
c6ce2b6b CR	26	#include <linux/slab.h>
	27	#include <linux/irq.h>
	28	#include <linux/irqdomain.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/io.h>
	31	#include <linux/of.h>
	32	#include <linux/of_platform.h>
c6ce2b6b CR	33	#include <linux/spinlock.h>
	34	#include <linux/bitops.h>
	35	#include <linux/pinctrl/consumer.h>
	36
	37	#define TB10X_GPIO_DIR_IN (0x00000000)
	38	#define TB10X_GPIO_DIR_OUT (0x00000001)
	39	#define OFFSET_TO_REG_DDR (0x00)
	40	#define OFFSET_TO_REG_DATA (0x04)
	41	#define OFFSET_TO_REG_INT_EN (0x08)
	42	#define OFFSET_TO_REG_CHANGE (0x0C)
	43	#define OFFSET_TO_REG_WRMASK (0x10)
	44	#define OFFSET_TO_REG_INT_TYPE (0x14)
	45
	46
	47	/**
	48	* @spinlock: used for atomic read/modify/write of registers
	49	* @base: register base address
	50	* @domain: IRQ domain of GPIO generated interrupts managed by this controller
	51	* @irq: Interrupt line of parent interrupt controller
	52	* @gc: gpio_chip structure associated to this GPIO controller
	53	*/
	54	struct tb10x_gpio {
	55	spinlock_t spinlock;
	56	void __iomem *base;
	57	struct irq_domain *domain;
	58	int irq;
	59	struct gpio_chip gc;
	60	};
	61
	62	static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs)
	63	{
	64	return ioread32(gpio->base + offs);
	65	}
	66
	67	static inline void tb10x_reg_write(struct tb10x_gpio *gpio, unsigned int offs,
	68	u32 val)
	69	{
	70	iowrite32(val, gpio->base + offs);
	71	}
	72
	73	static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
	74	u32 mask, u32 val)
	75	{
	76	u32 r;
	77	unsigned long flags;
	78
	79	spin_lock_irqsave(&gpio->spinlock, flags);
	80
	81	r = tb10x_reg_read(gpio, offs);
	82	r = (r & ~mask) \| (val & mask);
	83
	84	tb10x_reg_write(gpio, offs, r);
	85
	86	spin_unlock_irqrestore(&gpio->spinlock, flags);
	87	}
	88
c6ce2b6b CR	89	static int tb10x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
c6ce2b6b CR	90	{
0ca8c5c4	91	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
c6ce2b6b CR	92	int mask = BIT(offset);
	93	int val = TB10X_GPIO_DIR_IN << offset;
	94
	95	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
	96
	97	return 0;
	98	}
	99
	100	static int tb10x_gpio_get(struct gpio_chip *chip, unsigned offset)
	101	{
0ca8c5c4	102	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
c6ce2b6b CR	103	int val;
	104
	105	val = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_DATA);
	106
	107	if (val & BIT(offset))
	108	return 1;
	109	else
	110	return 0;
	111	}
	112
	113	static void tb10x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	114	{
0ca8c5c4	115	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
c6ce2b6b CR	116	int mask = BIT(offset);
	117	int val = value << offset;
	118
	119	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DATA, mask, val);
	120	}
	121
	122	static int tb10x_gpio_direction_out(struct gpio_chip *chip,
	123	unsigned offset, int value)
	124	{
0ca8c5c4	125	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
c6ce2b6b CR	126	int mask = BIT(offset);
	127	int val = TB10X_GPIO_DIR_OUT << offset;
	128
2e86230f	129	tb10x_gpio_set(chip, offset, value);
c6ce2b6b CR	130	tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
	131
	132	return 0;
	133	}
	134
c6ce2b6b CR	135	static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
c6ce2b6b CR	136	{
0ca8c5c4	137	struct tb10x_gpio *tb10x_gpio = gpiochip_get_data(chip);
c6ce2b6b CR	138
	139	return irq_create_mapping(tb10x_gpio->domain, offset);
	140	}
	141
	142	static int tb10x_gpio_irq_set_type(struct irq_data *data, unsigned int type)
	143	{
	144	if ((type & IRQF_TRIGGER_MASK) != IRQ_TYPE_EDGE_BOTH) {
	145	pr_err("Only (both) edge triggered interrupts supported.\n");
	146	return -EINVAL;
	147	}
	148
	149	irqd_set_trigger_type(data, type);
	150
	151	return IRQ_SET_MASK_OK;
	152	}
	153
	154	static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
	155	{
	156	struct tb10x_gpio *tb10x_gpio = data;
	157	u32 r = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_CHANGE);
	158	u32 m = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_INT_EN);
	159	const unsigned long bits = r & m;
	160	int i;
	161
	162	for_each_set_bit(i, &bits, 32)
	163	generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));
	164
	165	return IRQ_HANDLED;
	166	}
	167
	168	static int tb10x_gpio_probe(struct platform_device *pdev)
	169	{
	170	struct tb10x_gpio *tb10x_gpio;
	171	struct resource *mem;
d28af35b LW	172	struct device *dev = &pdev->dev;
d28af35b LW	173	struct device_node *np = dev->of_node;
c6ce2b6b CR	174	int ret = -EBUSY;
	175	u32 ngpio;
	176
d28af35b	177	if (!np)
c6ce2b6b CR	178	return -EINVAL;
c6ce2b6b CR	179
d28af35b	180	if (of_property_read_u32(np, "abilis,ngpio", &ngpio))
c6ce2b6b CR	181	return -EINVAL;
c6ce2b6b CR	182
d28af35b	183	tb10x_gpio = devm_kzalloc(dev, sizeof(*tb10x_gpio), GFP_KERNEL);
c6ce2b6b CR	184	if (tb10x_gpio == NULL)
	185	return -ENOMEM;
	186
	187	spin_lock_init(&tb10x_gpio->spinlock);
	188
ee2a9f7f	189	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
d28af35b	190	tb10x_gpio->base = devm_ioremap_resource(dev, mem);
9a4864c8 WY	191	if (IS_ERR(tb10x_gpio->base))
9a4864c8 WY	192	return PTR_ERR(tb10x_gpio->base);
c6ce2b6b	193
d28af35b LW	194	tb10x_gpio->gc.label =
d28af35b LW	195	devm_kasprintf(dev, GFP_KERNEL, "%pOF", pdev->dev.of_node);
a5ae5f5c AY	196	if (!tb10x_gpio->gc.label)
	197	return -ENOMEM;
	198
58383c78	199	tb10x_gpio->gc.parent = &pdev->dev;
c6ce2b6b CR	200	tb10x_gpio->gc.owner = THIS_MODULE;
	201	tb10x_gpio->gc.direction_input = tb10x_gpio_direction_in;
	202	tb10x_gpio->gc.get = tb10x_gpio_get;
	203	tb10x_gpio->gc.direction_output = tb10x_gpio_direction_out;
	204	tb10x_gpio->gc.set = tb10x_gpio_set;
203f0daa JG	205	tb10x_gpio->gc.request = gpiochip_generic_request;
203f0daa JG	206	tb10x_gpio->gc.free = gpiochip_generic_free;
c6ce2b6b CR	207	tb10x_gpio->gc.base = -1;
c6ce2b6b CR	208	tb10x_gpio->gc.ngpio = ngpio;
9fb1f39e	209	tb10x_gpio->gc.can_sleep = false;
c6ce2b6b CR	210
c6ce2b6b CR	211
ad7b550a	212	ret = devm_gpiochip_add_data(&pdev->dev, &tb10x_gpio->gc, tb10x_gpio);
c6ce2b6b	213	if (ret < 0) {
d28af35b	214	dev_err(dev, "Could not add gpiochip.\n");
ad7b550a	215	return ret;
c6ce2b6b CR	216	}
	217
	218	platform_set_drvdata(pdev, tb10x_gpio);
	219
d28af35b	220	if (of_find_property(np, "interrupt-controller", NULL)) {
c6ce2b6b CR	221	struct irq_chip_generic *gc;
	222
	223	ret = platform_get_irq(pdev, 0);
	224	if (ret < 0) {
d28af35b	225	dev_err(dev, "No interrupt specified.\n");
ad7b550a	226	return ret;
c6ce2b6b CR	227	}
	228
	229	tb10x_gpio->gc.to_irq = tb10x_gpio_to_irq;
	230	tb10x_gpio->irq = ret;
	231
d28af35b	232	ret = devm_request_irq(dev, ret, tb10x_gpio_irq_cascade,
c6ce2b6b	233	IRQF_TRIGGER_NONE \| IRQF_SHARED,
d28af35b	234	dev_name(dev), tb10x_gpio);
c6ce2b6b	235	if (ret != 0)
ad7b550a	236	return ret;
c6ce2b6b	237
d28af35b	238	tb10x_gpio->domain = irq_domain_add_linear(np,
c6ce2b6b CR	239	tb10x_gpio->gc.ngpio,
	240	&irq_generic_chip_ops, NULL);
	241	if (!tb10x_gpio->domain) {
ad7b550a	242	return -ENOMEM;
c6ce2b6b CR	243	}
	244
	245	ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
	246	tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
	247	handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
	248	IRQ_GC_INIT_MASK_CACHE);
	249	if (ret)
ad7b550a	250	return ret;
c6ce2b6b CR	251
	252	gc = tb10x_gpio->domain->gc->gc[0];
	253	gc->reg_base = tb10x_gpio->base;
	254	gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
	255	gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
	256	gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
	257	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
	258	gc->chip_types[0].chip.irq_set_type = tb10x_gpio_irq_set_type;
	259	gc->chip_types[0].regs.ack = OFFSET_TO_REG_CHANGE;
	260	gc->chip_types[0].regs.mask = OFFSET_TO_REG_INT_EN;
	261	}
	262
	263	return 0;
c6ce2b6b CR	264	}
c6ce2b6b CR	265
b8a51a2e	266	static int tb10x_gpio_remove(struct platform_device *pdev)
c6ce2b6b CR	267	{
c6ce2b6b CR	268	struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
c6ce2b6b CR	269
	270	if (tb10x_gpio->gc.to_irq) {
	271	irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
	272	BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
	273	kfree(tb10x_gpio->domain->gc);
	274	irq_domain_remove(tb10x_gpio->domain);
c6ce2b6b	275	}
c6ce2b6b CR	276
	277	return 0;
	278	}
	279
	280	static const struct of_device_id tb10x_gpio_dt_ids[] = {
	281	{ .compatible = "abilis,tb10x-gpio" },
	282	{ }
	283	};
	284	MODULE_DEVICE_TABLE(of, tb10x_gpio_dt_ids);
	285
	286	static struct platform_driver tb10x_gpio_driver = {
	287	.probe = tb10x_gpio_probe,
	288	.remove = tb10x_gpio_remove,
	289	.driver = {
	290	.name = "tb10x-gpio",
b10b45c0	291	.of_match_table = tb10x_gpio_dt_ids,
c6ce2b6b CR	292	}
	293	};
	294
85aa3915	295	module_platform_driver(tb10x_gpio_driver);
c6ce2b6b CR	296	MODULE_LICENSE("GPL");
	297	MODULE_DESCRIPTION("tb10x gpio.");
	298	MODULE_VERSION("0.0.1");