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d2c19e89 P |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * Intel Tangier GPIO driver | |
4 | * | |
5 | * Copyright (c) 2016, 2021, 2023 Intel Corporation. | |
6 | * | |
7 | * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> | |
8 | * Pandith N <pandith.n@intel.com> | |
9 | * Raag Jadav <raag.jadav@intel.com> | |
10 | */ | |
11 | ||
12 | #include <linux/bitops.h> | |
92fc925f | 13 | #include <linux/cleanup.h> |
d2c19e89 P |
14 | #include <linux/device.h> |
15 | #include <linux/errno.h> | |
16 | #include <linux/export.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/io.h> | |
19 | #include <linux/irq.h> | |
3b8d8ccc | 20 | #include <linux/math.h> |
d2c19e89 P |
21 | #include <linux/module.h> |
22 | #include <linux/pinctrl/pinconf-generic.h> | |
fc84abc4 | 23 | #include <linux/pm.h> |
d2c19e89 P |
24 | #include <linux/spinlock.h> |
25 | #include <linux/string_helpers.h> | |
26 | #include <linux/types.h> | |
27 | ||
28 | #include <linux/gpio/driver.h> | |
29 | ||
30 | #include "gpio-tangier.h" | |
31 | ||
32 | #define GCCR 0x000 /* Controller configuration */ | |
33 | #define GPLR 0x004 /* Pin level r/o */ | |
34 | #define GPDR 0x01c /* Pin direction */ | |
35 | #define GPSR 0x034 /* Pin set w/o */ | |
36 | #define GPCR 0x04c /* Pin clear w/o */ | |
37 | #define GRER 0x064 /* Rising edge detect */ | |
38 | #define GFER 0x07c /* Falling edge detect */ | |
39 | #define GFBR 0x094 /* Glitch filter bypass */ | |
40 | #define GIMR 0x0ac /* Interrupt mask */ | |
41 | #define GISR 0x0c4 /* Interrupt source */ | |
42 | #define GITR 0x300 /* Input type */ | |
43 | #define GLPR 0x318 /* Level input polarity */ | |
44 | ||
45 | /** | |
46 | * struct tng_gpio_context - Context to be saved during suspend-resume | |
47 | * @level: Pin level | |
48 | * @gpdr: Pin direction | |
49 | * @grer: Rising edge detect enable | |
50 | * @gfer: Falling edge detect enable | |
51 | * @gimr: Interrupt mask | |
52 | * @gwmr: Wake mask | |
53 | */ | |
54 | struct tng_gpio_context { | |
55 | u32 level; | |
56 | u32 gpdr; | |
57 | u32 grer; | |
58 | u32 gfer; | |
59 | u32 gimr; | |
60 | u32 gwmr; | |
61 | }; | |
62 | ||
63 | static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset, | |
64 | unsigned int reg) | |
65 | { | |
66 | struct tng_gpio *priv = gpiochip_get_data(chip); | |
67 | u8 reg_offset = offset / 32; | |
68 | ||
69 | return priv->reg_base + reg + reg_offset * 4; | |
70 | } | |
71 | ||
72 | static void __iomem *gpio_reg_and_bit(struct gpio_chip *chip, unsigned int offset, | |
73 | unsigned int reg, u8 *bit) | |
74 | { | |
75 | struct tng_gpio *priv = gpiochip_get_data(chip); | |
76 | u8 reg_offset = offset / 32; | |
77 | u8 shift = offset % 32; | |
78 | ||
79 | *bit = shift; | |
80 | return priv->reg_base + reg + reg_offset * 4; | |
81 | } | |
82 | ||
83 | static int tng_gpio_get(struct gpio_chip *chip, unsigned int offset) | |
84 | { | |
85 | void __iomem *gplr; | |
86 | u8 shift; | |
87 | ||
88 | gplr = gpio_reg_and_bit(chip, offset, GPLR, &shift); | |
89 | ||
90 | return !!(readl(gplr) & BIT(shift)); | |
91 | } | |
92 | ||
93 | static void tng_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) | |
94 | { | |
95 | struct tng_gpio *priv = gpiochip_get_data(chip); | |
d2c19e89 P |
96 | void __iomem *reg; |
97 | u8 shift; | |
98 | ||
99 | reg = gpio_reg_and_bit(chip, offset, value ? GPSR : GPCR, &shift); | |
100 | ||
92fc925f | 101 | guard(raw_spinlock_irqsave)(&priv->lock); |
d2c19e89 P |
102 | |
103 | writel(BIT(shift), reg); | |
d2c19e89 P |
104 | } |
105 | ||
106 | static int tng_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) | |
107 | { | |
108 | struct tng_gpio *priv = gpiochip_get_data(chip); | |
d2c19e89 P |
109 | void __iomem *gpdr; |
110 | u32 value; | |
111 | u8 shift; | |
112 | ||
113 | gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); | |
114 | ||
92fc925f | 115 | guard(raw_spinlock_irqsave)(&priv->lock); |
d2c19e89 P |
116 | |
117 | value = readl(gpdr); | |
118 | value &= ~BIT(shift); | |
119 | writel(value, gpdr); | |
120 | ||
d2c19e89 P |
121 | return 0; |
122 | } | |
123 | ||
124 | static int tng_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, | |
125 | int value) | |
126 | { | |
127 | struct tng_gpio *priv = gpiochip_get_data(chip); | |
d2c19e89 P |
128 | void __iomem *gpdr; |
129 | u8 shift; | |
130 | ||
131 | gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); | |
132 | tng_gpio_set(chip, offset, value); | |
133 | ||
92fc925f | 134 | guard(raw_spinlock_irqsave)(&priv->lock); |
d2c19e89 P |
135 | |
136 | value = readl(gpdr); | |
137 | value |= BIT(shift); | |
138 | writel(value, gpdr); | |
139 | ||
d2c19e89 P |
140 | return 0; |
141 | } | |
142 | ||
143 | static int tng_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) | |
144 | { | |
145 | void __iomem *gpdr; | |
146 | u8 shift; | |
147 | ||
148 | gpdr = gpio_reg_and_bit(chip, offset, GPDR, &shift); | |
149 | ||
150 | if (readl(gpdr) & BIT(shift)) | |
151 | return GPIO_LINE_DIRECTION_OUT; | |
152 | ||
153 | return GPIO_LINE_DIRECTION_IN; | |
154 | } | |
155 | ||
156 | static int tng_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, | |
157 | unsigned int debounce) | |
158 | { | |
159 | struct tng_gpio *priv = gpiochip_get_data(chip); | |
d2c19e89 P |
160 | void __iomem *gfbr; |
161 | u32 value; | |
162 | u8 shift; | |
163 | ||
164 | gfbr = gpio_reg_and_bit(chip, offset, GFBR, &shift); | |
165 | ||
92fc925f | 166 | guard(raw_spinlock_irqsave)(&priv->lock); |
d2c19e89 P |
167 | |
168 | value = readl(gfbr); | |
169 | if (debounce) | |
170 | value &= ~BIT(shift); | |
171 | else | |
172 | value |= BIT(shift); | |
173 | writel(value, gfbr); | |
174 | ||
d2c19e89 P |
175 | return 0; |
176 | } | |
177 | ||
178 | static int tng_gpio_set_config(struct gpio_chip *chip, unsigned int offset, | |
179 | unsigned long config) | |
180 | { | |
181 | u32 debounce; | |
182 | ||
183 | switch (pinconf_to_config_param(config)) { | |
184 | case PIN_CONFIG_BIAS_DISABLE: | |
185 | case PIN_CONFIG_BIAS_PULL_UP: | |
186 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
187 | return gpiochip_generic_config(chip, offset, config); | |
188 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
189 | debounce = pinconf_to_config_argument(config); | |
190 | return tng_gpio_set_debounce(chip, offset, debounce); | |
191 | default: | |
192 | return -ENOTSUPP; | |
193 | } | |
194 | } | |
195 | ||
196 | static void tng_irq_ack(struct irq_data *d) | |
197 | { | |
198 | struct tng_gpio *priv = irq_data_get_irq_chip_data(d); | |
199 | irq_hw_number_t gpio = irqd_to_hwirq(d); | |
d2c19e89 P |
200 | void __iomem *gisr; |
201 | u8 shift; | |
202 | ||
203 | gisr = gpio_reg_and_bit(&priv->chip, gpio, GISR, &shift); | |
204 | ||
92fc925f RJ |
205 | guard(raw_spinlock_irqsave)(&priv->lock); |
206 | ||
d2c19e89 | 207 | writel(BIT(shift), gisr); |
d2c19e89 P |
208 | } |
209 | ||
210 | static void tng_irq_unmask_mask(struct tng_gpio *priv, u32 gpio, bool unmask) | |
211 | { | |
d2c19e89 P |
212 | void __iomem *gimr; |
213 | u32 value; | |
214 | u8 shift; | |
215 | ||
216 | gimr = gpio_reg_and_bit(&priv->chip, gpio, GIMR, &shift); | |
217 | ||
92fc925f | 218 | guard(raw_spinlock_irqsave)(&priv->lock); |
d2c19e89 P |
219 | |
220 | value = readl(gimr); | |
221 | if (unmask) | |
222 | value |= BIT(shift); | |
223 | else | |
224 | value &= ~BIT(shift); | |
225 | writel(value, gimr); | |
d2c19e89 P |
226 | } |
227 | ||
228 | static void tng_irq_mask(struct irq_data *d) | |
229 | { | |
230 | struct tng_gpio *priv = irq_data_get_irq_chip_data(d); | |
231 | irq_hw_number_t gpio = irqd_to_hwirq(d); | |
232 | ||
233 | tng_irq_unmask_mask(priv, gpio, false); | |
234 | gpiochip_disable_irq(&priv->chip, gpio); | |
235 | } | |
236 | ||
237 | static void tng_irq_unmask(struct irq_data *d) | |
238 | { | |
239 | struct tng_gpio *priv = irq_data_get_irq_chip_data(d); | |
240 | irq_hw_number_t gpio = irqd_to_hwirq(d); | |
241 | ||
242 | gpiochip_enable_irq(&priv->chip, gpio); | |
243 | tng_irq_unmask_mask(priv, gpio, true); | |
244 | } | |
245 | ||
246 | static int tng_irq_set_type(struct irq_data *d, unsigned int type) | |
247 | { | |
248 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
249 | struct tng_gpio *priv = gpiochip_get_data(gc); | |
250 | irq_hw_number_t gpio = irqd_to_hwirq(d); | |
251 | void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); | |
252 | void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); | |
253 | void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR); | |
254 | void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR); | |
255 | u8 shift = gpio % 32; | |
d2c19e89 P |
256 | u32 value; |
257 | ||
92fc925f | 258 | guard(raw_spinlock_irqsave)(&priv->lock); |
d2c19e89 P |
259 | |
260 | value = readl(grer); | |
261 | if (type & IRQ_TYPE_EDGE_RISING) | |
262 | value |= BIT(shift); | |
263 | else | |
264 | value &= ~BIT(shift); | |
265 | writel(value, grer); | |
266 | ||
267 | value = readl(gfer); | |
268 | if (type & IRQ_TYPE_EDGE_FALLING) | |
269 | value |= BIT(shift); | |
270 | else | |
271 | value &= ~BIT(shift); | |
272 | writel(value, gfer); | |
273 | ||
274 | /* | |
275 | * To prevent glitches from triggering an unintended level interrupt, | |
276 | * configure GLPR register first and then configure GITR. | |
277 | */ | |
278 | value = readl(glpr); | |
279 | if (type & IRQ_TYPE_LEVEL_LOW) | |
280 | value |= BIT(shift); | |
281 | else | |
282 | value &= ~BIT(shift); | |
283 | writel(value, glpr); | |
284 | ||
285 | if (type & IRQ_TYPE_LEVEL_MASK) { | |
286 | value = readl(gitr); | |
287 | value |= BIT(shift); | |
288 | writel(value, gitr); | |
289 | ||
290 | irq_set_handler_locked(d, handle_level_irq); | |
291 | } else if (type & IRQ_TYPE_EDGE_BOTH) { | |
292 | value = readl(gitr); | |
293 | value &= ~BIT(shift); | |
294 | writel(value, gitr); | |
295 | ||
296 | irq_set_handler_locked(d, handle_edge_irq); | |
297 | } | |
298 | ||
d2c19e89 P |
299 | return 0; |
300 | } | |
301 | ||
302 | static int tng_irq_set_wake(struct irq_data *d, unsigned int on) | |
303 | { | |
304 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
305 | struct tng_gpio *priv = gpiochip_get_data(gc); | |
306 | irq_hw_number_t gpio = irqd_to_hwirq(d); | |
307 | void __iomem *gwmr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwmr); | |
308 | void __iomem *gwsr = gpio_reg(&priv->chip, gpio, priv->wake_regs.gwsr); | |
309 | u8 shift = gpio % 32; | |
d2c19e89 P |
310 | u32 value; |
311 | ||
92fc925f RJ |
312 | dev_dbg(priv->dev, "%s wake for gpio %lu\n", str_enable_disable(on), gpio); |
313 | ||
314 | guard(raw_spinlock_irqsave)(&priv->lock); | |
d2c19e89 P |
315 | |
316 | /* Clear the existing wake status */ | |
317 | writel(BIT(shift), gwsr); | |
318 | ||
319 | value = readl(gwmr); | |
320 | if (on) | |
321 | value |= BIT(shift); | |
322 | else | |
323 | value &= ~BIT(shift); | |
324 | writel(value, gwmr); | |
325 | ||
d2c19e89 P |
326 | return 0; |
327 | } | |
328 | ||
329 | static const struct irq_chip tng_irqchip = { | |
330 | .name = "gpio-tangier", | |
331 | .irq_ack = tng_irq_ack, | |
332 | .irq_mask = tng_irq_mask, | |
333 | .irq_unmask = tng_irq_unmask, | |
334 | .irq_set_type = tng_irq_set_type, | |
335 | .irq_set_wake = tng_irq_set_wake, | |
336 | .flags = IRQCHIP_IMMUTABLE, | |
337 | GPIOCHIP_IRQ_RESOURCE_HELPERS, | |
338 | }; | |
339 | ||
340 | static void tng_irq_handler(struct irq_desc *desc) | |
341 | { | |
342 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); | |
343 | struct tng_gpio *priv = gpiochip_get_data(gc); | |
344 | struct irq_chip *irqchip = irq_desc_get_chip(desc); | |
345 | unsigned long base, gpio; | |
346 | ||
347 | chained_irq_enter(irqchip, desc); | |
348 | ||
349 | /* Check GPIO controller to check which pin triggered the interrupt */ | |
350 | for (base = 0; base < priv->chip.ngpio; base += 32) { | |
351 | void __iomem *gisr = gpio_reg(&priv->chip, base, GISR); | |
352 | void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); | |
353 | unsigned long pending, enabled; | |
354 | ||
355 | pending = readl(gisr); | |
356 | enabled = readl(gimr); | |
357 | ||
358 | /* Only interrupts that are enabled */ | |
359 | pending &= enabled; | |
360 | ||
361 | for_each_set_bit(gpio, &pending, 32) | |
362 | generic_handle_domain_irq(gc->irq.domain, base + gpio); | |
363 | } | |
364 | ||
365 | chained_irq_exit(irqchip, desc); | |
366 | } | |
367 | ||
368 | static int tng_irq_init_hw(struct gpio_chip *chip) | |
369 | { | |
370 | struct tng_gpio *priv = gpiochip_get_data(chip); | |
371 | void __iomem *reg; | |
372 | unsigned int base; | |
373 | ||
374 | for (base = 0; base < priv->chip.ngpio; base += 32) { | |
375 | /* Clear the rising-edge detect register */ | |
376 | reg = gpio_reg(&priv->chip, base, GRER); | |
377 | writel(0, reg); | |
378 | ||
379 | /* Clear the falling-edge detect register */ | |
380 | reg = gpio_reg(&priv->chip, base, GFER); | |
381 | writel(0, reg); | |
382 | } | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
387 | static int tng_gpio_add_pin_ranges(struct gpio_chip *chip) | |
388 | { | |
389 | struct tng_gpio *priv = gpiochip_get_data(chip); | |
390 | const struct tng_gpio_pinrange *range; | |
391 | unsigned int i; | |
392 | int ret; | |
393 | ||
394 | for (i = 0; i < priv->pin_info.nranges; i++) { | |
395 | range = &priv->pin_info.pin_ranges[i]; | |
396 | ret = gpiochip_add_pin_range(&priv->chip, | |
397 | priv->pin_info.name, | |
398 | range->gpio_base, | |
399 | range->pin_base, | |
400 | range->npins); | |
401 | if (ret) { | |
402 | dev_err(priv->dev, "failed to add GPIO pin range\n"); | |
403 | return ret; | |
404 | } | |
405 | } | |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
410 | int devm_tng_gpio_probe(struct device *dev, struct tng_gpio *gpio) | |
411 | { | |
412 | const struct tng_gpio_info *info = &gpio->info; | |
3b8d8ccc | 413 | size_t nctx = DIV_ROUND_UP(info->ngpio, 32); |
d2c19e89 P |
414 | struct gpio_irq_chip *girq; |
415 | int ret; | |
416 | ||
3b8d8ccc | 417 | gpio->ctx = devm_kcalloc(dev, nctx, sizeof(*gpio->ctx), GFP_KERNEL); |
d2c19e89 P |
418 | if (!gpio->ctx) |
419 | return -ENOMEM; | |
420 | ||
421 | gpio->chip.label = dev_name(dev); | |
422 | gpio->chip.parent = dev; | |
423 | gpio->chip.request = gpiochip_generic_request; | |
424 | gpio->chip.free = gpiochip_generic_free; | |
425 | gpio->chip.direction_input = tng_gpio_direction_input; | |
426 | gpio->chip.direction_output = tng_gpio_direction_output; | |
427 | gpio->chip.get = tng_gpio_get; | |
428 | gpio->chip.set = tng_gpio_set; | |
429 | gpio->chip.get_direction = tng_gpio_get_direction; | |
430 | gpio->chip.set_config = tng_gpio_set_config; | |
431 | gpio->chip.base = info->base; | |
432 | gpio->chip.ngpio = info->ngpio; | |
433 | gpio->chip.can_sleep = false; | |
434 | gpio->chip.add_pin_ranges = tng_gpio_add_pin_ranges; | |
435 | ||
436 | raw_spin_lock_init(&gpio->lock); | |
437 | ||
438 | girq = &gpio->chip.irq; | |
439 | gpio_irq_chip_set_chip(girq, &tng_irqchip); | |
440 | girq->init_hw = tng_irq_init_hw; | |
441 | girq->parent_handler = tng_irq_handler; | |
442 | girq->num_parents = 1; | |
443 | girq->parents = devm_kcalloc(dev, girq->num_parents, | |
444 | sizeof(*girq->parents), GFP_KERNEL); | |
445 | if (!girq->parents) | |
446 | return -ENOMEM; | |
447 | ||
448 | girq->parents[0] = gpio->irq; | |
449 | girq->first = info->first; | |
450 | girq->default_type = IRQ_TYPE_NONE; | |
451 | girq->handler = handle_bad_irq; | |
452 | ||
453 | ret = devm_gpiochip_add_data(dev, &gpio->chip, gpio); | |
454 | if (ret) | |
455 | return dev_err_probe(dev, ret, "gpiochip_add error\n"); | |
456 | ||
457 | return 0; | |
458 | } | |
459 | EXPORT_SYMBOL_NS_GPL(devm_tng_gpio_probe, GPIO_TANGIER); | |
460 | ||
c4a79ae2 | 461 | static int tng_gpio_suspend(struct device *dev) |
d2c19e89 P |
462 | { |
463 | struct tng_gpio *priv = dev_get_drvdata(dev); | |
464 | struct tng_gpio_context *ctx = priv->ctx; | |
d2c19e89 P |
465 | unsigned int base; |
466 | ||
92fc925f | 467 | guard(raw_spinlock_irqsave)(&priv->lock); |
d2c19e89 P |
468 | |
469 | for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) { | |
470 | /* GPLR is RO, values read will be restored using GPSR */ | |
471 | ctx->level = readl(gpio_reg(&priv->chip, base, GPLR)); | |
472 | ||
473 | ctx->gpdr = readl(gpio_reg(&priv->chip, base, GPDR)); | |
474 | ctx->grer = readl(gpio_reg(&priv->chip, base, GRER)); | |
475 | ctx->gfer = readl(gpio_reg(&priv->chip, base, GFER)); | |
476 | ctx->gimr = readl(gpio_reg(&priv->chip, base, GIMR)); | |
477 | ||
478 | ctx->gwmr = readl(gpio_reg(&priv->chip, base, priv->wake_regs.gwmr)); | |
479 | } | |
480 | ||
d2c19e89 P |
481 | return 0; |
482 | } | |
d2c19e89 | 483 | |
c4a79ae2 | 484 | static int tng_gpio_resume(struct device *dev) |
d2c19e89 P |
485 | { |
486 | struct tng_gpio *priv = dev_get_drvdata(dev); | |
487 | struct tng_gpio_context *ctx = priv->ctx; | |
d2c19e89 P |
488 | unsigned int base; |
489 | ||
92fc925f | 490 | guard(raw_spinlock_irqsave)(&priv->lock); |
d2c19e89 P |
491 | |
492 | for (base = 0; base < priv->chip.ngpio; base += 32, ctx++) { | |
493 | /* GPLR is RO, values read will be restored using GPSR */ | |
494 | writel(ctx->level, gpio_reg(&priv->chip, base, GPSR)); | |
495 | ||
496 | writel(ctx->gpdr, gpio_reg(&priv->chip, base, GPDR)); | |
497 | writel(ctx->grer, gpio_reg(&priv->chip, base, GRER)); | |
498 | writel(ctx->gfer, gpio_reg(&priv->chip, base, GFER)); | |
499 | writel(ctx->gimr, gpio_reg(&priv->chip, base, GIMR)); | |
500 | ||
501 | writel(ctx->gwmr, gpio_reg(&priv->chip, base, priv->wake_regs.gwmr)); | |
502 | } | |
503 | ||
d2c19e89 P |
504 | return 0; |
505 | } | |
d2c19e89 | 506 | |
fc84abc4 RJ |
507 | EXPORT_NS_GPL_SIMPLE_DEV_PM_OPS(tng_gpio_pm_ops, tng_gpio_suspend, tng_gpio_resume, GPIO_TANGIER); |
508 | ||
d2c19e89 P |
509 | MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); |
510 | MODULE_AUTHOR("Pandith N <pandith.n@intel.com>"); | |
511 | MODULE_AUTHOR("Raag Jadav <raag.jadav@intel.com>"); | |
512 | MODULE_DESCRIPTION("Intel Tangier GPIO driver"); | |
513 | MODULE_LICENSE("GPL"); |