[linux-block.git] / drivers / gpio / gpio-syscon.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  SYSCON GPIO driver
 *
 *  Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
 */

#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>

#define GPIO_SYSCON_FEAT_IN	BIT(0)
#define GPIO_SYSCON_FEAT_OUT	BIT(1)
#define GPIO_SYSCON_FEAT_DIR	BIT(2)

/* SYSCON driver is designed to use 32-bit wide registers */
#define SYSCON_REG_SIZE		(4)
#define SYSCON_REG_BITS		(SYSCON_REG_SIZE * 8)

/**
 * struct syscon_gpio_data - Configuration for the device.
 * @compatible:		SYSCON driver compatible string.
 * @flags:		Set of GPIO_SYSCON_FEAT_ flags:
 *			GPIO_SYSCON_FEAT_IN:	GPIOs supports input,
 *			GPIO_SYSCON_FEAT_OUT:	GPIOs supports output,
 *			GPIO_SYSCON_FEAT_DIR:	GPIOs supports switch direction.
 * @bit_count:		Number of bits used as GPIOs.
 * @dat_bit_offset:	Offset (in bits) to the first GPIO bit.
 * @dir_bit_offset:	Optional offset (in bits) to the first bit to switch
 *			GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag).
 * @set:		HW specific callback to assigns output value
 *			for signal "offset"
 */

struct syscon_gpio_data {
	unsigned int	flags;
	unsigned int	bit_count;
	unsigned int	dat_bit_offset;
	unsigned int	dir_bit_offset;
	void		(*set)(struct gpio_chip *chip,
			       unsigned offset, int value);
};

struct syscon_gpio_priv {
	struct gpio_chip		chip;
	struct regmap			*syscon;
	const struct syscon_gpio_data	*data;
	u32				dreg_offset;
	u32				dir_reg_offset;
};

static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
	unsigned int val, offs;
	int ret;

	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;

	ret = regmap_read(priv->syscon,
			  (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val);
	if (ret)
		return ret;

	return !!(val & BIT(offs % SYSCON_REG_BITS));
}

static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
	unsigned int offs;

	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;

	regmap_update_bits(priv->syscon,
			   (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
			   BIT(offs % SYSCON_REG_BITS),
			   val ? BIT(offs % SYSCON_REG_BITS) : 0);
}

static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
{
	struct syscon_gpio_priv *priv = gpiochip_get_data(chip);

	if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
		unsigned int offs;

		offs = priv->dir_reg_offset +
		       priv->data->dir_bit_offset + offset;

		regmap_update_bits(priv->syscon,
				   (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
				   BIT(offs % SYSCON_REG_BITS), 0);
	}

	return 0;
}

static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val)
{
	struct syscon_gpio_priv *priv = gpiochip_get_data(chip);

	if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
		unsigned int offs;

		offs = priv->dir_reg_offset +
		       priv->data->dir_bit_offset + offset;

		regmap_update_bits(priv->syscon,
				   (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
				   BIT(offs % SYSCON_REG_BITS),
				   BIT(offs % SYSCON_REG_BITS));
	}

	chip->set(chip, offset, val);

	return 0;
}

static const struct syscon_gpio_data clps711x_mctrl_gpio = {
	/* ARM CLPS711X SYSFLG1 Bits 8-10 */
	.flags		= GPIO_SYSCON_FEAT_IN,
	.bit_count	= 3,
	.dat_bit_offset	= 0x40 * 8 + 8,
};

static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset,
			      int val)
{
	struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
	unsigned int offs;
	u8 bit;
	u32 data;
	int ret;

	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
	bit = offs % SYSCON_REG_BITS;
	data = (val ? BIT(bit) : 0) | BIT(bit + 16);
	ret = regmap_write(priv->syscon,
			   (offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
			   data);
	if (ret < 0)
		dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
}

static const struct syscon_gpio_data rockchip_rk3328_gpio_mute = {
	/* RK3328 GPIO_MUTE is an output only pin at GRF_SOC_CON10[1] */
	.flags		= GPIO_SYSCON_FEAT_OUT,
	.bit_count	= 1,
	.dat_bit_offset = 0x0428 * 8 + 1,
	.set		= rockchip_gpio_set,
};

#define KEYSTONE_LOCK_BIT BIT(0)

static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
	unsigned int offs;
	int ret;

	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;

	if (!val)
		return;

	ret = regmap_update_bits(
			priv->syscon,
			(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
			BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT,
			BIT(offs % SYSCON_REG_BITS) | KEYSTONE_LOCK_BIT);
	if (ret < 0)
		dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
}

static const struct syscon_gpio_data keystone_dsp_gpio = {
	/* ARM Keystone 2 */
	.flags		= GPIO_SYSCON_FEAT_OUT,
	.bit_count	= 28,
	.dat_bit_offset	= 4,
	.set		= keystone_gpio_set,
};

static const struct of_device_id syscon_gpio_ids[] = {
	{
		.compatible	= "cirrus,ep7209-mctrl-gpio",
		.data		= &clps711x_mctrl_gpio,
	},
	{
		.compatible	= "ti,keystone-dsp-gpio",
		.data		= &keystone_dsp_gpio,
	},
	{
		.compatible	= "rockchip,rk3328-grf-gpio",
		.data		= &rockchip_rk3328_gpio_mute,
	},
	{ }
};
MODULE_DEVICE_TABLE(of, syscon_gpio_ids);

static int syscon_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct syscon_gpio_priv *priv;
	struct device_node *np = dev->of_node;
	int ret;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->data = of_device_get_match_data(dev);

	priv->syscon = syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev");
	if (IS_ERR(priv->syscon) && np->parent)
		priv->syscon = syscon_node_to_regmap(np->parent);
	if (IS_ERR(priv->syscon))
		return PTR_ERR(priv->syscon);

	ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1,
					 &priv->dreg_offset);
	if (ret)
		dev_err(dev, "can't read the data register offset!\n");

	priv->dreg_offset <<= 3;

	ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2,
					 &priv->dir_reg_offset);
	if (ret)
		dev_dbg(dev, "can't read the dir register offset!\n");

	priv->dir_reg_offset <<= 3;

	priv->chip.parent = dev;
	priv->chip.owner = THIS_MODULE;
	priv->chip.label = dev_name(dev);
	priv->chip.base = -1;
	priv->chip.ngpio = priv->data->bit_count;
	priv->chip.get = syscon_gpio_get;
	if (priv->data->flags & GPIO_SYSCON_FEAT_IN)
		priv->chip.direction_input = syscon_gpio_dir_in;
	if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) {
		priv->chip.set = priv->data->set ? : syscon_gpio_set;
		priv->chip.direction_output = syscon_gpio_dir_out;
	}

	platform_set_drvdata(pdev, priv);

	return devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
}

static struct platform_driver syscon_gpio_driver = {
	.driver	= {
		.name		= "gpio-syscon",
		.of_match_table	= syscon_gpio_ids,
	},
	.probe	= syscon_gpio_probe,
};
module_platform_driver(syscon_gpio_driver);

MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
MODULE_DESCRIPTION("SYSCON GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
6a8a0c1d AS	2	/*
	3	* SYSCON GPIO driver
	4	*
	5	* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
6a8a0c1d AS	6	*/
	7
	8	#include <linux/err.h>
122d00f7	9	#include <linux/gpio/driver.h>
6a8a0c1d AS	10	#include <linux/module.h>
	11	#include <linux/of.h>
	12	#include <linux/of_device.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/regmap.h>
	15	#include <linux/mfd/syscon.h>
	16
	17	#define GPIO_SYSCON_FEAT_IN BIT(0)
	18	#define GPIO_SYSCON_FEAT_OUT BIT(1)
	19	#define GPIO_SYSCON_FEAT_DIR BIT(2)
	20
	21	/* SYSCON driver is designed to use 32-bit wide registers */
	22	#define SYSCON_REG_SIZE (4)
	23	#define SYSCON_REG_BITS (SYSCON_REG_SIZE * 8)
	24
	25	/**
	26	* struct syscon_gpio_data - Configuration for the device.
5f3beb67 LJ	27	* @compatible: SYSCON driver compatible string.
5f3beb67 LJ	28	* @flags: Set of GPIO_SYSCON_FEAT_ flags:
6a8a0c1d AS	29	* GPIO_SYSCON_FEAT_IN: GPIOs supports input,
	30	* GPIO_SYSCON_FEAT_OUT: GPIOs supports output,
	31	* GPIO_SYSCON_FEAT_DIR: GPIOs supports switch direction.
5f3beb67 LJ	32	* @bit_count: Number of bits used as GPIOs.
	33	* @dat_bit_offset: Offset (in bits) to the first GPIO bit.
	34	* @dir_bit_offset: Optional offset (in bits) to the first bit to switch
6a8a0c1d	35	* GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag).
5f3beb67	36	* @set: HW specific callback to assigns output value
2c341d62	37	* for signal "offset"
6a8a0c1d AS	38	*/
	39
	40	struct syscon_gpio_data {
6a8a0c1d AS	41	unsigned int flags;
	42	unsigned int bit_count;
	43	unsigned int dat_bit_offset;
	44	unsigned int dir_bit_offset;
2c341d62 GS	45	void (set)(struct gpio_chip chip,
2c341d62 GS	46	unsigned offset, int value);
6a8a0c1d AS	47	};
	48
	49	struct syscon_gpio_priv {
	50	struct gpio_chip chip;
	51	struct regmap *syscon;
	52	const struct syscon_gpio_data *data;
5a3e3f88 GS	53	u32 dreg_offset;
5a3e3f88 GS	54	u32 dir_reg_offset;
6a8a0c1d AS	55	};
6a8a0c1d AS	56
6a8a0c1d AS	57	static int syscon_gpio_get(struct gpio_chip *chip, unsigned offset)
6a8a0c1d AS	58	{
d27ad7a8	59	struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
5a3e3f88	60	unsigned int val, offs;
6a8a0c1d AS	61	int ret;
6a8a0c1d AS	62
5a3e3f88 GS	63	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
5a3e3f88 GS	64
6a8a0c1d AS	65	ret = regmap_read(priv->syscon,
	66	(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE, &val);
	67	if (ret)
	68	return ret;
	69
	70	return !!(val & BIT(offs % SYSCON_REG_BITS));
	71	}
	72
	73	static void syscon_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	74	{
d27ad7a8	75	struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
5a3e3f88 GS	76	unsigned int offs;
	77
	78	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
6a8a0c1d AS	79
	80	regmap_update_bits(priv->syscon,
	81	(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
	82	BIT(offs % SYSCON_REG_BITS),
	83	val ? BIT(offs % SYSCON_REG_BITS) : 0);
	84	}
	85
	86	static int syscon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
	87	{
d27ad7a8	88	struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
6a8a0c1d AS	89
6a8a0c1d AS	90	if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
5a3e3f88 GS	91	unsigned int offs;
	92
	93	offs = priv->dir_reg_offset +
	94	priv->data->dir_bit_offset + offset;
6a8a0c1d AS	95
	96	regmap_update_bits(priv->syscon,
	97	(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
	98	BIT(offs % SYSCON_REG_BITS), 0);
	99	}
	100
	101	return 0;
	102	}
	103
	104	static int syscon_gpio_dir_out(struct gpio_chip *chip, unsigned offset, int val)
	105	{
d27ad7a8	106	struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
6a8a0c1d AS	107
6a8a0c1d AS	108	if (priv->data->flags & GPIO_SYSCON_FEAT_DIR) {
5a3e3f88 GS	109	unsigned int offs;
	110
	111	offs = priv->dir_reg_offset +
	112	priv->data->dir_bit_offset + offset;
6a8a0c1d AS	113
	114	regmap_update_bits(priv->syscon,
	115	(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
	116	BIT(offs % SYSCON_REG_BITS),
	117	BIT(offs % SYSCON_REG_BITS));
	118	}
	119
70728c29	120	chip->set(chip, offset, val);
6a8a0c1d AS	121
	122	return 0;
	123	}
	124
	125	static const struct syscon_gpio_data clps711x_mctrl_gpio = {
	126	/* ARM CLPS711X SYSFLG1 Bits 8-10 */
6a8a0c1d AS	127	.flags = GPIO_SYSCON_FEAT_IN,
	128	.bit_count = 3,
	129	.dat_bit_offset = 0x40 * 8 + 8,
	130	};
	131
cf2ff877 LD	132	static void rockchip_gpio_set(struct gpio_chip *chip, unsigned int offset,
	133	int val)
	134	{
	135	struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
	136	unsigned int offs;
	137	u8 bit;
	138	u32 data;
	139	int ret;
	140
	141	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
	142	bit = offs % SYSCON_REG_BITS;
	143	data = (val ? BIT(bit) : 0) \| BIT(bit + 16);
	144	ret = regmap_write(priv->syscon,
	145	(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
	146	data);
	147	if (ret < 0)
	148	dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
	149	}
	150
	151	static const struct syscon_gpio_data rockchip_rk3328_gpio_mute = {
	152	/* RK3328 GPIO_MUTE is an output only pin at GRF_SOC_CON10[1] */
	153	.flags = GPIO_SYSCON_FEAT_OUT,
	154	.bit_count = 1,
	155	.dat_bit_offset = 0x0428 * 8 + 1,
	156	.set = rockchip_gpio_set,
	157	};
	158
2134cb99 GS	159	#define KEYSTONE_LOCK_BIT BIT(0)
	160
	161	static void keystone_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	162	{
d27ad7a8	163	struct syscon_gpio_priv *priv = gpiochip_get_data(chip);
2134cb99 GS	164	unsigned int offs;
	165	int ret;
	166
	167	offs = priv->dreg_offset + priv->data->dat_bit_offset + offset;
	168
	169	if (!val)
	170	return;
	171
	172	ret = regmap_update_bits(
	173	priv->syscon,
	174	(offs / SYSCON_REG_BITS) * SYSCON_REG_SIZE,
	175	BIT(offs % SYSCON_REG_BITS) \| KEYSTONE_LOCK_BIT,
	176	BIT(offs % SYSCON_REG_BITS) \| KEYSTONE_LOCK_BIT);
	177	if (ret < 0)
58383c78	178	dev_err(chip->parent, "gpio write failed ret(%d)\n", ret);
2134cb99 GS	179	}
	180
	181	static const struct syscon_gpio_data keystone_dsp_gpio = {
	182	/* ARM Keystone 2 */
2134cb99 GS	183	.flags = GPIO_SYSCON_FEAT_OUT,
	184	.bit_count = 28,
	185	.dat_bit_offset = 4,
	186	.set = keystone_gpio_set,
	187	};
	188
6a8a0c1d AS	189	static const struct of_device_id syscon_gpio_ids[] = {
6a8a0c1d AS	190	{
2e607fca	191	.compatible = "cirrus,ep7209-mctrl-gpio",
6a8a0c1d AS	192	.data = &clps711x_mctrl_gpio,
6a8a0c1d AS	193	},
2134cb99 GS	194	{
	195	.compatible = "ti,keystone-dsp-gpio",
	196	.data = &keystone_dsp_gpio,
	197	},
cf2ff877 LD	198	{
	199	.compatible = "rockchip,rk3328-grf-gpio",
	200	.data = &rockchip_rk3328_gpio_mute,
	201	},
6a8a0c1d AS	202	{ }
	203	};
	204	MODULE_DEVICE_TABLE(of, syscon_gpio_ids);
	205
	206	static int syscon_gpio_probe(struct platform_device *pdev)
	207	{
	208	struct device *dev = &pdev->dev;
6a8a0c1d	209	struct syscon_gpio_priv *priv;
5a3e3f88 GS	210	struct device_node *np = dev->of_node;
5a3e3f88 GS	211	int ret;
6a8a0c1d AS	212
	213	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	214	if (!priv)
	215	return -ENOMEM;
	216
edf874ef	217	priv->data = of_device_get_match_data(dev);
6a8a0c1d	218
2e9cf845 AS	219	priv->syscon = syscon_regmap_lookup_by_phandle(np, "gpio,syscon-dev");
	220	if (IS_ERR(priv->syscon) && np->parent)
	221	priv->syscon = syscon_node_to_regmap(np->parent);
	222	if (IS_ERR(priv->syscon))
	223	return PTR_ERR(priv->syscon);
	224
	225	ret = of_property_read_u32_index(np, "gpio,syscon-dev", 1,
	226	&priv->dreg_offset);
	227	if (ret)
	228	dev_err(dev, "can't read the data register offset!\n");
	229
	230	priv->dreg_offset <<= 3;
	231
	232	ret = of_property_read_u32_index(np, "gpio,syscon-dev", 2,
	233	&priv->dir_reg_offset);
	234	if (ret)
	235	dev_dbg(dev, "can't read the dir register offset!\n");
	236
	237	priv->dir_reg_offset <<= 3;
6a8a0c1d	238
58383c78	239	priv->chip.parent = dev;
6a8a0c1d AS	240	priv->chip.owner = THIS_MODULE;
	241	priv->chip.label = dev_name(dev);
	242	priv->chip.base = -1;
	243	priv->chip.ngpio = priv->data->bit_count;
	244	priv->chip.get = syscon_gpio_get;
	245	if (priv->data->flags & GPIO_SYSCON_FEAT_IN)
	246	priv->chip.direction_input = syscon_gpio_dir_in;
	247	if (priv->data->flags & GPIO_SYSCON_FEAT_OUT) {
2c341d62	248	priv->chip.set = priv->data->set ? : syscon_gpio_set;
6a8a0c1d AS	249	priv->chip.direction_output = syscon_gpio_dir_out;
	250	}
	251
	252	platform_set_drvdata(pdev, priv);
	253
94c683ab	254	return devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
6a8a0c1d AS	255	}
	256
	257	static struct platform_driver syscon_gpio_driver = {
	258	.driver = {
	259	.name = "gpio-syscon",
6a8a0c1d AS	260	.of_match_table = syscon_gpio_ids,
	261	},
	262	.probe = syscon_gpio_probe,
6a8a0c1d AS	263	};
	264	module_platform_driver(syscon_gpio_driver);
	265
	266	MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
	267	MODULE_DESCRIPTION("SYSCON GPIO driver");
	268	MODULE_LICENSE("GPL");