[linux-2.6-block.git] / drivers / gpio / gpio-stp-xway.c

/*
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License version 2 as published
 *  by the Free Software Foundation.
 *
 *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
 *
 */

#include <linux/slab.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/of_platform.h>
#include <linux/mutex.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/of_gpio.h>
#include <linux/clk.h>
#include <linux/err.h>

#include <lantiq_soc.h>

/*
 * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
 * peripheral controller used to drive external shift register cascades. At most
 * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
 * to drive the 2 LSBs of the cascade automatically.
 */

/* control register 0 */
#define XWAY_STP_CON0		0x00
/* control register 1 */
#define XWAY_STP_CON1		0x04
/* data register 0 */
#define XWAY_STP_CPU0		0x08
/* data register 1 */
#define XWAY_STP_CPU1		0x0C
/* access register */
#define XWAY_STP_AR		0x10

/* software or hardware update select bit */
#define XWAY_STP_CON_SWU	BIT(31)

/* automatic update rates */
#define XWAY_STP_2HZ		0
#define XWAY_STP_4HZ		BIT(23)
#define XWAY_STP_8HZ		BIT(24)
#define XWAY_STP_10HZ		(BIT(24) | BIT(23))
#define XWAY_STP_SPEED_MASK	(0xf << 23)

/* clock source for automatic update */
#define XWAY_STP_UPD_FPI	BIT(31)
#define XWAY_STP_UPD_MASK	(BIT(31) | BIT(30))

/* let the adsl core drive the 2 LSBs */
#define XWAY_STP_ADSL_SHIFT	24
#define XWAY_STP_ADSL_MASK	0x3

/* 2 groups of 3 bits can be driven by the phys */
#define XWAY_STP_PHY_MASK	0x7
#define XWAY_STP_PHY1_SHIFT	27
#define XWAY_STP_PHY2_SHIFT	15

/* STP has 3 groups of 8 bits */
#define XWAY_STP_GROUP0		BIT(0)
#define XWAY_STP_GROUP1		BIT(1)
#define XWAY_STP_GROUP2		BIT(2)
#define XWAY_STP_GROUP_MASK	(0x7)

/* Edge configuration bits */
#define XWAY_STP_FALLING	BIT(26)
#define XWAY_STP_EDGE_MASK	BIT(26)

#define xway_stp_r32(m, reg)		__raw_readl(m + reg)
#define xway_stp_w32(m, val, reg)	__raw_writel(val, m + reg)
#define xway_stp_w32_mask(m, clear, set, reg) \
		ltq_w32((ltq_r32(m + reg) & ~(clear)) | (set), \
		m + reg)

struct xway_stp {
	struct gpio_chip gc;
	void __iomem *virt;
	u32 edge;	/* rising or falling edge triggered shift register */
	u32 shadow;	/* shadow the shift registers state */
	u8 groups;	/* we can drive 1-3 groups of 8bit each */
	u8 dsl;		/* the 2 LSBs can be driven by the dsl core */
	u8 phy1;	/* 3 bits can be driven by phy1 */
	u8 phy2;	/* 3 bits can be driven by phy2 */
	u8 reserved;	/* mask out the hw driven bits in gpio_request */
};

/**
 * xway_stp_set() - gpio_chip->set - set gpios.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 * @val:    Value to be written to specified signal.
 *
 * Set the shadow value and call ltq_ebu_apply.
 */
static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
{
	struct xway_stp *chip =
		container_of(gc, struct xway_stp, gc);

	if (val)
		chip->shadow |= BIT(gpio);
	else
		chip->shadow &= ~BIT(gpio);
	xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
	xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
}

/**
 * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 * @val:    Value to be written to specified signal.
 *
 * Same as xway_stp_set, always returns 0.
 */
static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
{
	xway_stp_set(gc, gpio, val);

	return 0;
}

/**
 * xway_stp_request() - gpio_chip->request
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 *
 * We mask out the HW driven pins
 */
static int xway_stp_request(struct gpio_chip *gc, unsigned gpio)
{
	struct xway_stp *chip =
		container_of(gc, struct xway_stp, gc);

	if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
		dev_err(gc->dev, "GPIO %d is driven by hardware\n", gpio);
		return -ENODEV;
	}

	return 0;
}

/**
 * xway_stp_hw_init() - Configure the STP unit and enable the clock gate
 * @virt: pointer to the remapped register range
 */
static int xway_stp_hw_init(struct xway_stp *chip)
{
	/* sane defaults */
	xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
	xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
	xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);

	/* apply edge trigger settings for the shift register */
	xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
				chip->edge, XWAY_STP_CON0);

	/* apply led group settings */
	xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
				chip->groups, XWAY_STP_CON1);

	/* tell the hardware which pins are controlled by the dsl modem */
	xway_stp_w32_mask(chip->virt,
			XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT,
			chip->dsl << XWAY_STP_ADSL_SHIFT,
			XWAY_STP_CON0);

	/* tell the hardware which pins are controlled by the phys */
	xway_stp_w32_mask(chip->virt,
			XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT,
			chip->phy1 << XWAY_STP_PHY1_SHIFT,
			XWAY_STP_CON0);
	xway_stp_w32_mask(chip->virt,
			XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT,
			chip->phy2 << XWAY_STP_PHY2_SHIFT,
			XWAY_STP_CON1);

	/* mask out the hw driven bits in gpio_request */
	chip->reserved = (chip->phy2 << 5) | (chip->phy1 << 2) | chip->dsl;

	/*
	 * if we have pins that are driven by hw, we need to tell the stp what
	 * clock to use as a timer.
	 */
	if (chip->reserved)
		xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
			XWAY_STP_UPD_FPI, XWAY_STP_CON1);

	return 0;
}

static int xway_stp_probe(struct platform_device *pdev)
{
	struct resource *res;
	const __be32 *shadow, *groups, *dsl, *phy;
	struct xway_stp *chip;
	struct clk *clk;
	int ret = 0;

	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	chip->virt = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(chip->virt))
		return PTR_ERR(chip->virt);

	chip->gc.dev = &pdev->dev;
	chip->gc.label = "stp-xway";
	chip->gc.direction_output = xway_stp_dir_out;
	chip->gc.set = xway_stp_set;
	chip->gc.request = xway_stp_request;
	chip->gc.base = -1;
	chip->gc.owner = THIS_MODULE;

	/* store the shadow value if one was passed by the devicetree */
	shadow = of_get_property(pdev->dev.of_node, "lantiq,shadow", NULL);
	if (shadow)
		chip->shadow = be32_to_cpu(*shadow);

	/* find out which gpio groups should be enabled */
	groups = of_get_property(pdev->dev.of_node, "lantiq,groups", NULL);
	if (groups)
		chip->groups = be32_to_cpu(*groups) & XWAY_STP_GROUP_MASK;
	else
		chip->groups = XWAY_STP_GROUP0;
	chip->gc.ngpio = fls(chip->groups) * 8;

	/* find out which gpios are controlled by the dsl core */
	dsl = of_get_property(pdev->dev.of_node, "lantiq,dsl", NULL);
	if (dsl)
		chip->dsl = be32_to_cpu(*dsl) & XWAY_STP_ADSL_MASK;

	/* find out which gpios are controlled by the phys */
	if (of_machine_is_compatible("lantiq,ar9") ||
			of_machine_is_compatible("lantiq,gr9") ||
			of_machine_is_compatible("lantiq,vr9")) {
		phy = of_get_property(pdev->dev.of_node, "lantiq,phy1", NULL);
		if (phy)
			chip->phy1 = be32_to_cpu(*phy) & XWAY_STP_PHY_MASK;
		phy = of_get_property(pdev->dev.of_node, "lantiq,phy2", NULL);
		if (phy)
			chip->phy2 = be32_to_cpu(*phy) & XWAY_STP_PHY_MASK;
	}

	/* check which edge trigger we should use, default to a falling edge */
	if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))
		chip->edge = XWAY_STP_FALLING;

	clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "Failed to get clock\n");
		return PTR_ERR(clk);
	}
	clk_enable(clk);

	ret = xway_stp_hw_init(chip);
	if (!ret)
		ret = gpiochip_add(&chip->gc);

	if (!ret)
		dev_info(&pdev->dev, "Init done\n");

	return ret;
}

static const struct of_device_id xway_stp_match[] = {
	{ .compatible = "lantiq,gpio-stp-xway" },
	{},
};
MODULE_DEVICE_TABLE(of, xway_stp_match);

static struct platform_driver xway_stp_driver = {
	.probe = xway_stp_probe,
	.driver = {
		.name = "gpio-stp-xway",
		.of_match_table = xway_stp_match,
	},
};

static int __init xway_stp_init(void)
{
	return platform_driver_register(&xway_stp_driver);
}

subsys_initcall(xway_stp_init);
Commit	Line	Data
935c500c JC	1	/*
	2	* This program is free software; you can redistribute it and/or modify it
	3	* under the terms of the GNU General Public License version 2 as published
	4	* by the Free Software Foundation.
	5	*
54f30066	6	* Copyright (C) 2012 John Crispin <blogic@openwrt.org>
935c500c JC	7	*
	8	*/
	9
	10	#include <linux/slab.h>
	11	#include <linux/init.h>
54f30066	12	#include <linux/module.h>
935c500c	13	#include <linux/types.h>
54f30066	14	#include <linux/of_platform.h>
935c500c	15	#include <linux/mutex.h>
935c500c	16	#include <linux/gpio.h>
54f30066 JC	17	#include <linux/io.h>
	18	#include <linux/of_gpio.h>
	19	#include <linux/clk.h>
	20	#include <linux/err.h>
935c500c JC	21
	22	#include <lantiq_soc.h>
	23
54f30066 JC	24	/*
	25	* The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
	26	* peripheral controller used to drive external shift register cascades. At most
	27	* 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
	28	* to drive the 2 LSBs of the cascade automatically.
	29	*/
	30
	31	/* control register 0 */
	32	#define XWAY_STP_CON0 0x00
	33	/* control register 1 */
	34	#define XWAY_STP_CON1 0x04
	35	/* data register 0 */
	36	#define XWAY_STP_CPU0 0x08
	37	/* data register 1 */
	38	#define XWAY_STP_CPU1 0x0C
	39	/* access register */
	40	#define XWAY_STP_AR 0x10
	41
	42	/* software or hardware update select bit */
	43	#define XWAY_STP_CON_SWU BIT(31)
	44
	45	/* automatic update rates */
	46	#define XWAY_STP_2HZ 0
	47	#define XWAY_STP_4HZ BIT(23)
	48	#define XWAY_STP_8HZ BIT(24)
	49	#define XWAY_STP_10HZ (BIT(24) \| BIT(23))
	50	#define XWAY_STP_SPEED_MASK (0xf << 23)
	51
	52	/* clock source for automatic update */
	53	#define XWAY_STP_UPD_FPI BIT(31)
	54	#define XWAY_STP_UPD_MASK (BIT(31) \| BIT(30))
	55
	56	/* let the adsl core drive the 2 LSBs */
	57	#define XWAY_STP_ADSL_SHIFT 24
	58	#define XWAY_STP_ADSL_MASK 0x3
	59
	60	/* 2 groups of 3 bits can be driven by the phys */
08b085a0	61	#define XWAY_STP_PHY_MASK 0x7
54f30066 JC	62	#define XWAY_STP_PHY1_SHIFT 27
	63	#define XWAY_STP_PHY2_SHIFT 15
	64
	65	/* STP has 3 groups of 8 bits */
	66	#define XWAY_STP_GROUP0 BIT(0)
	67	#define XWAY_STP_GROUP1 BIT(1)
	68	#define XWAY_STP_GROUP2 BIT(2)
	69	#define XWAY_STP_GROUP_MASK (0x7)
	70
	71	/* Edge configuration bits */
	72	#define XWAY_STP_FALLING BIT(26)
	73	#define XWAY_STP_EDGE_MASK BIT(26)
	74
	75	#define xway_stp_r32(m, reg) __raw_readl(m + reg)
	76	#define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg)
	77	#define xway_stp_w32_mask(m, clear, set, reg) \
	78	ltq_w32((ltq_r32(m + reg) & ~(clear)) \| (set), \
	79	m + reg)
	80
	81	struct xway_stp {
	82	struct gpio_chip gc;
	83	void __iomem *virt;
	84	u32 edge; /* rising or falling edge triggered shift register */
c9e854cf	85	u32 shadow; /* shadow the shift registers state */
54f30066 JC	86	u8 groups; /* we can drive 1-3 groups of 8bit each */
	87	u8 dsl; /* the 2 LSBs can be driven by the dsl core */
	88	u8 phy1; /* 3 bits can be driven by phy1 */
	89	u8 phy2; /* 3 bits can be driven by phy2 */
	90	u8 reserved; /* mask out the hw driven bits in gpio_request */
	91	};
	92
	93	/**
	94	* xway_stp_set() - gpio_chip->set - set gpios.
	95	* @gc: Pointer to gpio_chip device structure.
	96	* @gpio: GPIO signal number.
	97	* @val: Value to be written to specified signal.
	98	*
	99	* Set the shadow value and call ltq_ebu_apply.
	100	*/
	101	static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
935c500c	102	{
54f30066 JC	103	struct xway_stp *chip =
	104	container_of(gc, struct xway_stp, gc);
	105
	106	if (val)
	107	chip->shadow \|= BIT(gpio);
935c500c	108	else
54f30066 JC	109	chip->shadow &= ~BIT(gpio);
	110	xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
	111	xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
935c500c JC	112	}
935c500c JC	113
54f30066 JC	114	/**
	115	* xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
	116	* @gc: Pointer to gpio_chip device structure.
	117	* @gpio: GPIO signal number.
	118	* @val: Value to be written to specified signal.
	119	*
	120	* Same as xway_stp_set, always returns 0.
	121	*/
	122	static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
935c500c	123	{
54f30066	124	xway_stp_set(gc, gpio, val);
935c500c JC	125
	126	return 0;
	127	}
	128
54f30066 JC	129	/**
	130	* xway_stp_request() - gpio_chip->request
	131	* @gc: Pointer to gpio_chip device structure.
	132	* @gpio: GPIO signal number.
	133	*
	134	* We mask out the HW driven pins
	135	*/
	136	static int xway_stp_request(struct gpio_chip *gc, unsigned gpio)
	137	{
	138	struct xway_stp *chip =
	139	container_of(gc, struct xway_stp, gc);
	140
	141	if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
	142	dev_err(gc->dev, "GPIO %d is driven by hardware\n", gpio);
	143	return -ENODEV;
	144	}
935c500c	145
54f30066 JC	146	return 0;
	147	}
	148
	149	/**
	150	* xway_stp_hw_init() - Configure the STP unit and enable the clock gate
	151	* @virt: pointer to the remapped register range
	152	*/
	153	static int xway_stp_hw_init(struct xway_stp *chip)
935c500c	154	{
935c500c	155	/* sane defaults */
54f30066 JC	156	xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
	157	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
	158	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
	159	xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
	160	xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);
935c500c	161
54f30066 JC	162	/* apply edge trigger settings for the shift register */
	163	xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
	164	chip->edge, XWAY_STP_CON0);
935c500c	165
54f30066 JC	166	/* apply led group settings */
	167	xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
	168	chip->groups, XWAY_STP_CON1);
935c500c	169
54f30066 JC	170	/* tell the hardware which pins are controlled by the dsl modem */
	171	xway_stp_w32_mask(chip->virt,
	172	XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT,
	173	chip->dsl << XWAY_STP_ADSL_SHIFT,
	174	XWAY_STP_CON0);
935c500c	175
54f30066 JC	176	/* tell the hardware which pins are controlled by the phys */
	177	xway_stp_w32_mask(chip->virt,
	178	XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT,
	179	chip->phy1 << XWAY_STP_PHY1_SHIFT,
	180	XWAY_STP_CON0);
	181	xway_stp_w32_mask(chip->virt,
	182	XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT,
	183	chip->phy2 << XWAY_STP_PHY2_SHIFT,
	184	XWAY_STP_CON1);
935c500c	185
54f30066 JC	186	/* mask out the hw driven bits in gpio_request */
	187	chip->reserved = (chip->phy2 << 5) \| (chip->phy1 << 2) \| chip->dsl;
	188
	189	/*
	190	* if we have pins that are driven by hw, we need to tell the stp what
	191	* clock to use as a timer.
935c500c	192	*/
54f30066 JC	193	if (chip->reserved)
	194	xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
	195	XWAY_STP_UPD_FPI, XWAY_STP_CON1);
935c500c	196
935c500c JC	197	return 0;
	198	}
	199
3836309d	200	static int xway_stp_probe(struct platform_device *pdev)
935c500c	201	{
d9b53c3c	202	struct resource *res;
54f30066 JC	203	const __be32 shadow, groups, dsl, phy;
	204	struct xway_stp *chip;
	205	struct clk *clk;
935c500c JC	206	int ret = 0;
935c500c JC	207
54f30066 JC	208	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	209	if (!chip)
	210	return -ENOMEM;
	211
d9b53c3c	212	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
641d0342 TR	213	chip->virt = devm_ioremap_resource(&pdev->dev, res);
	214	if (IS_ERR(chip->virt))
	215	return PTR_ERR(chip->virt);
8ab2a6d2	216
54f30066 JC	217	chip->gc.dev = &pdev->dev;
	218	chip->gc.label = "stp-xway";
	219	chip->gc.direction_output = xway_stp_dir_out;
	220	chip->gc.set = xway_stp_set;
	221	chip->gc.request = xway_stp_request;
	222	chip->gc.base = -1;
	223	chip->gc.owner = THIS_MODULE;
	224
	225	/* store the shadow value if one was passed by the devicetree */
	226	shadow = of_get_property(pdev->dev.of_node, "lantiq,shadow", NULL);
	227	if (shadow)
	228	chip->shadow = be32_to_cpu(*shadow);
	229
	230	/* find out which gpio groups should be enabled */
	231	groups = of_get_property(pdev->dev.of_node, "lantiq,groups", NULL);
	232	if (groups)
	233	chip->groups = be32_to_cpu(*groups) & XWAY_STP_GROUP_MASK;
	234	else
	235	chip->groups = XWAY_STP_GROUP0;
	236	chip->gc.ngpio = fls(chip->groups) * 8;
	237
	238	/* find out which gpios are controlled by the dsl core */
	239	dsl = of_get_property(pdev->dev.of_node, "lantiq,dsl", NULL);
	240	if (dsl)
	241	chip->dsl = be32_to_cpu(*dsl) & XWAY_STP_ADSL_MASK;
	242
	243	/* find out which gpios are controlled by the phys */
	244	if (of_machine_is_compatible("lantiq,ar9") \|\|
	245	of_machine_is_compatible("lantiq,gr9") \|\|
	246	of_machine_is_compatible("lantiq,vr9")) {
	247	phy = of_get_property(pdev->dev.of_node, "lantiq,phy1", NULL);
	248	if (phy)
	249	chip->phy1 = be32_to_cpu(*phy) & XWAY_STP_PHY_MASK;
	250	phy = of_get_property(pdev->dev.of_node, "lantiq,phy2", NULL);
	251	if (phy)
	252	chip->phy2 = be32_to_cpu(*phy) & XWAY_STP_PHY_MASK;
	253	}
	254
	255	/* check which edge trigger we should use, default to a falling edge */
	256	if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))
	257	chip->edge = XWAY_STP_FALLING;
	258
	259	clk = clk_get(&pdev->dev, NULL);
	260	if (IS_ERR(clk)) {
	261	dev_err(&pdev->dev, "Failed to get clock\n");
	262	return PTR_ERR(clk);
	263	}
	264	clk_enable(clk);
	265
	266	ret = xway_stp_hw_init(chip);
935c500c	267	if (!ret)
54f30066 JC	268	ret = gpiochip_add(&chip->gc);
	269
	270	if (!ret)
	271	dev_info(&pdev->dev, "Init done\n");
935c500c JC	272
	273	return ret;
	274	}
	275
54f30066 JC	276	static const struct of_device_id xway_stp_match[] = {
	277	{ .compatible = "lantiq,gpio-stp-xway" },
	278	{},
	279	};
	280	MODULE_DEVICE_TABLE(of, xway_stp_match);
	281
	282	static struct platform_driver xway_stp_driver = {
	283	.probe = xway_stp_probe,
935c500c	284	.driver = {
54f30066	285	.name = "gpio-stp-xway",
54f30066	286	.of_match_table = xway_stp_match,
935c500c JC	287	},
	288	};
	289
afdadc06	290	static int __init xway_stp_init(void)
935c500c	291	{
54f30066	292	return platform_driver_register(&xway_stp_driver);
935c500c JC	293	}
935c500c JC	294
54f30066	295	subsys_initcall(xway_stp_init);