[linux-2.6-block.git] / drivers / gpio / gpio-stp-xway.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 *
 *  Copyright (C) 2012 John Crispin <john@phrozen.org>
 */

#include <linux/slab.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/of_platform.h>
#include <linux/mutex.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>

/*
 * The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
 * peripheral controller used to drive external shift register cascades. At most
 * 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
 * to drive the 2 LSBs of the cascade automatically.
 */

/* control register 0 */
#define XWAY_STP_CON0		0x00
/* control register 1 */
#define XWAY_STP_CON1		0x04
/* data register 0 */
#define XWAY_STP_CPU0		0x08
/* data register 1 */
#define XWAY_STP_CPU1		0x0C
/* access register */
#define XWAY_STP_AR		0x10

/* software or hardware update select bit */
#define XWAY_STP_CON_SWU	BIT(31)

/* automatic update rates */
#define XWAY_STP_2HZ		0
#define XWAY_STP_4HZ		BIT(23)
#define XWAY_STP_8HZ		BIT(24)
#define XWAY_STP_10HZ		(BIT(24) | BIT(23))
#define XWAY_STP_SPEED_MASK	(0xf << 23)

/* clock source for automatic update */
#define XWAY_STP_UPD_FPI	BIT(31)
#define XWAY_STP_UPD_MASK	(BIT(31) | BIT(30))

/* let the adsl core drive the 2 LSBs */
#define XWAY_STP_ADSL_SHIFT	24
#define XWAY_STP_ADSL_MASK	0x3

/* 2 groups of 3 bits can be driven by the phys */
#define XWAY_STP_PHY_MASK	0x7
#define XWAY_STP_PHY1_SHIFT	27
#define XWAY_STP_PHY2_SHIFT	15

/* STP has 3 groups of 8 bits */
#define XWAY_STP_GROUP0		BIT(0)
#define XWAY_STP_GROUP1		BIT(1)
#define XWAY_STP_GROUP2		BIT(2)
#define XWAY_STP_GROUP_MASK	(0x7)

/* Edge configuration bits */
#define XWAY_STP_FALLING	BIT(26)
#define XWAY_STP_EDGE_MASK	BIT(26)

#define xway_stp_r32(m, reg)		__raw_readl(m + reg)
#define xway_stp_w32(m, val, reg)	__raw_writel(val, m + reg)
#define xway_stp_w32_mask(m, clear, set, reg) \
		xway_stp_w32(m, (xway_stp_r32(m, reg) & ~(clear)) | (set), reg)

struct xway_stp {
	struct gpio_chip gc;
	void __iomem *virt;
	u32 edge;	/* rising or falling edge triggered shift register */
	u32 shadow;	/* shadow the shift registers state */
	u8 groups;	/* we can drive 1-3 groups of 8bit each */
	u8 dsl;		/* the 2 LSBs can be driven by the dsl core */
	u8 phy1;	/* 3 bits can be driven by phy1 */
	u8 phy2;	/* 3 bits can be driven by phy2 */
	u8 reserved;	/* mask out the hw driven bits in gpio_request */
};

/**
 * xway_stp_get() - gpio_chip->get - get gpios.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 *
 * Gets the shadow value.
 */
static int xway_stp_get(struct gpio_chip *gc, unsigned int gpio)
{
	struct xway_stp *chip = gpiochip_get_data(gc);

	return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio));
}

/**
 * xway_stp_set() - gpio_chip->set - set gpios.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 * @val:    Value to be written to specified signal.
 *
 * Set the shadow value and call ltq_ebu_apply.
 */
static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
{
	struct xway_stp *chip = gpiochip_get_data(gc);

	if (val)
		chip->shadow |= BIT(gpio);
	else
		chip->shadow &= ~BIT(gpio);
	xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
	xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
}

/**
 * xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 * @val:    Value to be written to specified signal.
 *
 * Same as xway_stp_set, always returns 0.
 */
static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
{
	xway_stp_set(gc, gpio, val);

	return 0;
}

/**
 * xway_stp_request() - gpio_chip->request
 * @gc:     Pointer to gpio_chip device structure.
 * @gpio:   GPIO signal number.
 *
 * We mask out the HW driven pins
 */
static int xway_stp_request(struct gpio_chip *gc, unsigned gpio)
{
	struct xway_stp *chip = gpiochip_get_data(gc);

	if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
		dev_err(gc->parent, "GPIO %d is driven by hardware\n", gpio);
		return -ENODEV;
	}

	return 0;
}

/**
 * xway_stp_hw_init() - Configure the STP unit and enable the clock gate
 * @chip: Pointer to the xway_stp chip structure
 */
static void xway_stp_hw_init(struct xway_stp *chip)
{
	/* sane defaults */
	xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
	xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
	xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);

	/* apply edge trigger settings for the shift register */
	xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
				chip->edge, XWAY_STP_CON0);

	/* apply led group settings */
	xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
				chip->groups, XWAY_STP_CON1);

	/* tell the hardware which pins are controlled by the dsl modem */
	xway_stp_w32_mask(chip->virt,
			XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT,
			chip->dsl << XWAY_STP_ADSL_SHIFT,
			XWAY_STP_CON0);

	/* tell the hardware which pins are controlled by the phys */
	xway_stp_w32_mask(chip->virt,
			XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT,
			chip->phy1 << XWAY_STP_PHY1_SHIFT,
			XWAY_STP_CON0);
	xway_stp_w32_mask(chip->virt,
			XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT,
			chip->phy2 << XWAY_STP_PHY2_SHIFT,
			XWAY_STP_CON1);

	/* mask out the hw driven bits in gpio_request */
	chip->reserved = (chip->phy2 << 5) | (chip->phy1 << 2) | chip->dsl;

	/*
	 * if we have pins that are driven by hw, we need to tell the stp what
	 * clock to use as a timer.
	 */
	if (chip->reserved)
		xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
			XWAY_STP_UPD_FPI, XWAY_STP_CON1);
}

static int xway_stp_probe(struct platform_device *pdev)
{
	u32 shadow, groups, dsl, phy;
	struct xway_stp *chip;
	struct clk *clk;
	int ret = 0;

	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;

	chip->virt = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(chip->virt))
		return PTR_ERR(chip->virt);

	chip->gc.parent = &pdev->dev;
	chip->gc.label = "stp-xway";
	chip->gc.direction_output = xway_stp_dir_out;
	chip->gc.get = xway_stp_get;
	chip->gc.set = xway_stp_set;
	chip->gc.request = xway_stp_request;
	chip->gc.base = -1;
	chip->gc.owner = THIS_MODULE;

	/* store the shadow value if one was passed by the devicetree */
	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow))
		chip->shadow = shadow;

	/* find out which gpio groups should be enabled */
	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,groups", &groups))
		chip->groups = groups & XWAY_STP_GROUP_MASK;
	else
		chip->groups = XWAY_STP_GROUP0;
	chip->gc.ngpio = fls(chip->groups) * 8;

	/* find out which gpios are controlled by the dsl core */
	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,dsl", &dsl))
		chip->dsl = dsl & XWAY_STP_ADSL_MASK;

	/* find out which gpios are controlled by the phys */
	if (of_machine_is_compatible("lantiq,ar9") ||
			of_machine_is_compatible("lantiq,gr9") ||
			of_machine_is_compatible("lantiq,vr9")) {
		if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy))
			chip->phy1 = phy & XWAY_STP_PHY_MASK;
		if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy))
			chip->phy2 = phy & XWAY_STP_PHY_MASK;
	}

	/* check which edge trigger we should use, default to a falling edge */
	if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))
		chip->edge = XWAY_STP_FALLING;

	clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "Failed to get clock\n");
		return PTR_ERR(clk);
	}

	ret = clk_prepare_enable(clk);
	if (ret)
		return ret;

	xway_stp_hw_init(chip);

	ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
	if (ret) {
		clk_disable_unprepare(clk);
		return ret;
	}

	dev_info(&pdev->dev, "Init done\n");

	return 0;
}

static const struct of_device_id xway_stp_match[] = {
	{ .compatible = "lantiq,gpio-stp-xway" },
	{},
};
MODULE_DEVICE_TABLE(of, xway_stp_match);

static struct platform_driver xway_stp_driver = {
	.probe = xway_stp_probe,
	.driver = {
		.name = "gpio-stp-xway",
		.of_match_table = xway_stp_match,
	},
};

static int __init xway_stp_init(void)
{
	return platform_driver_register(&xway_stp_driver);
}

subsys_initcall(xway_stp_init);
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
935c500c	2	/*
935c500c	3	*
baddc7ca	4	* Copyright (C) 2012 John Crispin <john@phrozen.org>
935c500c JC	5	*/
	6
	7	#include <linux/slab.h>
	8	#include <linux/init.h>
54f30066	9	#include <linux/module.h>
935c500c	10	#include <linux/types.h>
54f30066	11	#include <linux/of_platform.h>
935c500c	12	#include <linux/mutex.h>
97a48fcd	13	#include <linux/gpio/driver.h>
54f30066	14	#include <linux/io.h>
54f30066 JC	15	#include <linux/clk.h>
54f30066 JC	16	#include <linux/err.h>
935c500c	17
54f30066 JC	18	/*
	19	* The Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a
	20	* peripheral controller used to drive external shift register cascades. At most
	21	* 3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem
	22	* to drive the 2 LSBs of the cascade automatically.
	23	*/
	24
	25	/* control register 0 */
	26	#define XWAY_STP_CON0 0x00
	27	/* control register 1 */
	28	#define XWAY_STP_CON1 0x04
	29	/* data register 0 */
	30	#define XWAY_STP_CPU0 0x08
	31	/* data register 1 */
	32	#define XWAY_STP_CPU1 0x0C
	33	/* access register */
	34	#define XWAY_STP_AR 0x10
	35
	36	/* software or hardware update select bit */
	37	#define XWAY_STP_CON_SWU BIT(31)
	38
	39	/* automatic update rates */
	40	#define XWAY_STP_2HZ 0
	41	#define XWAY_STP_4HZ BIT(23)
	42	#define XWAY_STP_8HZ BIT(24)
	43	#define XWAY_STP_10HZ (BIT(24) \| BIT(23))
	44	#define XWAY_STP_SPEED_MASK (0xf << 23)
	45
	46	/* clock source for automatic update */
	47	#define XWAY_STP_UPD_FPI BIT(31)
	48	#define XWAY_STP_UPD_MASK (BIT(31) \| BIT(30))
	49
	50	/* let the adsl core drive the 2 LSBs */
	51	#define XWAY_STP_ADSL_SHIFT 24
	52	#define XWAY_STP_ADSL_MASK 0x3
	53
	54	/* 2 groups of 3 bits can be driven by the phys */
08b085a0	55	#define XWAY_STP_PHY_MASK 0x7
54f30066 JC	56	#define XWAY_STP_PHY1_SHIFT 27
	57	#define XWAY_STP_PHY2_SHIFT 15
	58
	59	/* STP has 3 groups of 8 bits */
	60	#define XWAY_STP_GROUP0 BIT(0)
	61	#define XWAY_STP_GROUP1 BIT(1)
	62	#define XWAY_STP_GROUP2 BIT(2)
	63	#define XWAY_STP_GROUP_MASK (0x7)
	64
	65	/* Edge configuration bits */
	66	#define XWAY_STP_FALLING BIT(26)
	67	#define XWAY_STP_EDGE_MASK BIT(26)
	68
	69	#define xway_stp_r32(m, reg) __raw_readl(m + reg)
	70	#define xway_stp_w32(m, val, reg) __raw_writel(val, m + reg)
	71	#define xway_stp_w32_mask(m, clear, set, reg) \
c0ec7012	72	xway_stp_w32(m, (xway_stp_r32(m, reg) & ~(clear)) \| (set), reg)
54f30066 JC	73
	74	struct xway_stp {
	75	struct gpio_chip gc;
	76	void __iomem *virt;
	77	u32 edge; /* rising or falling edge triggered shift register */
c9e854cf	78	u32 shadow; /* shadow the shift registers state */
54f30066 JC	79	u8 groups; /* we can drive 1-3 groups of 8bit each */
	80	u8 dsl; /* the 2 LSBs can be driven by the dsl core */
	81	u8 phy1; /* 3 bits can be driven by phy1 */
	82	u8 phy2; /* 3 bits can be driven by phy2 */
	83	u8 reserved; /* mask out the hw driven bits in gpio_request */
	84	};
	85
5b9b2b52 MK	86	/**
	87	* xway_stp_get() - gpio_chip->get - get gpios.
	88	* @gc: Pointer to gpio_chip device structure.
	89	* @gpio: GPIO signal number.
	90	*
	91	* Gets the shadow value.
	92	*/
	93	static int xway_stp_get(struct gpio_chip *gc, unsigned int gpio)
	94	{
	95	struct xway_stp *chip = gpiochip_get_data(gc);
	96
	97	return (xway_stp_r32(chip->virt, XWAY_STP_CPU0) & BIT(gpio));
	98	}
	99
54f30066 JC	100	/**
	101	* xway_stp_set() - gpio_chip->set - set gpios.
	102	* @gc: Pointer to gpio_chip device structure.
	103	* @gpio: GPIO signal number.
	104	* @val: Value to be written to specified signal.
	105	*
	106	* Set the shadow value and call ltq_ebu_apply.
	107	*/
	108	static void xway_stp_set(struct gpio_chip *gc, unsigned gpio, int val)
935c500c	109	{
c63b30b0	110	struct xway_stp *chip = gpiochip_get_data(gc);
54f30066 JC	111
	112	if (val)
	113	chip->shadow \|= BIT(gpio);
935c500c	114	else
54f30066 JC	115	chip->shadow &= ~BIT(gpio);
	116	xway_stp_w32(chip->virt, chip->shadow, XWAY_STP_CPU0);
	117	xway_stp_w32_mask(chip->virt, 0, XWAY_STP_CON_SWU, XWAY_STP_CON0);
935c500c JC	118	}
935c500c JC	119
54f30066 JC	120	/**
	121	* xway_stp_dir_out() - gpio_chip->dir_out - set gpio direction.
	122	* @gc: Pointer to gpio_chip device structure.
	123	* @gpio: GPIO signal number.
	124	* @val: Value to be written to specified signal.
	125	*
	126	* Same as xway_stp_set, always returns 0.
	127	*/
	128	static int xway_stp_dir_out(struct gpio_chip *gc, unsigned gpio, int val)
935c500c	129	{
54f30066	130	xway_stp_set(gc, gpio, val);
935c500c JC	131
	132	return 0;
	133	}
	134
54f30066 JC	135	/**
	136	* xway_stp_request() - gpio_chip->request
	137	* @gc: Pointer to gpio_chip device structure.
	138	* @gpio: GPIO signal number.
	139	*
	140	* We mask out the HW driven pins
	141	*/
	142	static int xway_stp_request(struct gpio_chip *gc, unsigned gpio)
	143	{
c63b30b0	144	struct xway_stp *chip = gpiochip_get_data(gc);
54f30066 JC	145
54f30066 JC	146	if ((gpio < 8) && (chip->reserved & BIT(gpio))) {
58383c78	147	dev_err(gc->parent, "GPIO %d is driven by hardware\n", gpio);
54f30066 JC	148	return -ENODEV;
54f30066 JC	149	}
935c500c	150
54f30066 JC	151	return 0;
	152	}
	153
	154	/**
	155	* xway_stp_hw_init() - Configure the STP unit and enable the clock gate
8a7b1797	156	* @chip: Pointer to the xway_stp chip structure
54f30066	157	*/
8a7b1797	158	static void xway_stp_hw_init(struct xway_stp *chip)
935c500c	159	{
935c500c	160	/* sane defaults */
54f30066 JC	161	xway_stp_w32(chip->virt, 0, XWAY_STP_AR);
	162	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU0);
	163	xway_stp_w32(chip->virt, 0, XWAY_STP_CPU1);
	164	xway_stp_w32(chip->virt, XWAY_STP_CON_SWU, XWAY_STP_CON0);
	165	xway_stp_w32(chip->virt, 0, XWAY_STP_CON1);
935c500c	166
54f30066 JC	167	/* apply edge trigger settings for the shift register */
	168	xway_stp_w32_mask(chip->virt, XWAY_STP_EDGE_MASK,
	169	chip->edge, XWAY_STP_CON0);
935c500c	170
54f30066 JC	171	/* apply led group settings */
	172	xway_stp_w32_mask(chip->virt, XWAY_STP_GROUP_MASK,
	173	chip->groups, XWAY_STP_CON1);
935c500c	174
54f30066 JC	175	/* tell the hardware which pins are controlled by the dsl modem */
	176	xway_stp_w32_mask(chip->virt,
	177	XWAY_STP_ADSL_MASK << XWAY_STP_ADSL_SHIFT,
	178	chip->dsl << XWAY_STP_ADSL_SHIFT,
	179	XWAY_STP_CON0);
935c500c	180
54f30066 JC	181	/* tell the hardware which pins are controlled by the phys */
	182	xway_stp_w32_mask(chip->virt,
	183	XWAY_STP_PHY_MASK << XWAY_STP_PHY1_SHIFT,
	184	chip->phy1 << XWAY_STP_PHY1_SHIFT,
	185	XWAY_STP_CON0);
	186	xway_stp_w32_mask(chip->virt,
	187	XWAY_STP_PHY_MASK << XWAY_STP_PHY2_SHIFT,
	188	chip->phy2 << XWAY_STP_PHY2_SHIFT,
	189	XWAY_STP_CON1);
935c500c	190
54f30066 JC	191	/* mask out the hw driven bits in gpio_request */
	192	chip->reserved = (chip->phy2 << 5) \| (chip->phy1 << 2) \| chip->dsl;
	193
	194	/*
	195	* if we have pins that are driven by hw, we need to tell the stp what
	196	* clock to use as a timer.
935c500c	197	*/
54f30066 JC	198	if (chip->reserved)
	199	xway_stp_w32_mask(chip->virt, XWAY_STP_UPD_MASK,
	200	XWAY_STP_UPD_FPI, XWAY_STP_CON1);
935c500c JC	201	}
935c500c JC	202
3836309d	203	static int xway_stp_probe(struct platform_device *pdev)
935c500c	204	{
50f09073	205	u32 shadow, groups, dsl, phy;
54f30066 JC	206	struct xway_stp *chip;
54f30066 JC	207	struct clk *clk;
935c500c JC	208	int ret = 0;
935c500c JC	209
54f30066 JC	210	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	211	if (!chip)
	212	return -ENOMEM;
	213
6ba7c53b	214	chip->virt = devm_platform_ioremap_resource(pdev, 0);
641d0342 TR	215	if (IS_ERR(chip->virt))
641d0342 TR	216	return PTR_ERR(chip->virt);
8ab2a6d2	217
58383c78	218	chip->gc.parent = &pdev->dev;
54f30066 JC	219	chip->gc.label = "stp-xway";
54f30066 JC	220	chip->gc.direction_output = xway_stp_dir_out;
5b9b2b52	221	chip->gc.get = xway_stp_get;
54f30066 JC	222	chip->gc.set = xway_stp_set;
	223	chip->gc.request = xway_stp_request;
	224	chip->gc.base = -1;
	225	chip->gc.owner = THIS_MODULE;
	226
	227	/* store the shadow value if one was passed by the devicetree */
50f09073 MB	228	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,shadow", &shadow))
50f09073 MB	229	chip->shadow = shadow;
54f30066 JC	230
54f30066 JC	231	/* find out which gpio groups should be enabled */
50f09073 MB	232	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,groups", &groups))
50f09073 MB	233	chip->groups = groups & XWAY_STP_GROUP_MASK;
54f30066 JC	234	else
	235	chip->groups = XWAY_STP_GROUP0;
	236	chip->gc.ngpio = fls(chip->groups) * 8;
	237
	238	/* find out which gpios are controlled by the dsl core */
50f09073 MB	239	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,dsl", &dsl))
50f09073 MB	240	chip->dsl = dsl & XWAY_STP_ADSL_MASK;
54f30066 JC	241
	242	/* find out which gpios are controlled by the phys */
	243	if (of_machine_is_compatible("lantiq,ar9") \|\|
	244	of_machine_is_compatible("lantiq,gr9") \|\|
	245	of_machine_is_compatible("lantiq,vr9")) {
50f09073 MB	246	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy1", &phy))
	247	chip->phy1 = phy & XWAY_STP_PHY_MASK;
	248	if (!of_property_read_u32(pdev->dev.of_node, "lantiq,phy2", &phy))
	249	chip->phy2 = phy & XWAY_STP_PHY_MASK;
54f30066 JC	250	}
	251
	252	/* check which edge trigger we should use, default to a falling edge */
	253	if (!of_find_property(pdev->dev.of_node, "lantiq,rising", NULL))
	254	chip->edge = XWAY_STP_FALLING;
	255
bd791c48	256	clk = devm_clk_get(&pdev->dev, NULL);
54f30066 JC	257	if (IS_ERR(clk)) {
	258	dev_err(&pdev->dev, "Failed to get clock\n");
	259	return PTR_ERR(clk);
	260	}
54f30066	261
bd791c48 MB	262	ret = clk_prepare_enable(clk);
	263	if (ret)
	264	return ret;
54f30066	265
8a7b1797	266	xway_stp_hw_init(chip);
935c500c	267
8a7b1797	268	ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip);
bd791c48 MB	269	if (ret) {
bd791c48 MB	270	clk_disable_unprepare(clk);
8a7b1797	271	return ret;
bd791c48	272	}
935c500c	273
8a7b1797 MB	274	dev_info(&pdev->dev, "Init done\n");
	275
	276	return 0;
935c500c JC	277	}
935c500c JC	278
54f30066 JC	279	static const struct of_device_id xway_stp_match[] = {
	280	{ .compatible = "lantiq,gpio-stp-xway" },
	281	{},
	282	};
	283	MODULE_DEVICE_TABLE(of, xway_stp_match);
	284
	285	static struct platform_driver xway_stp_driver = {
	286	.probe = xway_stp_probe,
935c500c	287	.driver = {
54f30066	288	.name = "gpio-stp-xway",
54f30066	289	.of_match_table = xway_stp_match,
935c500c JC	290	},
	291	};
	292
afdadc06	293	static int __init xway_stp_init(void)
935c500c	294	{
54f30066	295	return platform_driver_register(&xway_stp_driver);
935c500c JC	296	}
935c500c JC	297
54f30066	298	subsys_initcall(xway_stp_init);