Merge tag 'pci-v6.16-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
[linux-block.git] / drivers / gpio / gpio-stmpe.c
CommitLineData
1f67b599 1// SPDX-License-Identifier: GPL-2.0-only
03f822f5
RV
2/*
3 * Copyright (C) ST-Ericsson SA 2010
4 *
03f822f5
RV
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
9f0127b9 8#include <linux/bitops.h>
f1b33ce4 9#include <linux/cleanup.h>
ecac6e60 10#include <linux/gpio/driver.h>
9f0127b9 11#include <linux/init.h>
03f822f5
RV
12#include <linux/interrupt.h>
13#include <linux/mfd/stmpe.h>
e6815a05 14#include <linux/property.h>
9f0127b9 15#include <linux/platform_device.h>
27ec8a9c 16#include <linux/seq_file.h>
9f0127b9 17#include <linux/slab.h>
de454ac4 18#include <linux/string_choices.h>
03f822f5
RV
19
20/*
21 * These registers are modified under the irq bus lock and cached to avoid
22 * unnecessary writes in bus_sync_unlock.
23 */
24enum { REG_RE, REG_FE, REG_IE };
25
43db289d
PC
26enum { LSB, CSB, MSB };
27
03f822f5 28#define CACHE_NR_REGS 3
9e9dc7d9
LW
29/* No variant has more than 24 GPIOs */
30#define CACHE_NR_BANKS (24 / 8)
03f822f5
RV
31
32struct stmpe_gpio {
33 struct gpio_chip chip;
34 struct stmpe *stmpe;
03f822f5 35 struct mutex irq_lock;
1dfb4a0d 36 u32 norequest_mask;
03f822f5
RV
37 /* Caches of interrupt control registers for bus_lock */
38 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
39 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
40};
41
03f822f5
RV
42static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
43{
b03c04a0 44 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5 45 struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d 46 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
4e2678b5 47 u8 mask = BIT(offset % 8);
03f822f5
RV
48 int ret;
49
50 ret = stmpe_reg_read(stmpe, reg);
51 if (ret < 0)
52 return ret;
53
7535b8be 54 return !!(ret & mask);
03f822f5
RV
55}
56
57static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
58{
b03c04a0 59 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5
RV
60 struct stmpe *stmpe = stmpe_gpio->stmpe;
61 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
43db289d 62 u8 reg = stmpe->regs[which + (offset / 8)];
4e2678b5 63 u8 mask = BIT(offset % 8);
03f822f5 64
cccdceb9
VK
65 /*
66 * Some variants have single register for gpio set/clear functionality.
67 * For them we need to write 0 to clear and 1 to set.
68 */
69 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
70 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
71 else
72 stmpe_reg_write(stmpe, reg, mask);
03f822f5
RV
73}
74
8e293fb0
LW
75static int stmpe_gpio_get_direction(struct gpio_chip *chip,
76 unsigned offset)
77{
78 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
79 struct stmpe *stmpe = stmpe_gpio->stmpe;
80 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
4e2678b5 81 u8 mask = BIT(offset % 8);
8e293fb0
LW
82 int ret;
83
84 ret = stmpe_reg_read(stmpe, reg);
85 if (ret < 0)
86 return ret;
87
e42615ec
MV
88 if (ret & mask)
89 return GPIO_LINE_DIRECTION_OUT;
90
91 return GPIO_LINE_DIRECTION_IN;
8e293fb0
LW
92}
93
03f822f5
RV
94static int stmpe_gpio_direction_output(struct gpio_chip *chip,
95 unsigned offset, int val)
96{
b03c04a0 97 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5 98 struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d 99 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
4e2678b5 100 u8 mask = BIT(offset % 8);
03f822f5
RV
101
102 stmpe_gpio_set(chip, offset, val);
103
104 return stmpe_set_bits(stmpe, reg, mask, mask);
105}
106
107static int stmpe_gpio_direction_input(struct gpio_chip *chip,
108 unsigned offset)
109{
b03c04a0 110 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5 111 struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d 112 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
4e2678b5 113 u8 mask = BIT(offset % 8);
03f822f5
RV
114
115 return stmpe_set_bits(stmpe, reg, mask, 0);
116}
117
03f822f5
RV
118static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
119{
b03c04a0 120 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5
RV
121 struct stmpe *stmpe = stmpe_gpio->stmpe;
122
4e2678b5 123 if (stmpe_gpio->norequest_mask & BIT(offset))
b8e9cf0b
WS
124 return -EINVAL;
125
4e2678b5 126 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
03f822f5
RV
127}
128
e35b5ab0 129static const struct gpio_chip template_chip = {
03f822f5
RV
130 .label = "stmpe",
131 .owner = THIS_MODULE,
8e293fb0 132 .get_direction = stmpe_gpio_get_direction,
03f822f5
RV
133 .direction_input = stmpe_gpio_direction_input,
134 .get = stmpe_gpio_get,
135 .direction_output = stmpe_gpio_direction_output,
136 .set = stmpe_gpio_set,
03f822f5 137 .request = stmpe_gpio_request,
9fb1f39e 138 .can_sleep = true,
03f822f5
RV
139};
140
2a866f39 141static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
03f822f5 142{
fe44e70d 143 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0 144 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
fc13d5a5 145 int offset = d->hwirq;
03f822f5 146 int regoffset = offset / 8;
4e2678b5 147 int mask = BIT(offset % 8);
03f822f5 148
1fe3bd9e 149 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
03f822f5
RV
150 return -EINVAL;
151
c6a05a05
PC
152 /* STMPE801 and STMPE 1600 don't have RE and FE registers */
153 if (stmpe_gpio->stmpe->partnum == STMPE801 ||
154 stmpe_gpio->stmpe->partnum == STMPE1600)
cccdceb9
VK
155 return 0;
156
1fe3bd9e 157 if (type & IRQ_TYPE_EDGE_RISING)
03f822f5
RV
158 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
159 else
160 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
161
1fe3bd9e 162 if (type & IRQ_TYPE_EDGE_FALLING)
03f822f5
RV
163 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
164 else
165 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
166
167 return 0;
168}
169
2a866f39 170static void stmpe_gpio_irq_lock(struct irq_data *d)
03f822f5 171{
fe44e70d 172 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0 173 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
03f822f5
RV
174
175 mutex_lock(&stmpe_gpio->irq_lock);
176}
177
2a866f39 178static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
03f822f5 179{
fe44e70d 180 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0 181 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
03f822f5
RV
182 struct stmpe *stmpe = stmpe_gpio->stmpe;
183 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
43db289d
PC
184 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
185 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
186 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
187 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
188 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
189 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
190 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
191 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
192 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
193 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
03f822f5 194 };
b9644fbf 195 int ret, i, j;
03f822f5 196
b888fb6f
PC
197 /*
198 * STMPE1600: to be able to get IRQ from pins,
199 * a read must be done on GPMR register, or a write in
200 * GPSR or GPCR registers
201 */
202 if (stmpe->partnum == STMPE1600) {
b9644fbf
WL
203 ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
204 if (ret < 0) {
205 dev_err(stmpe->dev, "Failed to read GPMR_LSB: %d\n", ret);
206 goto err;
207 }
208 ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
209 if (ret < 0) {
210 dev_err(stmpe->dev, "Failed to read GPMR_CSB: %d\n", ret);
211 goto err;
212 }
b888fb6f
PC
213 }
214
03f822f5 215 for (i = 0; i < CACHE_NR_REGS; i++) {
c6a05a05
PC
216 /* STMPE801 and STMPE1600 don't have RE and FE registers */
217 if ((stmpe->partnum == STMPE801 ||
218 stmpe->partnum == STMPE1600) &&
219 (i != REG_IE))
cccdceb9
VK
220 continue;
221
03f822f5
RV
222 for (j = 0; j < num_banks; j++) {
223 u8 old = stmpe_gpio->oldregs[i][j];
224 u8 new = stmpe_gpio->regs[i][j];
225
226 if (new == old)
227 continue;
228
229 stmpe_gpio->oldregs[i][j] = new;
43db289d 230 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
03f822f5
RV
231 }
232 }
233
b9644fbf 234err:
03f822f5
RV
235 mutex_unlock(&stmpe_gpio->irq_lock);
236}
237
2a866f39 238static void stmpe_gpio_irq_mask(struct irq_data *d)
03f822f5 239{
fe44e70d 240 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0 241 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
fc13d5a5 242 int offset = d->hwirq;
03f822f5 243 int regoffset = offset / 8;
4e2678b5 244 int mask = BIT(offset % 8);
03f822f5
RV
245
246 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
32585b56 247 gpiochip_disable_irq(gc, offset);
03f822f5
RV
248}
249
2a866f39 250static void stmpe_gpio_irq_unmask(struct irq_data *d)
03f822f5 251{
fe44e70d 252 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0 253 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
fc13d5a5 254 int offset = d->hwirq;
03f822f5 255 int regoffset = offset / 8;
4e2678b5 256 int mask = BIT(offset % 8);
03f822f5 257
32585b56 258 gpiochip_enable_irq(gc, offset);
03f822f5
RV
259 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
260}
261
27ec8a9c
LW
262static void stmpe_dbg_show_one(struct seq_file *s,
263 struct gpio_chip *gc,
264 unsigned offset, unsigned gpio)
265{
b03c04a0 266 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
27ec8a9c 267 struct stmpe *stmpe = stmpe_gpio->stmpe;
27ec8a9c 268 bool val = !!stmpe_gpio_get(gc, offset);
43db289d
PC
269 u8 bank = offset / 8;
270 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
4e2678b5 271 u8 mask = BIT(offset % 8);
27ec8a9c
LW
272 int ret;
273 u8 dir;
274
f1b33ce4
BG
275 char *label __free(kfree) = gpiochip_dup_line_label(gc, offset);
276 if (IS_ERR(label))
277 return;
278
27ec8a9c
LW
279 ret = stmpe_reg_read(stmpe, dir_reg);
280 if (ret < 0)
281 return;
282 dir = !!(ret & mask);
283
284 if (dir) {
285 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
de454ac4 286 gpio, label ?: "(none)", str_hi_lo(val));
27ec8a9c 287 } else {
287849cb
PC
288 u8 edge_det_reg;
289 u8 rise_reg;
290 u8 fall_reg;
291 u8 irqen_reg;
292
e2843cb6
CIK
293 static const char * const edge_det_values[] = {
294 "edge-inactive",
295 "edge-asserted",
296 "not-supported"
297 };
298 static const char * const rise_values[] = {
299 "no-rising-edge-detection",
300 "rising-edge-detection",
301 "not-supported"
302 };
303 static const char * const fall_values[] = {
304 "no-falling-edge-detection",
305 "falling-edge-detection",
306 "not-supported"
307 };
287849cb
PC
308 #define NOT_SUPPORTED_IDX 2
309 u8 edge_det = NOT_SUPPORTED_IDX;
310 u8 rise = NOT_SUPPORTED_IDX;
311 u8 fall = NOT_SUPPORTED_IDX;
27ec8a9c
LW
312 bool irqen;
313
287849cb
PC
314 switch (stmpe->partnum) {
315 case STMPE610:
316 case STMPE811:
317 case STMPE1601:
318 case STMPE2401:
319 case STMPE2403:
43db289d 320 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
287849cb
PC
321 ret = stmpe_reg_read(stmpe, edge_det_reg);
322 if (ret < 0)
323 return;
324 edge_det = !!(ret & mask);
df561f66 325 fallthrough;
287849cb 326 case STMPE1801:
43db289d
PC
327 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
328 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
329
287849cb
PC
330 ret = stmpe_reg_read(stmpe, rise_reg);
331 if (ret < 0)
332 return;
333 rise = !!(ret & mask);
334 ret = stmpe_reg_read(stmpe, fall_reg);
335 if (ret < 0)
336 return;
337 fall = !!(ret & mask);
df561f66 338 fallthrough;
287849cb 339 case STMPE801:
c6a05a05 340 case STMPE1600:
43db289d 341 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
287849cb
PC
342 break;
343
344 default:
27ec8a9c 345 return;
287849cb
PC
346 }
347
27ec8a9c
LW
348 ret = stmpe_reg_read(stmpe, irqen_reg);
349 if (ret < 0)
350 return;
351 irqen = !!(ret & mask);
352
287849cb 353 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
27ec8a9c 354 gpio, label ?: "(none)",
de454ac4 355 str_hi_lo(val),
287849cb
PC
356 edge_det_values[edge_det],
357 irqen ? "IRQ-enabled" : "IRQ-disabled",
358 rise_values[rise],
359 fall_values[fall]);
27ec8a9c
LW
360 }
361}
362
363static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
364{
365 unsigned i;
366 unsigned gpio = gc->base;
367
368 for (i = 0; i < gc->ngpio; i++, gpio++) {
369 stmpe_dbg_show_one(s, gc, i, gpio);
0d83a5eb 370 seq_putc(s, '\n');
27ec8a9c
LW
371 }
372}
373
32585b56 374static const struct irq_chip stmpe_gpio_irq_chip = {
03f822f5 375 .name = "stmpe-gpio",
2a866f39
LB
376 .irq_bus_lock = stmpe_gpio_irq_lock,
377 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
378 .irq_mask = stmpe_gpio_irq_mask,
379 .irq_unmask = stmpe_gpio_irq_unmask,
380 .irq_set_type = stmpe_gpio_irq_set_type,
32585b56
LW
381 .flags = IRQCHIP_IMMUTABLE,
382 GPIOCHIP_IRQ_RESOURCE_HELPERS,
03f822f5
RV
383};
384
97fe7bef
LA
385#define MAX_GPIOS 24
386
03f822f5
RV
387static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
388{
389 struct stmpe_gpio *stmpe_gpio = dev;
390 struct stmpe *stmpe = stmpe_gpio->stmpe;
c6a05a05 391 u8 statmsbreg;
03f822f5 392 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
97fe7bef 393 u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
03f822f5
RV
394 int ret;
395 int i;
396
c6a05a05
PC
397 /*
398 * the stmpe_block_read() call below, imposes to set statmsbreg
399 * with the register located at the lowest address. As STMPE1600
400 * variant is the only one which respect registers address's order
401 * (LSB regs located at lowest address than MSB ones) whereas all
402 * the others have a registers layout with MSB located before the
403 * LSB regs.
404 */
405 if (stmpe->partnum == STMPE1600)
406 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
407 else
408 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
409
03f822f5
RV
410 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
411 if (ret < 0)
412 return IRQ_NONE;
413
414 for (i = 0; i < num_banks; i++) {
c6a05a05
PC
415 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
416 num_banks - i - 1;
03f822f5
RV
417 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
418 unsigned int stat = status[i];
419
420 stat &= enabled;
421 if (!stat)
422 continue;
423
424 while (stat) {
425 int bit = __ffs(stat);
426 int line = bank * 8 + bit;
f0fbe7bc 427 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
ed05e204 428 line);
03f822f5 429
ed05e204 430 handle_nested_irq(child_irq);
4e2678b5 431 stat &= ~BIT(bit);
03f822f5
RV
432 }
433
6936e1f8
PC
434 /*
435 * interrupt status register write has no effect on
c6a05a05
PC
436 * 801/1801/1600, bits are cleared when read.
437 * Edge detect register is not present on 801/1600/1801
6936e1f8 438 */
d1ca19cb 439 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
c6a05a05 440 stmpe->partnum != STMPE1801) {
6936e1f8 441 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
43db289d 442 stmpe_reg_write(stmpe,
1516c635 443 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
43db289d 444 status[i]);
6936e1f8 445 }
03f822f5
RV
446 }
447
448 return IRQ_HANDLED;
449}
450
5fbe5b58
LW
451static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
452 unsigned long *valid_mask,
453 unsigned int ngpios)
454{
455 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
456 int i;
457
458 if (!stmpe_gpio->norequest_mask)
459 return;
460
461 /* Forbid unused lines to be mapped as IRQs */
462 for (i = 0; i < sizeof(u32); i++) {
463 if (stmpe_gpio->norequest_mask & BIT(i))
464 clear_bit(i, valid_mask);
465 }
466}
467
2a9a2cca
AA
468static void stmpe_gpio_disable(void *stmpe)
469{
470 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
471}
472
3836309d 473static int stmpe_gpio_probe(struct platform_device *pdev)
03f822f5 474{
a7943313 475 struct device *dev = &pdev->dev;
56f534dd 476 struct stmpe *stmpe = dev_get_drvdata(dev->parent);
03f822f5 477 struct stmpe_gpio *stmpe_gpio;
0f719231 478 int ret, irq;
03f822f5 479
97fe7bef 480 if (stmpe->num_gpios > MAX_GPIOS) {
56f534dd 481 dev_err(dev, "Need to increase maximum GPIO number\n");
97fe7bef
LA
482 return -EINVAL;
483 }
484
56f534dd 485 stmpe_gpio = devm_kzalloc(dev, sizeof(*stmpe_gpio), GFP_KERNEL);
03f822f5
RV
486 if (!stmpe_gpio)
487 return -ENOMEM;
488
489 mutex_init(&stmpe_gpio->irq_lock);
490
03f822f5 491 stmpe_gpio->stmpe = stmpe;
03f822f5
RV
492 stmpe_gpio->chip = template_chip;
493 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
56f534dd 494 stmpe_gpio->chip.parent = dev;
9e9dc7d9 495 stmpe_gpio->chip.base = -1;
03f822f5 496
27ec8a9c
LW
497 if (IS_ENABLED(CONFIG_DEBUG_FS))
498 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
499
e6815a05 500 device_property_read_u32(dev, "st,norequest-mask", &stmpe_gpio->norequest_mask);
86605cfe 501
03f822f5
RV
502 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
503 if (ret)
2a9a2cca
AA
504 return ret;
505
56f534dd 506 ret = devm_add_action_or_reset(dev, stmpe_gpio_disable, stmpe);
2a9a2cca
AA
507 if (ret)
508 return ret;
03f822f5 509
a7943313 510 irq = platform_get_irq(pdev, 0);
fe44e70d 511 if (irq > 0) {
97450796
LW
512 struct gpio_irq_chip *girq;
513
56f534dd
AS
514 ret = devm_request_threaded_irq(dev, irq, NULL, stmpe_gpio_irq,
515 IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
1882e769 516 if (ret)
a7943313 517 return dev_err_probe(dev, ret, "unable to register IRQ handler\n");
03f822f5 518
97450796 519 girq = &stmpe_gpio->chip.irq;
32585b56 520 gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip);
97450796
LW
521 /* This will let us handle the parent IRQ in the driver */
522 girq->parent_handler = NULL;
523 girq->num_parents = 0;
524 girq->parents = NULL;
525 girq->default_type = IRQ_TYPE_NONE;
526 girq->handler = handle_simple_irq;
527 girq->threaded = true;
8aa16335 528 girq->init_valid_mask = stmpe_init_irq_valid_mask;
03f822f5
RV
529 }
530
56f534dd 531 return devm_gpiochip_add_data(dev, &stmpe_gpio->chip, stmpe_gpio);
03f822f5
RV
532}
533
03f822f5 534static struct platform_driver stmpe_gpio_driver = {
3b52bb96
PG
535 .driver = {
536 .suppress_bind_attrs = true,
537 .name = "stmpe-gpio",
3b52bb96 538 },
03f822f5 539 .probe = stmpe_gpio_probe,
03f822f5
RV
540};
541
542static int __init stmpe_gpio_init(void)
543{
544 return platform_driver_register(&stmpe_gpio_driver);
545}
546subsys_initcall(stmpe_gpio_init);