[linux-block.git] / drivers / gpio / gpio-stmpe.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
 */

#include <linux/bitops.h>
#include <linux/cleanup.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/mfd/stmpe.h>
#include <linux/property.h>
#include <linux/platform_device.h>
#include <linux/seq_file.h>
#include <linux/slab.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_RE, REG_FE, REG_IE };

enum { LSB, CSB, MSB };

#define CACHE_NR_REGS	3
/* No variant has more than 24 GPIOs */
#define CACHE_NR_BANKS	(24 / 8)

struct stmpe_gpio {
	struct gpio_chip chip;
	struct stmpe *stmpe;
	struct mutex irq_lock;
	u32 norequest_mask;
	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
	u8 mask = BIT(offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	return !!(ret & mask);
}

static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	u8 reg = stmpe->regs[which + (offset / 8)];
	u8 mask = BIT(offset % 8);

	/*
	 * Some variants have single register for gpio set/clear functionality.
	 * For them we need to write 0 to clear and 1 to set.
	 */
	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
		stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	else
		stmpe_reg_write(stmpe, reg, mask);
}

static int stmpe_gpio_get_direction(struct gpio_chip *chip,
				    unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = BIT(offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	if (ret & mask)
		return GPIO_LINE_DIRECTION_OUT;

	return GPIO_LINE_DIRECTION_IN;
}

static int stmpe_gpio_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
	u8 mask = BIT(offset % 8);

	stmpe_gpio_set(chip, offset, val);

	return stmpe_set_bits(stmpe, reg, mask, mask);
}

static int stmpe_gpio_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
	u8 mask = BIT(offset % 8);

	return stmpe_set_bits(stmpe, reg, mask, 0);
}

static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;

	if (stmpe_gpio->norequest_mask & BIT(offset))
		return -EINVAL;

	return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
}

static const struct gpio_chip template_chip = {
	.label			= "stmpe",
	.owner			= THIS_MODULE,
	.get_direction		= stmpe_gpio_get_direction,
	.direction_input	= stmpe_gpio_direction_input,
	.get			= stmpe_gpio_get,
	.direction_output	= stmpe_gpio_direction_output,
	.set			= stmpe_gpio_set,
	.request		= stmpe_gpio_request,
	.can_sleep		= true,
};

static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
		return -EINVAL;

	/* STMPE801 and STMPE 1600 don't have RE and FE registers */
	if (stmpe_gpio->stmpe->partnum == STMPE801 ||
	    stmpe_gpio->stmpe->partnum == STMPE1600)
		return 0;

	if (type & IRQ_TYPE_EDGE_RISING)
		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;

	if (type & IRQ_TYPE_EDGE_FALLING)
		stmpe_gpio->regs[REG_FE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;

	return 0;
}

static void stmpe_gpio_irq_lock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);

	mutex_lock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
		[REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
		[REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
		[REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
		[REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
		[REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
		[REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
		[REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
		[REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
		[REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
	};
	int i, j;

	/*
	 * STMPE1600: to be able to get IRQ from pins,
	 * a read must be done on GPMR register, or a write in
	 * GPSR or GPCR registers
	 */
	if (stmpe->partnum == STMPE1600) {
		stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
		stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
	}

	for (i = 0; i < CACHE_NR_REGS; i++) {
		/* STMPE801 and STMPE1600 don't have RE and FE registers */
		if ((stmpe->partnum == STMPE801 ||
		     stmpe->partnum == STMPE1600) &&
		     (i != REG_IE))
			continue;

		for (j = 0; j < num_banks; j++) {
			u8 old = stmpe_gpio->oldregs[i][j];
			u8 new = stmpe_gpio->regs[i][j];

			if (new == old)
				continue;

			stmpe_gpio->oldregs[i][j] = new;
			stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
		}
	}

	mutex_unlock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
	gpiochip_disable_irq(gc, offset);
}

static void stmpe_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	gpiochip_enable_irq(gc, offset);
	stmpe_gpio->regs[REG_IE][regoffset] |= mask;
}

static void stmpe_dbg_show_one(struct seq_file *s,
			       struct gpio_chip *gc,
			       unsigned offset, unsigned gpio)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	bool val = !!stmpe_gpio_get(gc, offset);
	u8 bank = offset / 8;
	u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
	u8 mask = BIT(offset % 8);
	int ret;
	u8 dir;

	char *label __free(kfree) = gpiochip_dup_line_label(gc, offset);
	if (IS_ERR(label))
		return;

	ret = stmpe_reg_read(stmpe, dir_reg);
	if (ret < 0)
		return;
	dir = !!(ret & mask);

	if (dir) {
		seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
			   gpio, label ?: "(none)",
			   val ? "hi" : "lo");
	} else {
		u8 edge_det_reg;
		u8 rise_reg;
		u8 fall_reg;
		u8 irqen_reg;

		static const char * const edge_det_values[] = {
			"edge-inactive",
			"edge-asserted",
			"not-supported"
		};
		static const char * const rise_values[] = {
			"no-rising-edge-detection",
			"rising-edge-detection",
			"not-supported"
		};
		static const char * const fall_values[] = {
			"no-falling-edge-detection",
			"falling-edge-detection",
			"not-supported"
		};
		#define NOT_SUPPORTED_IDX 2
		u8 edge_det = NOT_SUPPORTED_IDX;
		u8 rise = NOT_SUPPORTED_IDX;
		u8 fall = NOT_SUPPORTED_IDX;
		bool irqen;

		switch (stmpe->partnum) {
		case STMPE610:
		case STMPE811:
		case STMPE1601:
		case STMPE2401:
		case STMPE2403:
			edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
			ret = stmpe_reg_read(stmpe, edge_det_reg);
			if (ret < 0)
				return;
			edge_det = !!(ret & mask);
			fallthrough;
		case STMPE1801:
			rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
			fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];

			ret = stmpe_reg_read(stmpe, rise_reg);
			if (ret < 0)
				return;
			rise = !!(ret & mask);
			ret = stmpe_reg_read(stmpe, fall_reg);
			if (ret < 0)
				return;
			fall = !!(ret & mask);
			fallthrough;
		case STMPE801:
		case STMPE1600:
			irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
			break;

		default:
			return;
		}

		ret = stmpe_reg_read(stmpe, irqen_reg);
		if (ret < 0)
			return;
		irqen = !!(ret & mask);

		seq_printf(s, " gpio-%-3d (%-20.20s) in  %s %13s %13s %25s %25s",
			   gpio, label ?: "(none)",
			   val ? "hi" : "lo",
			   edge_det_values[edge_det],
			   irqen ? "IRQ-enabled" : "IRQ-disabled",
			   rise_values[rise],
			   fall_values[fall]);
	}
}

static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
{
	unsigned i;
	unsigned gpio = gc->base;

	for (i = 0; i < gc->ngpio; i++, gpio++) {
		stmpe_dbg_show_one(s, gc, i, gpio);
		seq_putc(s, '\n');
	}
}

static const struct irq_chip stmpe_gpio_irq_chip = {
	.name			= "stmpe-gpio",
	.irq_bus_lock		= stmpe_gpio_irq_lock,
	.irq_bus_sync_unlock	= stmpe_gpio_irq_sync_unlock,
	.irq_mask		= stmpe_gpio_irq_mask,
	.irq_unmask		= stmpe_gpio_irq_unmask,
	.irq_set_type		= stmpe_gpio_irq_set_type,
	.flags			= IRQCHIP_IMMUTABLE,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

#define MAX_GPIOS 24

static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
{
	struct stmpe_gpio *stmpe_gpio = dev;
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 statmsbreg;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
	int ret;
	int i;

	/*
	 * the stmpe_block_read() call below, imposes to set statmsbreg
	 * with the register located at the lowest address. As STMPE1600
	 * variant is the only one which respect registers address's order
	 * (LSB regs located at lowest address than MSB ones) whereas all
	 * the others have a registers layout with MSB located before the
	 * LSB regs.
	 */
	if (stmpe->partnum == STMPE1600)
		statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
	else
		statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];

	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < num_banks; i++) {
		int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
			   num_banks - i - 1;
		unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
		unsigned int stat = status[i];

		stat &= enabled;
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = bank * 8 + bit;
			int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
							 line);

			handle_nested_irq(child_irq);
			stat &= ~BIT(bit);
		}

		/*
		 * interrupt status register write has no effect on
		 * 801/1801/1600, bits are cleared when read.
		 * Edge detect register is not present on 801/1600/1801
		 */
		if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
		    stmpe->partnum != STMPE1801) {
			stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
			stmpe_reg_write(stmpe,
					stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
					status[i]);
		}
	}

	return IRQ_HANDLED;
}

static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
				      unsigned long *valid_mask,
				      unsigned int ngpios)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int i;

	if (!stmpe_gpio->norequest_mask)
		return;

	/* Forbid unused lines to be mapped as IRQs */
	for (i = 0; i < sizeof(u32); i++) {
		if (stmpe_gpio->norequest_mask & BIT(i))
			clear_bit(i, valid_mask);
	}
}

static void stmpe_gpio_disable(void *stmpe)
{
	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
}

static int stmpe_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct stmpe *stmpe = dev_get_drvdata(dev->parent);
	struct stmpe_gpio *stmpe_gpio;
	int ret, irq;

	if (stmpe->num_gpios > MAX_GPIOS) {
		dev_err(dev, "Need to increase maximum GPIO number\n");
		return -EINVAL;
	}

	stmpe_gpio = devm_kzalloc(dev, sizeof(*stmpe_gpio), GFP_KERNEL);
	if (!stmpe_gpio)
		return -ENOMEM;

	mutex_init(&stmpe_gpio->irq_lock);

	stmpe_gpio->stmpe = stmpe;
	stmpe_gpio->chip = template_chip;
	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	stmpe_gpio->chip.parent = dev;
	stmpe_gpio->chip.base = -1;

	if (IS_ENABLED(CONFIG_DEBUG_FS))
                stmpe_gpio->chip.dbg_show = stmpe_dbg_show;

	device_property_read_u32(dev, "st,norequest-mask", &stmpe_gpio->norequest_mask);

	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	if (ret)
		return ret;

	ret = devm_add_action_or_reset(dev, stmpe_gpio_disable, stmpe);
	if (ret)
		return ret;

	irq = platform_get_irq(pdev, 0);
	if (irq > 0) {
		struct gpio_irq_chip *girq;

		ret = devm_request_threaded_irq(dev, irq, NULL, stmpe_gpio_irq,
						IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
		if (ret)
			return dev_err_probe(dev, ret, "unable to register IRQ handler\n");

		girq = &stmpe_gpio->chip.irq;
		gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip);
		/* This will let us handle the parent IRQ in the driver */
		girq->parent_handler = NULL;
		girq->num_parents = 0;
		girq->parents = NULL;
		girq->default_type = IRQ_TYPE_NONE;
		girq->handler = handle_simple_irq;
		girq->threaded = true;
		girq->init_valid_mask = stmpe_init_irq_valid_mask;
	}

	return devm_gpiochip_add_data(dev, &stmpe_gpio->chip, stmpe_gpio);
}

static struct platform_driver stmpe_gpio_driver = {
	.driver = {
		.suppress_bind_attrs	= true,
		.name			= "stmpe-gpio",
	},
	.probe		= stmpe_gpio_probe,
};

static int __init stmpe_gpio_init(void)
{
	return platform_driver_register(&stmpe_gpio_driver);
}
subsys_initcall(stmpe_gpio_init);
Commit	Line	Data
1f67b599	1	// SPDX-License-Identifier: GPL-2.0-only
03f822f5 RV	2	/*
	3	* Copyright (C) ST-Ericsson SA 2010
	4	*
03f822f5 RV	5	* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	6	*/
	7
9f0127b9	8	#include <linux/bitops.h>
f1b33ce4	9	#include <linux/cleanup.h>
ecac6e60	10	#include <linux/gpio/driver.h>
9f0127b9	11	#include <linux/init.h>
03f822f5 RV	12	#include <linux/interrupt.h>
03f822f5 RV	13	#include <linux/mfd/stmpe.h>
e6815a05	14	#include <linux/property.h>
9f0127b9	15	#include <linux/platform_device.h>
27ec8a9c	16	#include <linux/seq_file.h>
9f0127b9	17	#include <linux/slab.h>
03f822f5 RV	18
	19	/*
	20	* These registers are modified under the irq bus lock and cached to avoid
	21	* unnecessary writes in bus_sync_unlock.
	22	*/
	23	enum { REG_RE, REG_FE, REG_IE };
	24
43db289d PC	25	enum { LSB, CSB, MSB };
43db289d PC	26
03f822f5	27	#define CACHE_NR_REGS 3
9e9dc7d9 LW	28	/* No variant has more than 24 GPIOs */
9e9dc7d9 LW	29	#define CACHE_NR_BANKS (24 / 8)
03f822f5 RV	30
	31	struct stmpe_gpio {
	32	struct gpio_chip chip;
	33	struct stmpe *stmpe;
03f822f5	34	struct mutex irq_lock;
1dfb4a0d	35	u32 norequest_mask;
03f822f5 RV	36	/* Caches of interrupt control registers for bus_lock */
	37	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	38	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	39	};
	40
03f822f5 RV	41	static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
03f822f5 RV	42	{
b03c04a0	43	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5	44	struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d	45	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
4e2678b5	46	u8 mask = BIT(offset % 8);
03f822f5 RV	47	int ret;
	48
	49	ret = stmpe_reg_read(stmpe, reg);
	50	if (ret < 0)
	51	return ret;
	52
7535b8be	53	return !!(ret & mask);
03f822f5 RV	54	}
	55
	56	static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	57	{
b03c04a0	58	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5 RV	59	struct stmpe *stmpe = stmpe_gpio->stmpe;
03f822f5 RV	60	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
43db289d	61	u8 reg = stmpe->regs[which + (offset / 8)];
4e2678b5	62	u8 mask = BIT(offset % 8);
03f822f5	63
cccdceb9 VK	64	/*
	65	* Some variants have single register for gpio set/clear functionality.
	66	* For them we need to write 0 to clear and 1 to set.
	67	*/
	68	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
	69	stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	70	else
	71	stmpe_reg_write(stmpe, reg, mask);
03f822f5 RV	72	}
03f822f5 RV	73
8e293fb0 LW	74	static int stmpe_gpio_get_direction(struct gpio_chip *chip,
	75	unsigned offset)
	76	{
	77	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	78	struct stmpe *stmpe = stmpe_gpio->stmpe;
	79	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
4e2678b5	80	u8 mask = BIT(offset % 8);
8e293fb0 LW	81	int ret;
	82
	83	ret = stmpe_reg_read(stmpe, reg);
	84	if (ret < 0)
	85	return ret;
	86
e42615ec MV	87	if (ret & mask)
	88	return GPIO_LINE_DIRECTION_OUT;
	89
	90	return GPIO_LINE_DIRECTION_IN;
8e293fb0 LW	91	}
8e293fb0 LW	92
03f822f5 RV	93	static int stmpe_gpio_direction_output(struct gpio_chip *chip,
	94	unsigned offset, int val)
	95	{
b03c04a0	96	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5	97	struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d	98	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
4e2678b5	99	u8 mask = BIT(offset % 8);
03f822f5 RV	100
	101	stmpe_gpio_set(chip, offset, val);
	102
	103	return stmpe_set_bits(stmpe, reg, mask, mask);
	104	}
	105
	106	static int stmpe_gpio_direction_input(struct gpio_chip *chip,
	107	unsigned offset)
	108	{
b03c04a0	109	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5	110	struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d	111	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
4e2678b5	112	u8 mask = BIT(offset % 8);
03f822f5 RV	113
	114	return stmpe_set_bits(stmpe, reg, mask, 0);
	115	}
	116
03f822f5 RV	117	static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
03f822f5 RV	118	{
b03c04a0	119	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5 RV	120	struct stmpe *stmpe = stmpe_gpio->stmpe;
03f822f5 RV	121
4e2678b5	122	if (stmpe_gpio->norequest_mask & BIT(offset))
b8e9cf0b WS	123	return -EINVAL;
b8e9cf0b WS	124
4e2678b5	125	return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
03f822f5 RV	126	}
03f822f5 RV	127
e35b5ab0	128	static const struct gpio_chip template_chip = {
03f822f5 RV	129	.label = "stmpe",
03f822f5 RV	130	.owner = THIS_MODULE,
8e293fb0	131	.get_direction = stmpe_gpio_get_direction,
03f822f5 RV	132	.direction_input = stmpe_gpio_direction_input,
	133	.get = stmpe_gpio_get,
	134	.direction_output = stmpe_gpio_direction_output,
	135	.set = stmpe_gpio_set,
03f822f5	136	.request = stmpe_gpio_request,
9fb1f39e	137	.can_sleep = true,
03f822f5 RV	138	};
03f822f5 RV	139
2a866f39	140	static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
03f822f5	141	{
fe44e70d	142	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	143	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
fc13d5a5	144	int offset = d->hwirq;
03f822f5	145	int regoffset = offset / 8;
4e2678b5	146	int mask = BIT(offset % 8);
03f822f5	147
1fe3bd9e	148	if (type & IRQ_TYPE_LEVEL_LOW \|\| type & IRQ_TYPE_LEVEL_HIGH)
03f822f5 RV	149	return -EINVAL;
03f822f5 RV	150
c6a05a05 PC	151	/* STMPE801 and STMPE 1600 don't have RE and FE registers */
	152	if (stmpe_gpio->stmpe->partnum == STMPE801 \|\|
	153	stmpe_gpio->stmpe->partnum == STMPE1600)
cccdceb9 VK	154	return 0;
cccdceb9 VK	155
1fe3bd9e	156	if (type & IRQ_TYPE_EDGE_RISING)
03f822f5 RV	157	stmpe_gpio->regs[REG_RE][regoffset] \|= mask;
	158	else
	159	stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
	160
1fe3bd9e	161	if (type & IRQ_TYPE_EDGE_FALLING)
03f822f5 RV	162	stmpe_gpio->regs[REG_FE][regoffset] \|= mask;
	163	else
	164	stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
	165
	166	return 0;
	167	}
	168
2a866f39	169	static void stmpe_gpio_irq_lock(struct irq_data *d)
03f822f5	170	{
fe44e70d	171	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	172	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
03f822f5 RV	173
	174	mutex_lock(&stmpe_gpio->irq_lock);
	175	}
	176
2a866f39	177	static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
03f822f5	178	{
fe44e70d	179	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	180	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
03f822f5 RV	181	struct stmpe *stmpe = stmpe_gpio->stmpe;
03f822f5 RV	182	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
43db289d PC	183	static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
	184	[REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
	185	[REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
	186	[REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
	187	[REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
	188	[REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
	189	[REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
	190	[REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
	191	[REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
	192	[REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
03f822f5 RV	193	};
	194	int i, j;
	195
b888fb6f PC	196	/*
	197	* STMPE1600: to be able to get IRQ from pins,
	198	* a read must be done on GPMR register, or a write in
	199	* GPSR or GPCR registers
	200	*/
	201	if (stmpe->partnum == STMPE1600) {
	202	stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
	203	stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
	204	}
	205
03f822f5	206	for (i = 0; i < CACHE_NR_REGS; i++) {
c6a05a05 PC	207	/* STMPE801 and STMPE1600 don't have RE and FE registers */
	208	if ((stmpe->partnum == STMPE801 \|\|
	209	stmpe->partnum == STMPE1600) &&
	210	(i != REG_IE))
cccdceb9 VK	211	continue;
cccdceb9 VK	212
03f822f5 RV	213	for (j = 0; j < num_banks; j++) {
	214	u8 old = stmpe_gpio->oldregs[i][j];
	215	u8 new = stmpe_gpio->regs[i][j];
	216
	217	if (new == old)
	218	continue;
	219
	220	stmpe_gpio->oldregs[i][j] = new;
43db289d	221	stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
03f822f5 RV	222	}
	223	}
	224
	225	mutex_unlock(&stmpe_gpio->irq_lock);
	226	}
	227
2a866f39	228	static void stmpe_gpio_irq_mask(struct irq_data *d)
03f822f5	229	{
fe44e70d	230	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	231	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
fc13d5a5	232	int offset = d->hwirq;
03f822f5	233	int regoffset = offset / 8;
4e2678b5	234	int mask = BIT(offset % 8);
03f822f5 RV	235
03f822f5 RV	236	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
32585b56	237	gpiochip_disable_irq(gc, offset);
03f822f5 RV	238	}
03f822f5 RV	239
2a866f39	240	static void stmpe_gpio_irq_unmask(struct irq_data *d)
03f822f5	241	{
fe44e70d	242	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	243	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
fc13d5a5	244	int offset = d->hwirq;
03f822f5	245	int regoffset = offset / 8;
4e2678b5	246	int mask = BIT(offset % 8);
03f822f5	247
32585b56	248	gpiochip_enable_irq(gc, offset);
03f822f5 RV	249	stmpe_gpio->regs[REG_IE][regoffset] \|= mask;
	250	}
	251
27ec8a9c LW	252	static void stmpe_dbg_show_one(struct seq_file *s,
	253	struct gpio_chip *gc,
	254	unsigned offset, unsigned gpio)
	255	{
b03c04a0	256	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
27ec8a9c	257	struct stmpe *stmpe = stmpe_gpio->stmpe;
27ec8a9c	258	bool val = !!stmpe_gpio_get(gc, offset);
43db289d PC	259	u8 bank = offset / 8;
43db289d PC	260	u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
4e2678b5	261	u8 mask = BIT(offset % 8);
27ec8a9c LW	262	int ret;
	263	u8 dir;
	264
f1b33ce4 BG	265	char *label __free(kfree) = gpiochip_dup_line_label(gc, offset);
	266	if (IS_ERR(label))
	267	return;
	268
27ec8a9c LW	269	ret = stmpe_reg_read(stmpe, dir_reg);
	270	if (ret < 0)
	271	return;
	272	dir = !!(ret & mask);
	273
	274	if (dir) {
	275	seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
	276	gpio, label ?: "(none)",
	277	val ? "hi" : "lo");
	278	} else {
287849cb PC	279	u8 edge_det_reg;
	280	u8 rise_reg;
	281	u8 fall_reg;
	282	u8 irqen_reg;
	283
e2843cb6 CIK	284	static const char * const edge_det_values[] = {
	285	"edge-inactive",
	286	"edge-asserted",
	287	"not-supported"
	288	};
	289	static const char * const rise_values[] = {
	290	"no-rising-edge-detection",
	291	"rising-edge-detection",
	292	"not-supported"
	293	};
	294	static const char * const fall_values[] = {
	295	"no-falling-edge-detection",
	296	"falling-edge-detection",
	297	"not-supported"
	298	};
287849cb PC	299	#define NOT_SUPPORTED_IDX 2
	300	u8 edge_det = NOT_SUPPORTED_IDX;
	301	u8 rise = NOT_SUPPORTED_IDX;
	302	u8 fall = NOT_SUPPORTED_IDX;
27ec8a9c LW	303	bool irqen;
27ec8a9c LW	304
287849cb PC	305	switch (stmpe->partnum) {
	306	case STMPE610:
	307	case STMPE811:
	308	case STMPE1601:
	309	case STMPE2401:
	310	case STMPE2403:
43db289d	311	edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
287849cb PC	312	ret = stmpe_reg_read(stmpe, edge_det_reg);
	313	if (ret < 0)
	314	return;
	315	edge_det = !!(ret & mask);
df561f66	316	fallthrough;
287849cb	317	case STMPE1801:
43db289d PC	318	rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
	319	fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
	320
287849cb PC	321	ret = stmpe_reg_read(stmpe, rise_reg);
	322	if (ret < 0)
	323	return;
	324	rise = !!(ret & mask);
	325	ret = stmpe_reg_read(stmpe, fall_reg);
	326	if (ret < 0)
	327	return;
	328	fall = !!(ret & mask);
df561f66	329	fallthrough;
287849cb	330	case STMPE801:
c6a05a05	331	case STMPE1600:
43db289d	332	irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
287849cb PC	333	break;
	334
	335	default:
27ec8a9c	336	return;
287849cb PC	337	}
287849cb PC	338
27ec8a9c LW	339	ret = stmpe_reg_read(stmpe, irqen_reg);
	340	if (ret < 0)
	341	return;
	342	irqen = !!(ret & mask);
	343
287849cb	344	seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
27ec8a9c LW	345	gpio, label ?: "(none)",
27ec8a9c LW	346	val ? "hi" : "lo",
287849cb PC	347	edge_det_values[edge_det],
	348	irqen ? "IRQ-enabled" : "IRQ-disabled",
	349	rise_values[rise],
	350	fall_values[fall]);
27ec8a9c LW	351	}
	352	}
	353
	354	static void stmpe_dbg_show(struct seq_file s, struct gpio_chip gc)
	355	{
	356	unsigned i;
	357	unsigned gpio = gc->base;
	358
	359	for (i = 0; i < gc->ngpio; i++, gpio++) {
	360	stmpe_dbg_show_one(s, gc, i, gpio);
0d83a5eb	361	seq_putc(s, '\n');
27ec8a9c LW	362	}
	363	}
	364
32585b56	365	static const struct irq_chip stmpe_gpio_irq_chip = {
03f822f5	366	.name = "stmpe-gpio",
2a866f39 LB	367	.irq_bus_lock = stmpe_gpio_irq_lock,
	368	.irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
	369	.irq_mask = stmpe_gpio_irq_mask,
	370	.irq_unmask = stmpe_gpio_irq_unmask,
	371	.irq_set_type = stmpe_gpio_irq_set_type,
32585b56 LW	372	.flags = IRQCHIP_IMMUTABLE,
32585b56 LW	373	GPIOCHIP_IRQ_RESOURCE_HELPERS,
03f822f5 RV	374	};
03f822f5 RV	375
97fe7bef LA	376	#define MAX_GPIOS 24
97fe7bef LA	377
03f822f5 RV	378	static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
	379	{
	380	struct stmpe_gpio *stmpe_gpio = dev;
	381	struct stmpe *stmpe = stmpe_gpio->stmpe;
c6a05a05	382	u8 statmsbreg;
03f822f5	383	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
97fe7bef	384	u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
03f822f5 RV	385	int ret;
	386	int i;
	387
c6a05a05 PC	388	/*
	389	* the stmpe_block_read() call below, imposes to set statmsbreg
	390	* with the register located at the lowest address. As STMPE1600
	391	* variant is the only one which respect registers address's order
	392	* (LSB regs located at lowest address than MSB ones) whereas all
	393	* the others have a registers layout with MSB located before the
	394	* LSB regs.
	395	*/
	396	if (stmpe->partnum == STMPE1600)
	397	statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
	398	else
	399	statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	400
03f822f5 RV	401	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	402	if (ret < 0)
	403	return IRQ_NONE;
	404
	405	for (i = 0; i < num_banks; i++) {
c6a05a05 PC	406	int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
c6a05a05 PC	407	num_banks - i - 1;
03f822f5 RV	408	unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
	409	unsigned int stat = status[i];
	410
	411	stat &= enabled;
	412	if (!stat)
	413	continue;
	414
	415	while (stat) {
	416	int bit = __ffs(stat);
	417	int line = bank * 8 + bit;
f0fbe7bc	418	int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
ed05e204	419	line);
03f822f5	420
ed05e204	421	handle_nested_irq(child_irq);
4e2678b5	422	stat &= ~BIT(bit);
03f822f5 RV	423	}
03f822f5 RV	424
6936e1f8 PC	425	/*
6936e1f8 PC	426	* interrupt status register write has no effect on
c6a05a05 PC	427	* 801/1801/1600, bits are cleared when read.
c6a05a05 PC	428	* Edge detect register is not present on 801/1600/1801
6936e1f8	429	*/
d1ca19cb	430	if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
c6a05a05	431	stmpe->partnum != STMPE1801) {
6936e1f8	432	stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
43db289d	433	stmpe_reg_write(stmpe,
1516c635	434	stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
43db289d	435	status[i]);
6936e1f8	436	}
03f822f5 RV	437	}
	438
	439	return IRQ_HANDLED;
	440	}
	441
5fbe5b58 LW	442	static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
	443	unsigned long *valid_mask,
	444	unsigned int ngpios)
	445	{
	446	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	447	int i;
	448
	449	if (!stmpe_gpio->norequest_mask)
	450	return;
	451
	452	/* Forbid unused lines to be mapped as IRQs */
	453	for (i = 0; i < sizeof(u32); i++) {
	454	if (stmpe_gpio->norequest_mask & BIT(i))
	455	clear_bit(i, valid_mask);
	456	}
	457	}
	458
2a9a2cca AA	459	static void stmpe_gpio_disable(void *stmpe)
	460	{
	461	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
	462	}
	463
3836309d	464	static int stmpe_gpio_probe(struct platform_device *pdev)
03f822f5	465	{
a7943313	466	struct device *dev = &pdev->dev;
56f534dd	467	struct stmpe *stmpe = dev_get_drvdata(dev->parent);
03f822f5	468	struct stmpe_gpio *stmpe_gpio;
0f719231	469	int ret, irq;
03f822f5	470
97fe7bef	471	if (stmpe->num_gpios > MAX_GPIOS) {
56f534dd	472	dev_err(dev, "Need to increase maximum GPIO number\n");
97fe7bef LA	473	return -EINVAL;
	474	}
	475
56f534dd	476	stmpe_gpio = devm_kzalloc(dev, sizeof(*stmpe_gpio), GFP_KERNEL);
03f822f5 RV	477	if (!stmpe_gpio)
	478	return -ENOMEM;
	479
	480	mutex_init(&stmpe_gpio->irq_lock);
	481
03f822f5	482	stmpe_gpio->stmpe = stmpe;
03f822f5 RV	483	stmpe_gpio->chip = template_chip;
03f822f5 RV	484	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
56f534dd	485	stmpe_gpio->chip.parent = dev;
9e9dc7d9	486	stmpe_gpio->chip.base = -1;
03f822f5	487
27ec8a9c LW	488	if (IS_ENABLED(CONFIG_DEBUG_FS))
	489	stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
	490
e6815a05	491	device_property_read_u32(dev, "st,norequest-mask", &stmpe_gpio->norequest_mask);
86605cfe	492
03f822f5 RV	493	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
03f822f5 RV	494	if (ret)
2a9a2cca AA	495	return ret;
2a9a2cca AA	496
56f534dd	497	ret = devm_add_action_or_reset(dev, stmpe_gpio_disable, stmpe);
2a9a2cca AA	498	if (ret)
2a9a2cca AA	499	return ret;
03f822f5	500
a7943313	501	irq = platform_get_irq(pdev, 0);
fe44e70d	502	if (irq > 0) {
97450796 LW	503	struct gpio_irq_chip *girq;
97450796 LW	504
56f534dd AS	505	ret = devm_request_threaded_irq(dev, irq, NULL, stmpe_gpio_irq,
56f534dd AS	506	IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
1882e769	507	if (ret)
a7943313	508	return dev_err_probe(dev, ret, "unable to register IRQ handler\n");
03f822f5	509
97450796	510	girq = &stmpe_gpio->chip.irq;
32585b56	511	gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip);
97450796 LW	512	/* This will let us handle the parent IRQ in the driver */
	513	girq->parent_handler = NULL;
	514	girq->num_parents = 0;
	515	girq->parents = NULL;
	516	girq->default_type = IRQ_TYPE_NONE;
	517	girq->handler = handle_simple_irq;
	518	girq->threaded = true;
8aa16335	519	girq->init_valid_mask = stmpe_init_irq_valid_mask;
03f822f5 RV	520	}
03f822f5 RV	521
56f534dd	522	return devm_gpiochip_add_data(dev, &stmpe_gpio->chip, stmpe_gpio);
03f822f5 RV	523	}
03f822f5 RV	524
03f822f5	525	static struct platform_driver stmpe_gpio_driver = {
3b52bb96 PG	526	.driver = {
	527	.suppress_bind_attrs = true,
	528	.name = "stmpe-gpio",
3b52bb96	529	},
03f822f5	530	.probe = stmpe_gpio_probe,
03f822f5 RV	531	};
	532
	533	static int __init stmpe_gpio_init(void)
	534	{
	535	return platform_driver_register(&stmpe_gpio_driver);
	536	}
	537	subsys_initcall(stmpe_gpio_init);