[linux-block.git] / drivers / gpio / gpio-stmpe.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * License Terms: GNU General Public License, version 2
 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/mfd/stmpe.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_RE, REG_FE, REG_IE };

#define CACHE_NR_REGS	3
/* No variant has more than 24 GPIOs */
#define CACHE_NR_BANKS	(24 / 8)

struct stmpe_gpio {
	struct gpio_chip chip;
	struct stmpe *stmpe;
	struct device *dev;
	struct mutex irq_lock;
	unsigned norequest_mask;
	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
{
	return container_of(chip, struct stmpe_gpio, chip);
}

static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	return !!(ret & mask);
}

static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	u8 reg = stmpe->regs[which] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	/*
	 * Some variants have single register for gpio set/clear functionality.
	 * For them we need to write 0 to clear and 1 to set.
	 */
	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
		stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	else
		stmpe_reg_write(stmpe, reg, mask);
}

static int stmpe_gpio_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	stmpe_gpio_set(chip, offset, val);

	return stmpe_set_bits(stmpe, reg, mask, mask);
}

static int stmpe_gpio_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = 1 << (offset % 8);

	return stmpe_set_bits(stmpe, reg, mask, 0);
}

static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;

	if (stmpe_gpio->norequest_mask & (1 << offset))
		return -EINVAL;

	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
}

static struct gpio_chip template_chip = {
	.label			= "stmpe",
	.owner			= THIS_MODULE,
	.direction_input	= stmpe_gpio_direction_input,
	.get			= stmpe_gpio_get,
	.direction_output	= stmpe_gpio_direction_output,
	.set			= stmpe_gpio_set,
	.request		= stmpe_gpio_request,
	.can_sleep		= true,
};

static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
		return -EINVAL;

	/* STMPE801 doesn't have RE and FE registers */
	if (stmpe_gpio->stmpe->partnum == STMPE801)
		return 0;

	if (type == IRQ_TYPE_EDGE_RISING)
		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;

	if (type == IRQ_TYPE_EDGE_FALLING)
		stmpe_gpio->regs[REG_FE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;

	return 0;
}

static void stmpe_gpio_irq_lock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);

	mutex_lock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	static const u8 regmap[] = {
		[REG_RE]	= STMPE_IDX_GPRER_LSB,
		[REG_FE]	= STMPE_IDX_GPFER_LSB,
		[REG_IE]	= STMPE_IDX_IEGPIOR_LSB,
	};
	int i, j;

	for (i = 0; i < CACHE_NR_REGS; i++) {
		/* STMPE801 doesn't have RE and FE registers */
		if ((stmpe->partnum == STMPE801) &&
				(i != REG_IE))
			continue;

		for (j = 0; j < num_banks; j++) {
			u8 old = stmpe_gpio->oldregs[i][j];
			u8 new = stmpe_gpio->regs[i][j];

			if (new == old)
				continue;

			stmpe_gpio->oldregs[i][j] = new;
			stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
		}
	}

	mutex_unlock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
}

static void stmpe_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = 1 << (offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] |= mask;
}

static struct irq_chip stmpe_gpio_irq_chip = {
	.name			= "stmpe-gpio",
	.irq_bus_lock		= stmpe_gpio_irq_lock,
	.irq_bus_sync_unlock	= stmpe_gpio_irq_sync_unlock,
	.irq_mask		= stmpe_gpio_irq_mask,
	.irq_unmask		= stmpe_gpio_irq_unmask,
	.irq_set_type		= stmpe_gpio_irq_set_type,
};

static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
{
	struct stmpe_gpio *stmpe_gpio = dev;
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	u8 status[num_banks];
	int ret;
	int i;

	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < num_banks; i++) {
		int bank = num_banks - i - 1;
		unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
		unsigned int stat = status[i];

		stat &= enabled;
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = bank * 8 + bit;
			int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain,
							 line);

			handle_nested_irq(child_irq);
			stat &= ~(1 << bit);
		}

		stmpe_reg_write(stmpe, statmsbreg + i, status[i]);

		/* Edge detect register is not present on 801 */
		if (stmpe->partnum != STMPE801)
			stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
					+ i, status[i]);
	}

	return IRQ_HANDLED;
}

static int stmpe_gpio_probe(struct platform_device *pdev)
{
	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
	struct device_node *np = pdev->dev.of_node;
	struct stmpe_gpio_platform_data *pdata;
	struct stmpe_gpio *stmpe_gpio;
	int ret;
	int irq = 0;

	pdata = stmpe->pdata->gpio;

	irq = platform_get_irq(pdev, 0);

	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
	if (!stmpe_gpio)
		return -ENOMEM;

	mutex_init(&stmpe_gpio->irq_lock);

	stmpe_gpio->dev = &pdev->dev;
	stmpe_gpio->stmpe = stmpe;
	stmpe_gpio->chip = template_chip;
	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	stmpe_gpio->chip.dev = &pdev->dev;
#ifdef CONFIG_OF
	stmpe_gpio->chip.of_node = np;
#endif
	stmpe_gpio->chip.base = -1;

	if (pdata)
		stmpe_gpio->norequest_mask = pdata->norequest_mask;
	else if (np)
		of_property_read_u32(np, "st,norequest-mask",
				&stmpe_gpio->norequest_mask);

	if (irq < 0)
		dev_info(&pdev->dev,
			"device configured in no-irq mode: "
			"irqs are not available\n");

	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	if (ret)
		goto out_free;

	ret = gpiochip_add(&stmpe_gpio->chip);
	if (ret) {
		dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
		goto out_disable;
	}

	if (irq > 0) {
		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
				stmpe_gpio_irq, IRQF_ONESHOT,
				"stmpe-gpio", stmpe_gpio);
		if (ret) {
			dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
			goto out_disable;
		}
		ret =  gpiochip_irqchip_add(&stmpe_gpio->chip,
					    &stmpe_gpio_irq_chip,
					    0,
					    handle_simple_irq,
					    IRQ_TYPE_NONE);
		if (ret) {
			dev_err(&pdev->dev,
				"could not connect irqchip to gpiochip\n");
			goto out_disable;
		}

		gpiochip_set_chained_irqchip(&stmpe_gpio->chip,
					     &stmpe_gpio_irq_chip,
					     irq,
					     NULL);
	}

	if (pdata && pdata->setup)
		pdata->setup(stmpe, stmpe_gpio->chip.base);

	platform_set_drvdata(pdev, stmpe_gpio);

	return 0;

out_disable:
	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
	gpiochip_remove(&stmpe_gpio->chip);
out_free:
	kfree(stmpe_gpio);
	return ret;
}

static int stmpe_gpio_remove(struct platform_device *pdev)
{
	struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;

	if (pdata && pdata->remove)
		pdata->remove(stmpe, stmpe_gpio->chip.base);

	gpiochip_remove(&stmpe_gpio->chip);

	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);

	kfree(stmpe_gpio);

	return 0;
}

static struct platform_driver stmpe_gpio_driver = {
	.driver.name	= "stmpe-gpio",
	.driver.owner	= THIS_MODULE,
	.probe		= stmpe_gpio_probe,
	.remove		= stmpe_gpio_remove,
};

static int __init stmpe_gpio_init(void)
{
	return platform_driver_register(&stmpe_gpio_driver);
}
subsys_initcall(stmpe_gpio_init);

static void __exit stmpe_gpio_exit(void)
{
	platform_driver_unregister(&stmpe_gpio_driver);
}
module_exit(stmpe_gpio_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("STMPExxxx GPIO driver");
MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");
Commit	Line	Data
03f822f5 RV	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* License Terms: GNU General Public License, version 2
	5	* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	6	*/
	7
	8	#include <linux/module.h>
	9	#include <linux/init.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/slab.h>
	12	#include <linux/gpio.h>
03f822f5	13	#include <linux/interrupt.h>
86605cfe	14	#include <linux/of.h>
03f822f5 RV	15	#include <linux/mfd/stmpe.h>
	16
	17	/*
	18	* These registers are modified under the irq bus lock and cached to avoid
	19	* unnecessary writes in bus_sync_unlock.
	20	*/
	21	enum { REG_RE, REG_FE, REG_IE };
	22
	23	#define CACHE_NR_REGS 3
9e9dc7d9 LW	24	/* No variant has more than 24 GPIOs */
9e9dc7d9 LW	25	#define CACHE_NR_BANKS (24 / 8)
03f822f5 RV	26
	27	struct stmpe_gpio {
	28	struct gpio_chip chip;
	29	struct stmpe *stmpe;
	30	struct device *dev;
	31	struct mutex irq_lock;
b8e9cf0b	32	unsigned norequest_mask;
03f822f5 RV	33	/* Caches of interrupt control registers for bus_lock */
	34	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	35	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	36	};
	37
	38	static inline struct stmpe_gpio to_stmpe_gpio(struct gpio_chip chip)
	39	{
	40	return container_of(chip, struct stmpe_gpio, chip);
	41	}
	42
	43	static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
	44	{
	45	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	46	struct stmpe *stmpe = stmpe_gpio->stmpe;
	47	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB] - (offset / 8);
	48	u8 mask = 1 << (offset % 8);
	49	int ret;
	50
	51	ret = stmpe_reg_read(stmpe, reg);
	52	if (ret < 0)
	53	return ret;
	54
7535b8be	55	return !!(ret & mask);
03f822f5 RV	56	}
	57
	58	static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	59	{
	60	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	61	struct stmpe *stmpe = stmpe_gpio->stmpe;
	62	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	63	u8 reg = stmpe->regs[which] - (offset / 8);
	64	u8 mask = 1 << (offset % 8);
	65
cccdceb9 VK	66	/*
	67	* Some variants have single register for gpio set/clear functionality.
	68	* For them we need to write 0 to clear and 1 to set.
	69	*/
	70	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
	71	stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	72	else
	73	stmpe_reg_write(stmpe, reg, mask);
03f822f5 RV	74	}
	75
	76	static int stmpe_gpio_direction_output(struct gpio_chip *chip,
	77	unsigned offset, int val)
	78	{
	79	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	80	struct stmpe *stmpe = stmpe_gpio->stmpe;
	81	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	82	u8 mask = 1 << (offset % 8);
	83
	84	stmpe_gpio_set(chip, offset, val);
	85
	86	return stmpe_set_bits(stmpe, reg, mask, mask);
	87	}
	88
	89	static int stmpe_gpio_direction_input(struct gpio_chip *chip,
	90	unsigned offset)
	91	{
	92	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	93	struct stmpe *stmpe = stmpe_gpio->stmpe;
	94	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	95	u8 mask = 1 << (offset % 8);
	96
	97	return stmpe_set_bits(stmpe, reg, mask, 0);
	98	}
	99
03f822f5 RV	100	static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
	101	{
	102	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
	103	struct stmpe *stmpe = stmpe_gpio->stmpe;
	104
b8e9cf0b WS	105	if (stmpe_gpio->norequest_mask & (1 << offset))
	106	return -EINVAL;
	107
03f822f5 RV	108	return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
	109	}
	110
	111	static struct gpio_chip template_chip = {
	112	.label = "stmpe",
	113	.owner = THIS_MODULE,
	114	.direction_input = stmpe_gpio_direction_input,
	115	.get = stmpe_gpio_get,
	116	.direction_output = stmpe_gpio_direction_output,
	117	.set = stmpe_gpio_set,
03f822f5	118	.request = stmpe_gpio_request,
9fb1f39e	119	.can_sleep = true,
03f822f5 RV	120	};
03f822f5 RV	121
2a866f39	122	static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
03f822f5	123	{
fe44e70d LW	124	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
fe44e70d LW	125	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
fc13d5a5	126	int offset = d->hwirq;
03f822f5 RV	127	int regoffset = offset / 8;
	128	int mask = 1 << (offset % 8);
	129
	130	if (type == IRQ_TYPE_LEVEL_LOW \|\| type == IRQ_TYPE_LEVEL_HIGH)
	131	return -EINVAL;
	132
cccdceb9 VK	133	/* STMPE801 doesn't have RE and FE registers */
	134	if (stmpe_gpio->stmpe->partnum == STMPE801)
	135	return 0;
	136
03f822f5 RV	137	if (type == IRQ_TYPE_EDGE_RISING)
	138	stmpe_gpio->regs[REG_RE][regoffset] \|= mask;
	139	else
	140	stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
	141
	142	if (type == IRQ_TYPE_EDGE_FALLING)
	143	stmpe_gpio->regs[REG_FE][regoffset] \|= mask;
	144	else
	145	stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
	146
	147	return 0;
	148	}
	149
2a866f39	150	static void stmpe_gpio_irq_lock(struct irq_data *d)
03f822f5	151	{
fe44e70d LW	152	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
fe44e70d LW	153	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
03f822f5 RV	154
	155	mutex_lock(&stmpe_gpio->irq_lock);
	156	}
	157
2a866f39	158	static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
03f822f5	159	{
fe44e70d LW	160	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
fe44e70d LW	161	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
03f822f5 RV	162	struct stmpe *stmpe = stmpe_gpio->stmpe;
	163	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	164	static const u8 regmap[] = {
	165	[REG_RE] = STMPE_IDX_GPRER_LSB,
	166	[REG_FE] = STMPE_IDX_GPFER_LSB,
	167	[REG_IE] = STMPE_IDX_IEGPIOR_LSB,
	168	};
	169	int i, j;
	170
	171	for (i = 0; i < CACHE_NR_REGS; i++) {
cccdceb9 VK	172	/* STMPE801 doesn't have RE and FE registers */
	173	if ((stmpe->partnum == STMPE801) &&
	174	(i != REG_IE))
	175	continue;
	176
03f822f5 RV	177	for (j = 0; j < num_banks; j++) {
	178	u8 old = stmpe_gpio->oldregs[i][j];
	179	u8 new = stmpe_gpio->regs[i][j];
	180
	181	if (new == old)
	182	continue;
	183
	184	stmpe_gpio->oldregs[i][j] = new;
	185	stmpe_reg_write(stmpe, stmpe->regs[regmap[i]] - j, new);
	186	}
	187	}
	188
	189	mutex_unlock(&stmpe_gpio->irq_lock);
	190	}
	191
2a866f39	192	static void stmpe_gpio_irq_mask(struct irq_data *d)
03f822f5	193	{
fe44e70d LW	194	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
fe44e70d LW	195	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
fc13d5a5	196	int offset = d->hwirq;
03f822f5 RV	197	int regoffset = offset / 8;
	198	int mask = 1 << (offset % 8);
	199
	200	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
	201	}
	202
2a866f39	203	static void stmpe_gpio_irq_unmask(struct irq_data *d)
03f822f5	204	{
fe44e70d LW	205	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
fe44e70d LW	206	struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
fc13d5a5	207	int offset = d->hwirq;
03f822f5 RV	208	int regoffset = offset / 8;
	209	int mask = 1 << (offset % 8);
	210
	211	stmpe_gpio->regs[REG_IE][regoffset] \|= mask;
	212	}
	213
	214	static struct irq_chip stmpe_gpio_irq_chip = {
	215	.name = "stmpe-gpio",
2a866f39 LB	216	.irq_bus_lock = stmpe_gpio_irq_lock,
	217	.irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
	218	.irq_mask = stmpe_gpio_irq_mask,
	219	.irq_unmask = stmpe_gpio_irq_unmask,
	220	.irq_set_type = stmpe_gpio_irq_set_type,
03f822f5 RV	221	};
	222
	223	static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
	224	{
	225	struct stmpe_gpio *stmpe_gpio = dev;
	226	struct stmpe *stmpe = stmpe_gpio->stmpe;
	227	u8 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	228	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	229	u8 status[num_banks];
	230	int ret;
	231	int i;
	232
	233	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	234	if (ret < 0)
	235	return IRQ_NONE;
	236
	237	for (i = 0; i < num_banks; i++) {
	238	int bank = num_banks - i - 1;
	239	unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
	240	unsigned int stat = status[i];
	241
	242	stat &= enabled;
	243	if (!stat)
	244	continue;
	245
	246	while (stat) {
	247	int bit = __ffs(stat);
	248	int line = bank * 8 + bit;
fe44e70d	249	int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain,
ed05e204	250	line);
03f822f5	251
ed05e204	252	handle_nested_irq(child_irq);
03f822f5 RV	253	stat &= ~(1 << bit);
	254	}
	255
	256	stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
cccdceb9 VK	257
	258	/* Edge detect register is not present on 801 */
	259	if (stmpe->partnum != STMPE801)
	260	stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
	261	+ i, status[i]);
03f822f5 RV	262	}
	263
	264	return IRQ_HANDLED;
	265	}
	266
3836309d	267	static int stmpe_gpio_probe(struct platform_device *pdev)
03f822f5 RV	268	{
03f822f5 RV	269	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
86605cfe	270	struct device_node *np = pdev->dev.of_node;
03f822f5 RV	271	struct stmpe_gpio_platform_data *pdata;
	272	struct stmpe_gpio *stmpe_gpio;
	273	int ret;
38040c85	274	int irq = 0;
03f822f5 RV	275
03f822f5 RV	276	pdata = stmpe->pdata->gpio;
03f822f5 RV	277
03f822f5 RV	278	irq = platform_get_irq(pdev, 0);
03f822f5 RV	279
	280	stmpe_gpio = kzalloc(sizeof(struct stmpe_gpio), GFP_KERNEL);
	281	if (!stmpe_gpio)
	282	return -ENOMEM;
	283
	284	mutex_init(&stmpe_gpio->irq_lock);
	285
	286	stmpe_gpio->dev = &pdev->dev;
	287	stmpe_gpio->stmpe = stmpe;
03f822f5 RV	288	stmpe_gpio->chip = template_chip;
	289	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	290	stmpe_gpio->chip.dev = &pdev->dev;
9afd9b70 GF	291	#ifdef CONFIG_OF
	292	stmpe_gpio->chip.of_node = np;
	293	#endif
9e9dc7d9	294	stmpe_gpio->chip.base = -1;
03f822f5	295
86605cfe VKS	296	if (pdata)
	297	stmpe_gpio->norequest_mask = pdata->norequest_mask;
	298	else if (np)
	299	of_property_read_u32(np, "st,norequest-mask",
	300	&stmpe_gpio->norequest_mask);
	301
9e9dc7d9	302	if (irq < 0)
38040c85	303	dev_info(&pdev->dev,
fe44e70d	304	"device configured in no-irq mode: "
38040c85	305	"irqs are not available\n");
03f822f5 RV	306
	307	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	308	if (ret)
02bf0749	309	goto out_free;
03f822f5	310
3f97d5fc LW	311	ret = gpiochip_add(&stmpe_gpio->chip);
	312	if (ret) {
	313	dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
	314	goto out_disable;
	315	}
	316
fe44e70d LW	317	if (irq > 0) {
	318	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
	319	stmpe_gpio_irq, IRQF_ONESHOT,
	320	"stmpe-gpio", stmpe_gpio);
38040c85 CB	321	if (ret) {
38040c85 CB	322	dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
fc13d5a5	323	goto out_disable;
38040c85	324	}
fe44e70d LW	325	ret = gpiochip_irqchip_add(&stmpe_gpio->chip,
	326	&stmpe_gpio_irq_chip,
	327	0,
	328	handle_simple_irq,
	329	IRQ_TYPE_NONE);
	330	if (ret) {
	331	dev_err(&pdev->dev,
	332	"could not connect irqchip to gpiochip\n");
3f97d5fc	333	goto out_disable;
fe44e70d	334	}
03f822f5	335
3f97d5fc LW	336	gpiochip_set_chained_irqchip(&stmpe_gpio->chip,
	337	&stmpe_gpio_irq_chip,
	338	irq,
	339	NULL);
03f822f5 RV	340	}
	341
	342	if (pdata && pdata->setup)
	343	pdata->setup(stmpe, stmpe_gpio->chip.base);
	344
	345	platform_set_drvdata(pdev, stmpe_gpio);
	346
	347	return 0;
	348
02bf0749 VK	349	out_disable:
02bf0749 VK	350	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
3f97d5fc	351	gpiochip_remove(&stmpe_gpio->chip);
03f822f5 RV	352	out_free:
	353	kfree(stmpe_gpio);
	354	return ret;
	355	}
	356
206210ce	357	static int stmpe_gpio_remove(struct platform_device *pdev)
03f822f5 RV	358	{
	359	struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
	360	struct stmpe *stmpe = stmpe_gpio->stmpe;
	361	struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
03f822f5 RV	362
	363	if (pdata && pdata->remove)
	364	pdata->remove(stmpe, stmpe_gpio->chip.base);
	365
9f5132ae	366	gpiochip_remove(&stmpe_gpio->chip);
03f822f5 RV	367
	368	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
	369
03f822f5 RV	370	kfree(stmpe_gpio);
	371
	372	return 0;
	373	}
	374
	375	static struct platform_driver stmpe_gpio_driver = {
	376	.driver.name = "stmpe-gpio",
	377	.driver.owner = THIS_MODULE,
	378	.probe = stmpe_gpio_probe,
8283c4ff	379	.remove = stmpe_gpio_remove,
03f822f5 RV	380	};
	381
	382	static int __init stmpe_gpio_init(void)
	383	{
	384	return platform_driver_register(&stmpe_gpio_driver);
	385	}
	386	subsys_initcall(stmpe_gpio_init);
	387
	388	static void __exit stmpe_gpio_exit(void)
	389	{
	390	platform_driver_unregister(&stmpe_gpio_driver);
	391	}
	392	module_exit(stmpe_gpio_exit);
	393
	394	MODULE_LICENSE("GPL v2");
	395	MODULE_DESCRIPTION("STMPExxxx GPIO driver");
	396	MODULE_AUTHOR("Rabin Vincent <rabin.vincent@stericsson.com>");