[linux-block.git] / drivers / gpio / gpio-stmpe.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
 */

#include <linux/cleanup.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/mfd/stmpe.h>
#include <linux/seq_file.h>
#include <linux/bitops.h>

/*
 * These registers are modified under the irq bus lock and cached to avoid
 * unnecessary writes in bus_sync_unlock.
 */
enum { REG_RE, REG_FE, REG_IE };

enum { LSB, CSB, MSB };

#define CACHE_NR_REGS	3
/* No variant has more than 24 GPIOs */
#define CACHE_NR_BANKS	(24 / 8)

struct stmpe_gpio {
	struct gpio_chip chip;
	struct stmpe *stmpe;
	struct device *dev;
	struct mutex irq_lock;
	u32 norequest_mask;
	/* Caches of interrupt control registers for bus_lock */
	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
};

static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
	u8 mask = BIT(offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	return !!(ret & mask);
}

static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
	u8 reg = stmpe->regs[which + (offset / 8)];
	u8 mask = BIT(offset % 8);

	/*
	 * Some variants have single register for gpio set/clear functionality.
	 * For them we need to write 0 to clear and 1 to set.
	 */
	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
		stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	else
		stmpe_reg_write(stmpe, reg, mask);
}

static int stmpe_gpio_get_direction(struct gpio_chip *chip,
				    unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
	u8 mask = BIT(offset % 8);
	int ret;

	ret = stmpe_reg_read(stmpe, reg);
	if (ret < 0)
		return ret;

	if (ret & mask)
		return GPIO_LINE_DIRECTION_OUT;

	return GPIO_LINE_DIRECTION_IN;
}

static int stmpe_gpio_direction_output(struct gpio_chip *chip,
					 unsigned offset, int val)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
	u8 mask = BIT(offset % 8);

	stmpe_gpio_set(chip, offset, val);

	return stmpe_set_bits(stmpe, reg, mask, mask);
}

static int stmpe_gpio_direction_input(struct gpio_chip *chip,
					unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
	u8 mask = BIT(offset % 8);

	return stmpe_set_bits(stmpe, reg, mask, 0);
}

static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	struct stmpe *stmpe = stmpe_gpio->stmpe;

	if (stmpe_gpio->norequest_mask & BIT(offset))
		return -EINVAL;

	return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
}

static const struct gpio_chip template_chip = {
	.label			= "stmpe",
	.owner			= THIS_MODULE,
	.get_direction		= stmpe_gpio_get_direction,
	.direction_input	= stmpe_gpio_direction_input,
	.get			= stmpe_gpio_get,
	.direction_output	= stmpe_gpio_direction_output,
	.set			= stmpe_gpio_set,
	.request		= stmpe_gpio_request,
	.can_sleep		= true,
};

static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
		return -EINVAL;

	/* STMPE801 and STMPE 1600 don't have RE and FE registers */
	if (stmpe_gpio->stmpe->partnum == STMPE801 ||
	    stmpe_gpio->stmpe->partnum == STMPE1600)
		return 0;

	if (type & IRQ_TYPE_EDGE_RISING)
		stmpe_gpio->regs[REG_RE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;

	if (type & IRQ_TYPE_EDGE_FALLING)
		stmpe_gpio->regs[REG_FE][regoffset] |= mask;
	else
		stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;

	return 0;
}

static void stmpe_gpio_irq_lock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);

	mutex_lock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
		[REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
		[REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
		[REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
		[REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
		[REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
		[REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
		[REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
		[REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
		[REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
	};
	int i, j;

	/*
	 * STMPE1600: to be able to get IRQ from pins,
	 * a read must be done on GPMR register, or a write in
	 * GPSR or GPCR registers
	 */
	if (stmpe->partnum == STMPE1600) {
		stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
		stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
	}

	for (i = 0; i < CACHE_NR_REGS; i++) {
		/* STMPE801 and STMPE1600 don't have RE and FE registers */
		if ((stmpe->partnum == STMPE801 ||
		     stmpe->partnum == STMPE1600) &&
		     (i != REG_IE))
			continue;

		for (j = 0; j < num_banks; j++) {
			u8 old = stmpe_gpio->oldregs[i][j];
			u8 new = stmpe_gpio->regs[i][j];

			if (new == old)
				continue;

			stmpe_gpio->oldregs[i][j] = new;
			stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
		}
	}

	mutex_unlock(&stmpe_gpio->irq_lock);
}

static void stmpe_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
	gpiochip_disable_irq(gc, offset);
}

static void stmpe_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int offset = d->hwirq;
	int regoffset = offset / 8;
	int mask = BIT(offset % 8);

	gpiochip_enable_irq(gc, offset);
	stmpe_gpio->regs[REG_IE][regoffset] |= mask;
}

static void stmpe_dbg_show_one(struct seq_file *s,
			       struct gpio_chip *gc,
			       unsigned offset, unsigned gpio)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	bool val = !!stmpe_gpio_get(gc, offset);
	u8 bank = offset / 8;
	u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
	u8 mask = BIT(offset % 8);
	int ret;
	u8 dir;

	char *label __free(kfree) = gpiochip_dup_line_label(gc, offset);
	if (IS_ERR(label))
		return;

	ret = stmpe_reg_read(stmpe, dir_reg);
	if (ret < 0)
		return;
	dir = !!(ret & mask);

	if (dir) {
		seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
			   gpio, label ?: "(none)",
			   val ? "hi" : "lo");
	} else {
		u8 edge_det_reg;
		u8 rise_reg;
		u8 fall_reg;
		u8 irqen_reg;

		static const char * const edge_det_values[] = {
			"edge-inactive",
			"edge-asserted",
			"not-supported"
		};
		static const char * const rise_values[] = {
			"no-rising-edge-detection",
			"rising-edge-detection",
			"not-supported"
		};
		static const char * const fall_values[] = {
			"no-falling-edge-detection",
			"falling-edge-detection",
			"not-supported"
		};
		#define NOT_SUPPORTED_IDX 2
		u8 edge_det = NOT_SUPPORTED_IDX;
		u8 rise = NOT_SUPPORTED_IDX;
		u8 fall = NOT_SUPPORTED_IDX;
		bool irqen;

		switch (stmpe->partnum) {
		case STMPE610:
		case STMPE811:
		case STMPE1601:
		case STMPE2401:
		case STMPE2403:
			edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
			ret = stmpe_reg_read(stmpe, edge_det_reg);
			if (ret < 0)
				return;
			edge_det = !!(ret & mask);
			fallthrough;
		case STMPE1801:
			rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
			fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];

			ret = stmpe_reg_read(stmpe, rise_reg);
			if (ret < 0)
				return;
			rise = !!(ret & mask);
			ret = stmpe_reg_read(stmpe, fall_reg);
			if (ret < 0)
				return;
			fall = !!(ret & mask);
			fallthrough;
		case STMPE801:
		case STMPE1600:
			irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
			break;

		default:
			return;
		}

		ret = stmpe_reg_read(stmpe, irqen_reg);
		if (ret < 0)
			return;
		irqen = !!(ret & mask);

		seq_printf(s, " gpio-%-3d (%-20.20s) in  %s %13s %13s %25s %25s",
			   gpio, label ?: "(none)",
			   val ? "hi" : "lo",
			   edge_det_values[edge_det],
			   irqen ? "IRQ-enabled" : "IRQ-disabled",
			   rise_values[rise],
			   fall_values[fall]);
	}
}

static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
{
	unsigned i;
	unsigned gpio = gc->base;

	for (i = 0; i < gc->ngpio; i++, gpio++) {
		stmpe_dbg_show_one(s, gc, i, gpio);
		seq_putc(s, '\n');
	}
}

static const struct irq_chip stmpe_gpio_irq_chip = {
	.name			= "stmpe-gpio",
	.irq_bus_lock		= stmpe_gpio_irq_lock,
	.irq_bus_sync_unlock	= stmpe_gpio_irq_sync_unlock,
	.irq_mask		= stmpe_gpio_irq_mask,
	.irq_unmask		= stmpe_gpio_irq_unmask,
	.irq_set_type		= stmpe_gpio_irq_set_type,
	.flags			= IRQCHIP_IMMUTABLE,
	GPIOCHIP_IRQ_RESOURCE_HELPERS,
};

#define MAX_GPIOS 24

static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
{
	struct stmpe_gpio *stmpe_gpio = dev;
	struct stmpe *stmpe = stmpe_gpio->stmpe;
	u8 statmsbreg;
	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
	u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
	int ret;
	int i;

	/*
	 * the stmpe_block_read() call below, imposes to set statmsbreg
	 * with the register located at the lowest address. As STMPE1600
	 * variant is the only one which respect registers address's order
	 * (LSB regs located at lowest address than MSB ones) whereas all
	 * the others have a registers layout with MSB located before the
	 * LSB regs.
	 */
	if (stmpe->partnum == STMPE1600)
		statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
	else
		statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];

	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	if (ret < 0)
		return IRQ_NONE;

	for (i = 0; i < num_banks; i++) {
		int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
			   num_banks - i - 1;
		unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
		unsigned int stat = status[i];

		stat &= enabled;
		if (!stat)
			continue;

		while (stat) {
			int bit = __ffs(stat);
			int line = bank * 8 + bit;
			int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
							 line);

			handle_nested_irq(child_irq);
			stat &= ~BIT(bit);
		}

		/*
		 * interrupt status register write has no effect on
		 * 801/1801/1600, bits are cleared when read.
		 * Edge detect register is not present on 801/1600/1801
		 */
		if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
		    stmpe->partnum != STMPE1801) {
			stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
			stmpe_reg_write(stmpe,
					stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
					status[i]);
		}
	}

	return IRQ_HANDLED;
}

static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
				      unsigned long *valid_mask,
				      unsigned int ngpios)
{
	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	int i;

	if (!stmpe_gpio->norequest_mask)
		return;

	/* Forbid unused lines to be mapped as IRQs */
	for (i = 0; i < sizeof(u32); i++) {
		if (stmpe_gpio->norequest_mask & BIT(i))
			clear_bit(i, valid_mask);
	}
}

static void stmpe_gpio_disable(void *stmpe)
{
	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
}

static int stmpe_gpio_probe(struct platform_device *pdev)
{
	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
	struct device_node *np = pdev->dev.of_node;
	struct stmpe_gpio *stmpe_gpio;
	int ret, irq;

	if (stmpe->num_gpios > MAX_GPIOS) {
		dev_err(&pdev->dev, "Need to increase maximum GPIO number\n");
		return -EINVAL;
	}

	stmpe_gpio = devm_kzalloc(&pdev->dev, sizeof(*stmpe_gpio), GFP_KERNEL);
	if (!stmpe_gpio)
		return -ENOMEM;

	mutex_init(&stmpe_gpio->irq_lock);

	stmpe_gpio->dev = &pdev->dev;
	stmpe_gpio->stmpe = stmpe;
	stmpe_gpio->chip = template_chip;
	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
	stmpe_gpio->chip.parent = &pdev->dev;
	stmpe_gpio->chip.base = -1;

	if (IS_ENABLED(CONFIG_DEBUG_FS))
                stmpe_gpio->chip.dbg_show = stmpe_dbg_show;

	of_property_read_u32(np, "st,norequest-mask",
			&stmpe_gpio->norequest_mask);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		dev_info(&pdev->dev,
			"device configured in no-irq mode: "
			"irqs are not available\n");

	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	if (ret)
		return ret;

	ret = devm_add_action_or_reset(&pdev->dev, stmpe_gpio_disable, stmpe);
	if (ret)
		return ret;

	if (irq > 0) {
		struct gpio_irq_chip *girq;

		ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
				stmpe_gpio_irq, IRQF_ONESHOT,
				"stmpe-gpio", stmpe_gpio);
		if (ret) {
			dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
			return ret;
		}

		girq = &stmpe_gpio->chip.irq;
		gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip);
		/* This will let us handle the parent IRQ in the driver */
		girq->parent_handler = NULL;
		girq->num_parents = 0;
		girq->parents = NULL;
		girq->default_type = IRQ_TYPE_NONE;
		girq->handler = handle_simple_irq;
		girq->threaded = true;
		girq->init_valid_mask = stmpe_init_irq_valid_mask;
	}

	return devm_gpiochip_add_data(&pdev->dev, &stmpe_gpio->chip, stmpe_gpio);
}

static struct platform_driver stmpe_gpio_driver = {
	.driver = {
		.suppress_bind_attrs	= true,
		.name			= "stmpe-gpio",
	},
	.probe		= stmpe_gpio_probe,
};

static int __init stmpe_gpio_init(void)
{
	return platform_driver_register(&stmpe_gpio_driver);
}
subsys_initcall(stmpe_gpio_init);
Commit	Line	Data
1f67b599	1	// SPDX-License-Identifier: GPL-2.0-only
03f822f5 RV	2	/*
	3	* Copyright (C) ST-Ericsson SA 2010
	4	*
03f822f5 RV	5	* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
	6	*/
	7
f1b33ce4	8	#include <linux/cleanup.h>
03f822f5 RV	9	#include <linux/init.h>
	10	#include <linux/platform_device.h>
	11	#include <linux/slab.h>
ecac6e60	12	#include <linux/gpio/driver.h>
03f822f5	13	#include <linux/interrupt.h>
86605cfe	14	#include <linux/of.h>
03f822f5	15	#include <linux/mfd/stmpe.h>
27ec8a9c	16	#include <linux/seq_file.h>
96b2cca6	17	#include <linux/bitops.h>
03f822f5 RV	18
	19	/*
	20	* These registers are modified under the irq bus lock and cached to avoid
	21	* unnecessary writes in bus_sync_unlock.
	22	*/
	23	enum { REG_RE, REG_FE, REG_IE };
	24
43db289d PC	25	enum { LSB, CSB, MSB };
43db289d PC	26
03f822f5	27	#define CACHE_NR_REGS 3
9e9dc7d9 LW	28	/* No variant has more than 24 GPIOs */
9e9dc7d9 LW	29	#define CACHE_NR_BANKS (24 / 8)
03f822f5 RV	30
	31	struct stmpe_gpio {
	32	struct gpio_chip chip;
	33	struct stmpe *stmpe;
	34	struct device *dev;
	35	struct mutex irq_lock;
1dfb4a0d	36	u32 norequest_mask;
03f822f5 RV	37	/* Caches of interrupt control registers for bus_lock */
	38	u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
	39	u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
	40	};
	41
03f822f5 RV	42	static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
03f822f5 RV	43	{
b03c04a0	44	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5	45	struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d	46	u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
4e2678b5	47	u8 mask = BIT(offset % 8);
03f822f5 RV	48	int ret;
	49
	50	ret = stmpe_reg_read(stmpe, reg);
	51	if (ret < 0)
	52	return ret;
	53
7535b8be	54	return !!(ret & mask);
03f822f5 RV	55	}
	56
	57	static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
	58	{
b03c04a0	59	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5 RV	60	struct stmpe *stmpe = stmpe_gpio->stmpe;
03f822f5 RV	61	int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
43db289d	62	u8 reg = stmpe->regs[which + (offset / 8)];
4e2678b5	63	u8 mask = BIT(offset % 8);
03f822f5	64
cccdceb9 VK	65	/*
	66	* Some variants have single register for gpio set/clear functionality.
	67	* For them we need to write 0 to clear and 1 to set.
	68	*/
	69	if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
	70	stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
	71	else
	72	stmpe_reg_write(stmpe, reg, mask);
03f822f5 RV	73	}
03f822f5 RV	74
8e293fb0 LW	75	static int stmpe_gpio_get_direction(struct gpio_chip *chip,
	76	unsigned offset)
	77	{
	78	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
	79	struct stmpe *stmpe = stmpe_gpio->stmpe;
	80	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
4e2678b5	81	u8 mask = BIT(offset % 8);
8e293fb0 LW	82	int ret;
	83
	84	ret = stmpe_reg_read(stmpe, reg);
	85	if (ret < 0)
	86	return ret;
	87
e42615ec MV	88	if (ret & mask)
	89	return GPIO_LINE_DIRECTION_OUT;
	90
	91	return GPIO_LINE_DIRECTION_IN;
8e293fb0 LW	92	}
8e293fb0 LW	93
03f822f5 RV	94	static int stmpe_gpio_direction_output(struct gpio_chip *chip,
	95	unsigned offset, int val)
	96	{
b03c04a0	97	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5	98	struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d	99	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
4e2678b5	100	u8 mask = BIT(offset % 8);
03f822f5 RV	101
	102	stmpe_gpio_set(chip, offset, val);
	103
	104	return stmpe_set_bits(stmpe, reg, mask, mask);
	105	}
	106
	107	static int stmpe_gpio_direction_input(struct gpio_chip *chip,
	108	unsigned offset)
	109	{
b03c04a0	110	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5	111	struct stmpe *stmpe = stmpe_gpio->stmpe;
43db289d	112	u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
4e2678b5	113	u8 mask = BIT(offset % 8);
03f822f5 RV	114
	115	return stmpe_set_bits(stmpe, reg, mask, 0);
	116	}
	117
03f822f5 RV	118	static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
03f822f5 RV	119	{
b03c04a0	120	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
03f822f5 RV	121	struct stmpe *stmpe = stmpe_gpio->stmpe;
03f822f5 RV	122
4e2678b5	123	if (stmpe_gpio->norequest_mask & BIT(offset))
b8e9cf0b WS	124	return -EINVAL;
b8e9cf0b WS	125
4e2678b5	126	return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
03f822f5 RV	127	}
03f822f5 RV	128
e35b5ab0	129	static const struct gpio_chip template_chip = {
03f822f5 RV	130	.label = "stmpe",
03f822f5 RV	131	.owner = THIS_MODULE,
8e293fb0	132	.get_direction = stmpe_gpio_get_direction,
03f822f5 RV	133	.direction_input = stmpe_gpio_direction_input,
	134	.get = stmpe_gpio_get,
	135	.direction_output = stmpe_gpio_direction_output,
	136	.set = stmpe_gpio_set,
03f822f5	137	.request = stmpe_gpio_request,
9fb1f39e	138	.can_sleep = true,
03f822f5 RV	139	};
03f822f5 RV	140
2a866f39	141	static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
03f822f5	142	{
fe44e70d	143	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	144	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
fc13d5a5	145	int offset = d->hwirq;
03f822f5	146	int regoffset = offset / 8;
4e2678b5	147	int mask = BIT(offset % 8);
03f822f5	148
1fe3bd9e	149	if (type & IRQ_TYPE_LEVEL_LOW \|\| type & IRQ_TYPE_LEVEL_HIGH)
03f822f5 RV	150	return -EINVAL;
03f822f5 RV	151
c6a05a05 PC	152	/* STMPE801 and STMPE 1600 don't have RE and FE registers */
	153	if (stmpe_gpio->stmpe->partnum == STMPE801 \|\|
	154	stmpe_gpio->stmpe->partnum == STMPE1600)
cccdceb9 VK	155	return 0;
cccdceb9 VK	156
1fe3bd9e	157	if (type & IRQ_TYPE_EDGE_RISING)
03f822f5 RV	158	stmpe_gpio->regs[REG_RE][regoffset] \|= mask;
	159	else
	160	stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
	161
1fe3bd9e	162	if (type & IRQ_TYPE_EDGE_FALLING)
03f822f5 RV	163	stmpe_gpio->regs[REG_FE][regoffset] \|= mask;
	164	else
	165	stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
	166
	167	return 0;
	168	}
	169
2a866f39	170	static void stmpe_gpio_irq_lock(struct irq_data *d)
03f822f5	171	{
fe44e70d	172	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	173	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
03f822f5 RV	174
	175	mutex_lock(&stmpe_gpio->irq_lock);
	176	}
	177
2a866f39	178	static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
03f822f5	179	{
fe44e70d	180	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	181	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
03f822f5 RV	182	struct stmpe *stmpe = stmpe_gpio->stmpe;
03f822f5 RV	183	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
43db289d PC	184	static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
	185	[REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
	186	[REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
	187	[REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
	188	[REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
	189	[REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
	190	[REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
	191	[REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
	192	[REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
	193	[REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
03f822f5 RV	194	};
	195	int i, j;
	196
b888fb6f PC	197	/*
	198	* STMPE1600: to be able to get IRQ from pins,
	199	* a read must be done on GPMR register, or a write in
	200	* GPSR or GPCR registers
	201	*/
	202	if (stmpe->partnum == STMPE1600) {
	203	stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
	204	stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
	205	}
	206
03f822f5	207	for (i = 0; i < CACHE_NR_REGS; i++) {
c6a05a05 PC	208	/* STMPE801 and STMPE1600 don't have RE and FE registers */
	209	if ((stmpe->partnum == STMPE801 \|\|
	210	stmpe->partnum == STMPE1600) &&
	211	(i != REG_IE))
cccdceb9 VK	212	continue;
cccdceb9 VK	213
03f822f5 RV	214	for (j = 0; j < num_banks; j++) {
	215	u8 old = stmpe_gpio->oldregs[i][j];
	216	u8 new = stmpe_gpio->regs[i][j];
	217
	218	if (new == old)
	219	continue;
	220
	221	stmpe_gpio->oldregs[i][j] = new;
43db289d	222	stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
03f822f5 RV	223	}
	224	}
	225
	226	mutex_unlock(&stmpe_gpio->irq_lock);
	227	}
	228
2a866f39	229	static void stmpe_gpio_irq_mask(struct irq_data *d)
03f822f5	230	{
fe44e70d	231	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	232	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
fc13d5a5	233	int offset = d->hwirq;
03f822f5	234	int regoffset = offset / 8;
4e2678b5	235	int mask = BIT(offset % 8);
03f822f5 RV	236
03f822f5 RV	237	stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
32585b56	238	gpiochip_disable_irq(gc, offset);
03f822f5 RV	239	}
03f822f5 RV	240
2a866f39	241	static void stmpe_gpio_irq_unmask(struct irq_data *d)
03f822f5	242	{
fe44e70d	243	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
b03c04a0	244	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
fc13d5a5	245	int offset = d->hwirq;
03f822f5	246	int regoffset = offset / 8;
4e2678b5	247	int mask = BIT(offset % 8);
03f822f5	248
32585b56	249	gpiochip_enable_irq(gc, offset);
03f822f5 RV	250	stmpe_gpio->regs[REG_IE][regoffset] \|= mask;
	251	}
	252
27ec8a9c LW	253	static void stmpe_dbg_show_one(struct seq_file *s,
	254	struct gpio_chip *gc,
	255	unsigned offset, unsigned gpio)
	256	{
b03c04a0	257	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
27ec8a9c	258	struct stmpe *stmpe = stmpe_gpio->stmpe;
27ec8a9c	259	bool val = !!stmpe_gpio_get(gc, offset);
43db289d PC	260	u8 bank = offset / 8;
43db289d PC	261	u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
4e2678b5	262	u8 mask = BIT(offset % 8);
27ec8a9c LW	263	int ret;
	264	u8 dir;
	265
f1b33ce4 BG	266	char *label __free(kfree) = gpiochip_dup_line_label(gc, offset);
	267	if (IS_ERR(label))
	268	return;
	269
27ec8a9c LW	270	ret = stmpe_reg_read(stmpe, dir_reg);
	271	if (ret < 0)
	272	return;
	273	dir = !!(ret & mask);
	274
	275	if (dir) {
	276	seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
	277	gpio, label ?: "(none)",
	278	val ? "hi" : "lo");
	279	} else {
287849cb PC	280	u8 edge_det_reg;
	281	u8 rise_reg;
	282	u8 fall_reg;
	283	u8 irqen_reg;
	284
e2843cb6 CIK	285	static const char * const edge_det_values[] = {
	286	"edge-inactive",
	287	"edge-asserted",
	288	"not-supported"
	289	};
	290	static const char * const rise_values[] = {
	291	"no-rising-edge-detection",
	292	"rising-edge-detection",
	293	"not-supported"
	294	};
	295	static const char * const fall_values[] = {
	296	"no-falling-edge-detection",
	297	"falling-edge-detection",
	298	"not-supported"
	299	};
287849cb PC	300	#define NOT_SUPPORTED_IDX 2
	301	u8 edge_det = NOT_SUPPORTED_IDX;
	302	u8 rise = NOT_SUPPORTED_IDX;
	303	u8 fall = NOT_SUPPORTED_IDX;
27ec8a9c LW	304	bool irqen;
27ec8a9c LW	305
287849cb PC	306	switch (stmpe->partnum) {
	307	case STMPE610:
	308	case STMPE811:
	309	case STMPE1601:
	310	case STMPE2401:
	311	case STMPE2403:
43db289d	312	edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
287849cb PC	313	ret = stmpe_reg_read(stmpe, edge_det_reg);
	314	if (ret < 0)
	315	return;
	316	edge_det = !!(ret & mask);
df561f66	317	fallthrough;
287849cb	318	case STMPE1801:
43db289d PC	319	rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
	320	fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
	321
287849cb PC	322	ret = stmpe_reg_read(stmpe, rise_reg);
	323	if (ret < 0)
	324	return;
	325	rise = !!(ret & mask);
	326	ret = stmpe_reg_read(stmpe, fall_reg);
	327	if (ret < 0)
	328	return;
	329	fall = !!(ret & mask);
df561f66	330	fallthrough;
287849cb	331	case STMPE801:
c6a05a05	332	case STMPE1600:
43db289d	333	irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
287849cb PC	334	break;
	335
	336	default:
27ec8a9c	337	return;
287849cb PC	338	}
287849cb PC	339
27ec8a9c LW	340	ret = stmpe_reg_read(stmpe, irqen_reg);
	341	if (ret < 0)
	342	return;
	343	irqen = !!(ret & mask);
	344
287849cb	345	seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
27ec8a9c LW	346	gpio, label ?: "(none)",
27ec8a9c LW	347	val ? "hi" : "lo",
287849cb PC	348	edge_det_values[edge_det],
	349	irqen ? "IRQ-enabled" : "IRQ-disabled",
	350	rise_values[rise],
	351	fall_values[fall]);
27ec8a9c LW	352	}
	353	}
	354
	355	static void stmpe_dbg_show(struct seq_file s, struct gpio_chip gc)
	356	{
	357	unsigned i;
	358	unsigned gpio = gc->base;
	359
	360	for (i = 0; i < gc->ngpio; i++, gpio++) {
	361	stmpe_dbg_show_one(s, gc, i, gpio);
0d83a5eb	362	seq_putc(s, '\n');
27ec8a9c LW	363	}
	364	}
	365
32585b56	366	static const struct irq_chip stmpe_gpio_irq_chip = {
03f822f5	367	.name = "stmpe-gpio",
2a866f39 LB	368	.irq_bus_lock = stmpe_gpio_irq_lock,
	369	.irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
	370	.irq_mask = stmpe_gpio_irq_mask,
	371	.irq_unmask = stmpe_gpio_irq_unmask,
	372	.irq_set_type = stmpe_gpio_irq_set_type,
32585b56 LW	373	.flags = IRQCHIP_IMMUTABLE,
32585b56 LW	374	GPIOCHIP_IRQ_RESOURCE_HELPERS,
03f822f5 RV	375	};
03f822f5 RV	376
97fe7bef LA	377	#define MAX_GPIOS 24
97fe7bef LA	378
03f822f5 RV	379	static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
	380	{
	381	struct stmpe_gpio *stmpe_gpio = dev;
	382	struct stmpe *stmpe = stmpe_gpio->stmpe;
c6a05a05	383	u8 statmsbreg;
03f822f5	384	int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
97fe7bef	385	u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
03f822f5 RV	386	int ret;
	387	int i;
	388
c6a05a05 PC	389	/*
	390	* the stmpe_block_read() call below, imposes to set statmsbreg
	391	* with the register located at the lowest address. As STMPE1600
	392	* variant is the only one which respect registers address's order
	393	* (LSB regs located at lowest address than MSB ones) whereas all
	394	* the others have a registers layout with MSB located before the
	395	* LSB regs.
	396	*/
	397	if (stmpe->partnum == STMPE1600)
	398	statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
	399	else
	400	statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
	401
03f822f5 RV	402	ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
	403	if (ret < 0)
	404	return IRQ_NONE;
	405
	406	for (i = 0; i < num_banks; i++) {
c6a05a05 PC	407	int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
c6a05a05 PC	408	num_banks - i - 1;
03f822f5 RV	409	unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
	410	unsigned int stat = status[i];
	411
	412	stat &= enabled;
	413	if (!stat)
	414	continue;
	415
	416	while (stat) {
	417	int bit = __ffs(stat);
	418	int line = bank * 8 + bit;
f0fbe7bc	419	int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
ed05e204	420	line);
03f822f5	421
ed05e204	422	handle_nested_irq(child_irq);
4e2678b5	423	stat &= ~BIT(bit);
03f822f5 RV	424	}
03f822f5 RV	425
6936e1f8 PC	426	/*
6936e1f8 PC	427	* interrupt status register write has no effect on
c6a05a05 PC	428	* 801/1801/1600, bits are cleared when read.
c6a05a05 PC	429	* Edge detect register is not present on 801/1600/1801
6936e1f8	430	*/
d1ca19cb	431	if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
c6a05a05	432	stmpe->partnum != STMPE1801) {
6936e1f8	433	stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
43db289d	434	stmpe_reg_write(stmpe,
1516c635	435	stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
43db289d	436	status[i]);
6936e1f8	437	}
03f822f5 RV	438	}
	439
	440	return IRQ_HANDLED;
	441	}
	442
5fbe5b58 LW	443	static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
	444	unsigned long *valid_mask,
	445	unsigned int ngpios)
	446	{
	447	struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
	448	int i;
	449
	450	if (!stmpe_gpio->norequest_mask)
	451	return;
	452
	453	/* Forbid unused lines to be mapped as IRQs */
	454	for (i = 0; i < sizeof(u32); i++) {
	455	if (stmpe_gpio->norequest_mask & BIT(i))
	456	clear_bit(i, valid_mask);
	457	}
	458	}
	459
2a9a2cca AA	460	static void stmpe_gpio_disable(void *stmpe)
	461	{
	462	stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
	463	}
	464
3836309d	465	static int stmpe_gpio_probe(struct platform_device *pdev)
03f822f5 RV	466	{
03f822f5 RV	467	struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
86605cfe	468	struct device_node *np = pdev->dev.of_node;
03f822f5	469	struct stmpe_gpio *stmpe_gpio;
0f719231	470	int ret, irq;
03f822f5	471
97fe7bef LA	472	if (stmpe->num_gpios > MAX_GPIOS) {
	473	dev_err(&pdev->dev, "Need to increase maximum GPIO number\n");
	474	return -EINVAL;
	475	}
	476
2a9a2cca	477	stmpe_gpio = devm_kzalloc(&pdev->dev, sizeof(*stmpe_gpio), GFP_KERNEL);
03f822f5 RV	478	if (!stmpe_gpio)
	479	return -ENOMEM;
	480
	481	mutex_init(&stmpe_gpio->irq_lock);
	482
	483	stmpe_gpio->dev = &pdev->dev;
	484	stmpe_gpio->stmpe = stmpe;
03f822f5 RV	485	stmpe_gpio->chip = template_chip;
03f822f5 RV	486	stmpe_gpio->chip.ngpio = stmpe->num_gpios;
58383c78	487	stmpe_gpio->chip.parent = &pdev->dev;
9e9dc7d9	488	stmpe_gpio->chip.base = -1;
03f822f5	489
27ec8a9c LW	490	if (IS_ENABLED(CONFIG_DEBUG_FS))
	491	stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
	492
1dfb4a0d LW	493	of_property_read_u32(np, "st,norequest-mask",
1dfb4a0d LW	494	&stmpe_gpio->norequest_mask);
86605cfe	495
757ad058	496	irq = platform_get_irq(pdev, 0);
9e9dc7d9	497	if (irq < 0)
38040c85	498	dev_info(&pdev->dev,
fe44e70d	499	"device configured in no-irq mode: "
38040c85	500	"irqs are not available\n");
03f822f5 RV	501
	502	ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
	503	if (ret)
2a9a2cca AA	504	return ret;
	505
	506	ret = devm_add_action_or_reset(&pdev->dev, stmpe_gpio_disable, stmpe);
	507	if (ret)
	508	return ret;
03f822f5	509
fe44e70d	510	if (irq > 0) {
97450796 LW	511	struct gpio_irq_chip *girq;
97450796 LW	512
fe44e70d LW	513	ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
	514	stmpe_gpio_irq, IRQF_ONESHOT,
	515	"stmpe-gpio", stmpe_gpio);
38040c85 CB	516	if (ret) {
38040c85 CB	517	dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
2a9a2cca	518	return ret;
38040c85	519	}
03f822f5	520
97450796	521	girq = &stmpe_gpio->chip.irq;
32585b56	522	gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip);
97450796 LW	523	/* This will let us handle the parent IRQ in the driver */
	524	girq->parent_handler = NULL;
	525	girq->num_parents = 0;
	526	girq->parents = NULL;
	527	girq->default_type = IRQ_TYPE_NONE;
	528	girq->handler = handle_simple_irq;
	529	girq->threaded = true;
8aa16335	530	girq->init_valid_mask = stmpe_init_irq_valid_mask;
03f822f5 RV	531	}
03f822f5 RV	532
2a9a2cca	533	return devm_gpiochip_add_data(&pdev->dev, &stmpe_gpio->chip, stmpe_gpio);
03f822f5 RV	534	}
03f822f5 RV	535
03f822f5	536	static struct platform_driver stmpe_gpio_driver = {
3b52bb96 PG	537	.driver = {
	538	.suppress_bind_attrs = true,
	539	.name = "stmpe-gpio",
3b52bb96	540	},
03f822f5	541	.probe = stmpe_gpio_probe,
03f822f5 RV	542	};
	543
	544	static int __init stmpe_gpio_init(void)
	545	{
	546	return platform_driver_register(&stmpe_gpio_driver);
	547	}
	548	subsys_initcall(stmpe_gpio_init);