[linux-2.6-block.git] / drivers / gpio / gpio-sta2x11.c

/*
 * STMicroelectronics ConneXt (STA2X11) GPIO driver
 *
 * Copyright 2012 ST Microelectronics (Alessandro Rubini)
 * Based on gpio-ml-ioh.c, Copyright 2010 OKI Semiconductors Ltd.
 * Also based on previous sta2x11 work, Copyright 2011 Wind River Systems, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
 * See the GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 */

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/gpio/driver.h>
#include <linux/bitops.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/mfd/sta2x11-mfd.h>

struct gsta_regs {
	u32 dat;		/* 0x00 */
	u32 dats;
	u32 datc;
	u32 pdis;
	u32 dir;		/* 0x10 */
	u32 dirs;
	u32 dirc;
	u32 unused_1c;
	u32 afsela;		/* 0x20 */
	u32 unused_24[7];
	u32 rimsc;		/* 0x40 */
	u32 fimsc;
	u32 is;
	u32 ic;
};

struct gsta_gpio {
	spinlock_t			lock;
	struct device			*dev;
	void __iomem			*reg_base;
	struct gsta_regs __iomem	*regs[GSTA_NR_BLOCKS];
	struct gpio_chip		gpio;
	int				irq_base;
	/* FIXME: save the whole config here (AF, ...) */
	unsigned			irq_type[GSTA_NR_GPIO];
};

/*
 * gpio methods
 */

static void gsta_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
{
	struct gsta_gpio *chip = gpiochip_get_data(gpio);
	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);

	if (val)
		writel(bit, &regs->dats);
	else
		writel(bit, &regs->datc);
}

static int gsta_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
	struct gsta_gpio *chip = gpiochip_get_data(gpio);
	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);

	return !!(readl(&regs->dat) & bit);
}

static int gsta_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
				      int val)
{
	struct gsta_gpio *chip = gpiochip_get_data(gpio);
	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);

	writel(bit, &regs->dirs);
	/* Data register after direction, otherwise pullup/down is selected */
	if (val)
		writel(bit, &regs->dats);
	else
		writel(bit, &regs->datc);
	return 0;
}

static int gsta_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	struct gsta_gpio *chip = gpiochip_get_data(gpio);
	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);

	writel(bit, &regs->dirc);
	return 0;
}

static int gsta_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
	struct gsta_gpio *chip = gpiochip_get_data(gpio);
	return chip->irq_base + offset;
}

static void gsta_gpio_setup(struct gsta_gpio *chip) /* called from probe */
{
	struct gpio_chip *gpio = &chip->gpio;

	/*
	 * ARCH_NR_GPIOS is currently 256 and dynamic allocation starts
	 * from the end. However, for compatibility, we need the first
	 * ConneXt device to start from gpio 0: it's the main chipset
	 * on most boards so documents and drivers assume gpio0..gpio127
	 */
	static int gpio_base;

	gpio->label = dev_name(chip->dev);
	gpio->owner = THIS_MODULE;
	gpio->direction_input = gsta_gpio_direction_input;
	gpio->get = gsta_gpio_get;
	gpio->direction_output = gsta_gpio_direction_output;
	gpio->set = gsta_gpio_set;
	gpio->dbg_show = NULL;
	gpio->base = gpio_base;
	gpio->ngpio = GSTA_NR_GPIO;
	gpio->can_sleep = false;
	gpio->to_irq = gsta_gpio_to_irq;

	/*
	 * After the first device, turn to dynamic gpio numbers.
	 * For example, with ARCH_NR_GPIOS = 256 we can fit two cards
	 */
	if (!gpio_base)
		gpio_base = -1;
}

/*
 * Special method: alternate functions and pullup/pulldown. This is only
 * invoked on startup to configure gpio's according to platform data.
 * FIXME : this functionality shall be managed (and exported to other drivers)
 * via the pin control subsystem.
 */
static void gsta_set_config(struct gsta_gpio *chip, int nr, unsigned cfg)
{
	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
	unsigned long flags;
	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
	u32 val;
	int err = 0;

	pr_info("%s: %p %i %i\n", __func__, chip, nr, cfg);

	if (cfg == PINMUX_TYPE_NONE)
		return;

	/* Alternate function or not? */
	spin_lock_irqsave(&chip->lock, flags);
	val = readl(&regs->afsela);
	if (cfg == PINMUX_TYPE_FUNCTION)
		val |= bit;
	else
		val &= ~bit;
	writel(val | bit, &regs->afsela);
	if (cfg == PINMUX_TYPE_FUNCTION) {
		spin_unlock_irqrestore(&chip->lock, flags);
		return;
	}

	/* not alternate function: set details */
	switch (cfg) {
	case PINMUX_TYPE_OUTPUT_LOW:
		writel(bit, &regs->dirs);
		writel(bit, &regs->datc);
		break;
	case PINMUX_TYPE_OUTPUT_HIGH:
		writel(bit, &regs->dirs);
		writel(bit, &regs->dats);
		break;
	case PINMUX_TYPE_INPUT:
		writel(bit, &regs->dirc);
		val = readl(&regs->pdis) | bit;
		writel(val, &regs->pdis);
		break;
	case PINMUX_TYPE_INPUT_PULLUP:
		writel(bit, &regs->dirc);
		val = readl(&regs->pdis) & ~bit;
		writel(val, &regs->pdis);
		writel(bit, &regs->dats);
		break;
	case PINMUX_TYPE_INPUT_PULLDOWN:
		writel(bit, &regs->dirc);
		val = readl(&regs->pdis) & ~bit;
		writel(val, &regs->pdis);
		writel(bit, &regs->datc);
		break;
	default:
		err = 1;
	}
	spin_unlock_irqrestore(&chip->lock, flags);
	if (err)
		pr_err("%s: chip %p, pin %i, cfg %i is invalid\n",
		       __func__, chip, nr, cfg);
}

/*
 * Irq methods
 */

static void gsta_irq_disable(struct irq_data *data)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
	struct gsta_gpio *chip = gc->private;
	int nr = data->irq - chip->irq_base;
	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
	u32 val;
	unsigned long flags;

	spin_lock_irqsave(&chip->lock, flags);
	if (chip->irq_type[nr] & IRQ_TYPE_EDGE_RISING) {
		val = readl(&regs->rimsc) & ~bit;
		writel(val, &regs->rimsc);
	}
	if (chip->irq_type[nr] & IRQ_TYPE_EDGE_FALLING) {
		val = readl(&regs->fimsc) & ~bit;
		writel(val, &regs->fimsc);
	}
	spin_unlock_irqrestore(&chip->lock, flags);
	return;
}

static void gsta_irq_enable(struct irq_data *data)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
	struct gsta_gpio *chip = gc->private;
	int nr = data->irq - chip->irq_base;
	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
	u32 val;
	int type;
	unsigned long flags;

	type = chip->irq_type[nr];

	spin_lock_irqsave(&chip->lock, flags);
	val = readl(&regs->rimsc);
	if (type & IRQ_TYPE_EDGE_RISING)
		writel(val | bit, &regs->rimsc);
	else
		writel(val & ~bit, &regs->rimsc);
	val = readl(&regs->rimsc);
	if (type & IRQ_TYPE_EDGE_FALLING)
		writel(val | bit, &regs->fimsc);
	else
		writel(val & ~bit, &regs->fimsc);
	spin_unlock_irqrestore(&chip->lock, flags);
	return;
}

static int gsta_irq_type(struct irq_data *d, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct gsta_gpio *chip = gc->private;
	int nr = d->irq - chip->irq_base;

	/* We only support edge interrupts */
	if (!(type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) {
		pr_debug("%s: unsupported type 0x%x\n", __func__, type);
		return -EINVAL;
	}

	chip->irq_type[nr] = type; /* used for enable/disable */

	gsta_irq_enable(d);
	return 0;
}

static irqreturn_t gsta_gpio_handler(int irq, void *dev_id)
{
	struct gsta_gpio *chip = dev_id;
	struct gsta_regs __iomem *regs;
	u32 is;
	int i, nr, base;
	irqreturn_t ret = IRQ_NONE;

	for (i = 0; i < GSTA_NR_BLOCKS; i++) {
		regs = chip->regs[i];
		base = chip->irq_base + i * GSTA_GPIO_PER_BLOCK;
		while ((is = readl(&regs->is))) {
			nr = __ffs(is);
			irq = base + nr;
			generic_handle_irq(irq);
			writel(1 << nr, &regs->ic);
			ret = IRQ_HANDLED;
		}
	}
	return ret;
}

static int gsta_alloc_irq_chip(struct gsta_gpio *chip)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int rv;

	gc = devm_irq_alloc_generic_chip(chip->dev, KBUILD_MODNAME, 1,
					 chip->irq_base,
					 chip->reg_base, handle_simple_irq);
	if (!gc)
		return -ENOMEM;

	gc->private = chip;
	ct = gc->chip_types;

	ct->chip.irq_set_type = gsta_irq_type;
	ct->chip.irq_disable = gsta_irq_disable;
	ct->chip.irq_enable = gsta_irq_enable;

	/* FIXME: this makes at most 32 interrupts. Request 0 by now */
	rv = devm_irq_setup_generic_chip(chip->dev, gc,
					 0 /* IRQ_MSK(GSTA_GPIO_PER_BLOCK) */,
					 0, IRQ_NOREQUEST | IRQ_NOPROBE, 0);
	if (rv)
		return rv;

	/* Set up all all 128 interrupts: code from setup_generic_chip */
	{
		struct irq_chip_type *ct = gc->chip_types;
		int i, j;
		for (j = 0; j < GSTA_NR_GPIO; j++) {
			i = chip->irq_base + j;
			irq_set_chip_and_handler(i, &ct->chip, ct->handler);
			irq_set_chip_data(i, gc);
			irq_clear_status_flags(i, IRQ_NOREQUEST | IRQ_NOPROBE);
		}
		gc->irq_cnt = i - gc->irq_base;
	}

	return 0;
}

/* The platform device used here is instantiated by the MFD device */
static int gsta_probe(struct platform_device *dev)
{
	int i, err;
	struct pci_dev *pdev;
	struct sta2x11_gpio_pdata *gpio_pdata;
	struct gsta_gpio *chip;
	struct resource *res;

	pdev = *(struct pci_dev **)dev_get_platdata(&dev->dev);
	gpio_pdata = dev_get_platdata(&pdev->dev);

	if (gpio_pdata == NULL)
		dev_err(&dev->dev, "no gpio config\n");
	pr_debug("gpio config: %p\n", gpio_pdata);

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);

	chip = devm_kzalloc(&dev->dev, sizeof(*chip), GFP_KERNEL);
	if (!chip)
		return -ENOMEM;
	chip->dev = &dev->dev;
	chip->reg_base = devm_ioremap_resource(&dev->dev, res);
	if (IS_ERR(chip->reg_base))
		return PTR_ERR(chip->reg_base);

	for (i = 0; i < GSTA_NR_BLOCKS; i++) {
		chip->regs[i] = chip->reg_base + i * 4096;
		/* disable all irqs */
		writel(0, &chip->regs[i]->rimsc);
		writel(0, &chip->regs[i]->fimsc);
		writel(~0, &chip->regs[i]->ic);
	}
	spin_lock_init(&chip->lock);
	gsta_gpio_setup(chip);
	if (gpio_pdata)
		for (i = 0; i < GSTA_NR_GPIO; i++)
			gsta_set_config(chip, i, gpio_pdata->pinconfig[i]);

	/* 384 was used in previous code: be compatible for other drivers */
	err = devm_irq_alloc_descs(&dev->dev, -1, 384,
				   GSTA_NR_GPIO, NUMA_NO_NODE);
	if (err < 0) {
		dev_warn(&dev->dev, "sta2x11 gpio: Can't get irq base (%i)\n",
			 -err);
		return err;
	}
	chip->irq_base = err;

	err = gsta_alloc_irq_chip(chip);
	if (err)
		return err;

	err = devm_request_irq(&dev->dev, pdev->irq, gsta_gpio_handler,
			       IRQF_SHARED, KBUILD_MODNAME, chip);
	if (err < 0) {
		dev_err(&dev->dev, "sta2x11 gpio: Can't request irq (%i)\n",
			-err);
		return err;
	}

	err = devm_gpiochip_add_data(&dev->dev, &chip->gpio, chip);
	if (err < 0) {
		dev_err(&dev->dev, "sta2x11 gpio: Can't register (%i)\n",
			-err);
		return err;
	}

	platform_set_drvdata(dev, chip);
	return 0;
}

static struct platform_driver sta2x11_gpio_platform_driver = {
	.driver = {
		.name	= "sta2x11-gpio",
		.suppress_bind_attrs = true,
	},
	.probe = gsta_probe,
};
builtin_platform_driver(sta2x11_gpio_platform_driver);
Commit	Line	Data
7b0d44f3 AR	1	/*
	2	* STMicroelectronics ConneXt (STA2X11) GPIO driver
	3	*
	4	* Copyright 2012 ST Microelectronics (Alessandro Rubini)
	5	* Based on gpio-ml-ioh.c, Copyright 2010 OKI Semiconductors Ltd.
	6	* Also based on previous sta2x11 work, Copyright 2011 Wind River Systems, Inc.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
	15	* See the GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*
	21	*/
	22
3c90c6d6	23	#include <linux/init.h>
7b0d44f3 AR	24	#include <linux/kernel.h>
7b0d44f3 AR	25	#include <linux/slab.h>
25fc1778	26	#include <linux/gpio/driver.h>
24dcfd84	27	#include <linux/bitops.h>
7b0d44f3 AR	28	#include <linux/interrupt.h>
	29	#include <linux/irq.h>
	30	#include <linux/pci.h>
	31	#include <linux/platform_device.h>
	32	#include <linux/mfd/sta2x11-mfd.h>
	33
	34	struct gsta_regs {
	35	u32 dat; /* 0x00 */
	36	u32 dats;
	37	u32 datc;
	38	u32 pdis;
	39	u32 dir; /* 0x10 */
	40	u32 dirs;
	41	u32 dirc;
	42	u32 unused_1c;
	43	u32 afsela; /* 0x20 */
	44	u32 unused_24[7];
	45	u32 rimsc; /* 0x40 */
	46	u32 fimsc;
	47	u32 is;
	48	u32 ic;
	49	};
	50
	51	struct gsta_gpio {
	52	spinlock_t lock;
	53	struct device *dev;
	54	void __iomem *reg_base;
	55	struct gsta_regs __iomem *regs[GSTA_NR_BLOCKS];
	56	struct gpio_chip gpio;
	57	int irq_base;
	58	/* FIXME: save the whole config here (AF, ...) */
	59	unsigned irq_type[GSTA_NR_GPIO];
	60	};
	61
7b0d44f3 AR	62	/*
	63	* gpio methods
	64	*/
	65
	66	static void gsta_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
	67	{
0b2c529a	68	struct gsta_gpio *chip = gpiochip_get_data(gpio);
aadf77c8	69	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
24dcfd84	70	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
7b0d44f3 AR	71
	72	if (val)
	73	writel(bit, &regs->dats);
	74	else
	75	writel(bit, &regs->datc);
	76	}
	77
	78	static int gsta_gpio_get(struct gpio_chip *gpio, unsigned nr)
	79	{
0b2c529a	80	struct gsta_gpio *chip = gpiochip_get_data(gpio);
aadf77c8	81	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
24dcfd84	82	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
7b0d44f3	83
8a240c31	84	return !!(readl(&regs->dat) & bit);
7b0d44f3 AR	85	}
	86
	87	static int gsta_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
	88	int val)
	89	{
0b2c529a	90	struct gsta_gpio *chip = gpiochip_get_data(gpio);
aadf77c8	91	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
24dcfd84	92	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
7b0d44f3 AR	93
	94	writel(bit, &regs->dirs);
	95	/* Data register after direction, otherwise pullup/down is selected */
	96	if (val)
	97	writel(bit, &regs->dats);
	98	else
	99	writel(bit, &regs->datc);
	100	return 0;
	101	}
	102
	103	static int gsta_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	104	{
0b2c529a	105	struct gsta_gpio *chip = gpiochip_get_data(gpio);
aadf77c8	106	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
24dcfd84	107	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
7b0d44f3 AR	108
	109	writel(bit, &regs->dirc);
	110	return 0;
	111	}
	112
	113	static int gsta_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
	114	{
0b2c529a	115	struct gsta_gpio *chip = gpiochip_get_data(gpio);
7b0d44f3 AR	116	return chip->irq_base + offset;
	117	}
	118
	119	static void gsta_gpio_setup(struct gsta_gpio chip) / called from probe */
	120	{
	121	struct gpio_chip *gpio = &chip->gpio;
	122
	123	/*
	124	* ARCH_NR_GPIOS is currently 256 and dynamic allocation starts
	125	* from the end. However, for compatibility, we need the first
	126	* ConneXt device to start from gpio 0: it's the main chipset
	127	* on most boards so documents and drivers assume gpio0..gpio127
	128	*/
	129	static int gpio_base;
	130
	131	gpio->label = dev_name(chip->dev);
	132	gpio->owner = THIS_MODULE;
	133	gpio->direction_input = gsta_gpio_direction_input;
	134	gpio->get = gsta_gpio_get;
	135	gpio->direction_output = gsta_gpio_direction_output;
	136	gpio->set = gsta_gpio_set;
	137	gpio->dbg_show = NULL;
	138	gpio->base = gpio_base;
	139	gpio->ngpio = GSTA_NR_GPIO;
9fb1f39e	140	gpio->can_sleep = false;
7b0d44f3 AR	141	gpio->to_irq = gsta_gpio_to_irq;
	142
	143	/*
	144	* After the first device, turn to dynamic gpio numbers.
	145	* For example, with ARCH_NR_GPIOS = 256 we can fit two cards
	146	*/
	147	if (!gpio_base)
	148	gpio_base = -1;
	149	}
	150
	151	/*
	152	* Special method: alternate functions and pullup/pulldown. This is only
	153	* invoked on startup to configure gpio's according to platform data.
	154	* FIXME : this functionality shall be managed (and exported to other drivers)
	155	* via the pin control subsystem.
	156	*/
	157	static void gsta_set_config(struct gsta_gpio *chip, int nr, unsigned cfg)
	158	{
aadf77c8	159	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
7b0d44f3	160	unsigned long flags;
24dcfd84	161	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
7b0d44f3 AR	162	u32 val;
	163	int err = 0;
	164
	165	pr_info("%s: %p %i %i\n", __func__, chip, nr, cfg);
	166
	167	if (cfg == PINMUX_TYPE_NONE)
	168	return;
	169
	170	/* Alternate function or not? */
	171	spin_lock_irqsave(&chip->lock, flags);
	172	val = readl(&regs->afsela);
	173	if (cfg == PINMUX_TYPE_FUNCTION)
	174	val \|= bit;
	175	else
	176	val &= ~bit;
	177	writel(val \| bit, &regs->afsela);
	178	if (cfg == PINMUX_TYPE_FUNCTION) {
	179	spin_unlock_irqrestore(&chip->lock, flags);
	180	return;
	181	}
	182
	183	/* not alternate function: set details */
	184	switch (cfg) {
	185	case PINMUX_TYPE_OUTPUT_LOW:
	186	writel(bit, &regs->dirs);
	187	writel(bit, &regs->datc);
	188	break;
	189	case PINMUX_TYPE_OUTPUT_HIGH:
	190	writel(bit, &regs->dirs);
	191	writel(bit, &regs->dats);
	192	break;
	193	case PINMUX_TYPE_INPUT:
	194	writel(bit, &regs->dirc);
	195	val = readl(&regs->pdis) \| bit;
	196	writel(val, &regs->pdis);
	197	break;
	198	case PINMUX_TYPE_INPUT_PULLUP:
	199	writel(bit, &regs->dirc);
	200	val = readl(&regs->pdis) & ~bit;
	201	writel(val, &regs->pdis);
	202	writel(bit, &regs->dats);
	203	break;
	204	case PINMUX_TYPE_INPUT_PULLDOWN:
	205	writel(bit, &regs->dirc);
	206	val = readl(&regs->pdis) & ~bit;
	207	writel(val, &regs->pdis);
	208	writel(bit, &regs->datc);
	209	break;
	210	default:
	211	err = 1;
	212	}
	213	spin_unlock_irqrestore(&chip->lock, flags);
	214	if (err)
	215	pr_err("%s: chip %p, pin %i, cfg %i is invalid\n",
	216	__func__, chip, nr, cfg);
	217	}
	218
	219	/*
	220	* Irq methods
	221	*/
	222
	223	static void gsta_irq_disable(struct irq_data *data)
	224	{
	225	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
226	struct gsta_gpio *chip = gc->private;
227	int nr = data->irq - chip->irq_base;
aadf77c8	228	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
24dcfd84	229	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
7b0d44f3 AR	230	u32 val;
	231	unsigned long flags;
	232
	233	spin_lock_irqsave(&chip->lock, flags);
	234	if (chip->irq_type[nr] & IRQ_TYPE_EDGE_RISING) {
	235	val = readl(&regs->rimsc) & ~bit;
	236	writel(val, &regs->rimsc);
	237	}
	238	if (chip->irq_type[nr] & IRQ_TYPE_EDGE_FALLING) {
	239	val = readl(&regs->fimsc) & ~bit;
	240	writel(val, &regs->fimsc);
	241	}
	242	spin_unlock_irqrestore(&chip->lock, flags);
	243	return;
	244	}
	245
	246	static void gsta_irq_enable(struct irq_data *data)
	247	{
	248	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
	249	struct gsta_gpio *chip = gc->private;
	250	int nr = data->irq - chip->irq_base;
aadf77c8	251	struct gsta_regs __iomem *regs = chip->regs[nr / GSTA_GPIO_PER_BLOCK];
24dcfd84	252	u32 bit = BIT(nr % GSTA_GPIO_PER_BLOCK);
7b0d44f3 AR	253	u32 val;
	254	int type;
	255	unsigned long flags;
	256
	257	type = chip->irq_type[nr];
	258
	259	spin_lock_irqsave(&chip->lock, flags);
	260	val = readl(&regs->rimsc);
	261	if (type & IRQ_TYPE_EDGE_RISING)
	262	writel(val \| bit, &regs->rimsc);
	263	else
	264	writel(val & ~bit, &regs->rimsc);
	265	val = readl(&regs->rimsc);
	266	if (type & IRQ_TYPE_EDGE_FALLING)
	267	writel(val \| bit, &regs->fimsc);
	268	else
	269	writel(val & ~bit, &regs->fimsc);
	270	spin_unlock_irqrestore(&chip->lock, flags);
	271	return;
	272	}
	273
	274	static int gsta_irq_type(struct irq_data *d, unsigned int type)
	275	{
	276	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	277	struct gsta_gpio *chip = gc->private;
	278	int nr = d->irq - chip->irq_base;
	279
	280	/* We only support edge interrupts */
	281	if (!(type & (IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING))) {
	282	pr_debug("%s: unsupported type 0x%x\n", __func__, type);
	283	return -EINVAL;
	284	}
	285
	286	chip->irq_type[nr] = type; /* used for enable/disable */
	287
	288	gsta_irq_enable(d);
	289	return 0;
	290	}
	291
	292	static irqreturn_t gsta_gpio_handler(int irq, void *dev_id)
	293	{
	294	struct gsta_gpio *chip = dev_id;
	295	struct gsta_regs __iomem *regs;
	296	u32 is;
	297	int i, nr, base;
	298	irqreturn_t ret = IRQ_NONE;
	299
	300	for (i = 0; i < GSTA_NR_BLOCKS; i++) {
	301	regs = chip->regs[i];
	302	base = chip->irq_base + i * GSTA_GPIO_PER_BLOCK;
	303	while ((is = readl(&regs->is))) {
	304	nr = __ffs(is);
	305	irq = base + nr;
	306	generic_handle_irq(irq);
	307	writel(1 << nr, &regs->ic);
	308	ret = IRQ_HANDLED;
	309	}
	310	}
	311	return ret;
	312	}
	313
d76e8bab	314	static int gsta_alloc_irq_chip(struct gsta_gpio *chip)
7b0d44f3 AR	315	{
	316	struct irq_chip_generic *gc;
	317	struct irq_chip_type *ct;
624b5a9c	318	int rv;
7b0d44f3	319
624b5a9c BG	320	gc = devm_irq_alloc_generic_chip(chip->dev, KBUILD_MODNAME, 1,
	321	chip->irq_base,
	322	chip->reg_base, handle_simple_irq);
d76e8bab BG	323	if (!gc)
	324	return -ENOMEM;
	325
7b0d44f3 AR	326	gc->private = chip;
	327	ct = gc->chip_types;
	328
	329	ct->chip.irq_set_type = gsta_irq_type;
	330	ct->chip.irq_disable = gsta_irq_disable;
	331	ct->chip.irq_enable = gsta_irq_enable;
	332
	333	/* FIXME: this makes at most 32 interrupts. Request 0 by now */
624b5a9c BG	334	rv = devm_irq_setup_generic_chip(chip->dev, gc,
	335	0 /* IRQ_MSK(GSTA_GPIO_PER_BLOCK) */,
	336	0, IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
	337	if (rv)
	338	return rv;
7b0d44f3 AR	339
	340	/* Set up all all 128 interrupts: code from setup_generic_chip */
	341	{
	342	struct irq_chip_type *ct = gc->chip_types;
	343	int i, j;
	344	for (j = 0; j < GSTA_NR_GPIO; j++) {
	345	i = chip->irq_base + j;
	346	irq_set_chip_and_handler(i, &ct->chip, ct->handler);
	347	irq_set_chip_data(i, gc);
23393d49	348	irq_clear_status_flags(i, IRQ_NOREQUEST \| IRQ_NOPROBE);
7b0d44f3 AR	349	}
	350	gc->irq_cnt = i - gc->irq_base;
	351	}
d76e8bab BG	352
d76e8bab BG	353	return 0;
7b0d44f3 AR	354	}
	355
	356	/* The platform device used here is instantiated by the MFD device */
3836309d	357	static int gsta_probe(struct platform_device *dev)
7b0d44f3 AR	358	{
	359	int i, err;
	360	struct pci_dev *pdev;
	361	struct sta2x11_gpio_pdata *gpio_pdata;
	362	struct gsta_gpio *chip;
	363	struct resource *res;
	364
e56aee18	365	pdev = (struct pci_dev *)dev_get_platdata(&dev->dev);
7b0d44f3 AR	366	gpio_pdata = dev_get_platdata(&pdev->dev);
	367
	368	if (gpio_pdata == NULL)
	369	dev_err(&dev->dev, "no gpio config\n");
	370	pr_debug("gpio config: %p\n", gpio_pdata);
	371
	372	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	373
	374	chip = devm_kzalloc(&dev->dev, sizeof(*chip), GFP_KERNEL);
cd738916 SK	375	if (!chip)
cd738916 SK	376	return -ENOMEM;
7b0d44f3	377	chip->dev = &dev->dev;
62ffac14 TB	378	chip->reg_base = devm_ioremap_resource(&dev->dev, res);
	379	if (IS_ERR(chip->reg_base))
	380	return PTR_ERR(chip->reg_base);
7b0d44f3 AR	381
	382	for (i = 0; i < GSTA_NR_BLOCKS; i++) {
	383	chip->regs[i] = chip->reg_base + i * 4096;
	384	/* disable all irqs */
	385	writel(0, &chip->regs[i]->rimsc);
	386	writel(0, &chip->regs[i]->fimsc);
	387	writel(~0, &chip->regs[i]->ic);
	388	}
	389	spin_lock_init(&chip->lock);
	390	gsta_gpio_setup(chip);
2e2070c8 AR	391	if (gpio_pdata)
	392	for (i = 0; i < GSTA_NR_GPIO; i++)
	393	gsta_set_config(chip, i, gpio_pdata->pinconfig[i]);
7b0d44f3 AR	394
7b0d44f3 AR	395	/* 384 was used in previous code: be compatible for other drivers */
7ad63c79 BG	396	err = devm_irq_alloc_descs(&dev->dev, -1, 384,
7ad63c79 BG	397	GSTA_NR_GPIO, NUMA_NO_NODE);
7b0d44f3 AR	398	if (err < 0) {
	399	dev_warn(&dev->dev, "sta2x11 gpio: Can't get irq base (%i)\n",
	400	-err);
	401	return err;
	402	}
	403	chip->irq_base = err;
d76e8bab BG	404
	405	err = gsta_alloc_irq_chip(chip);
	406	if (err)
	407	return err;
7b0d44f3	408
7ad63c79 BG	409	err = devm_request_irq(&dev->dev, pdev->irq, gsta_gpio_handler,
7ad63c79 BG	410	IRQF_SHARED, KBUILD_MODNAME, chip);
7b0d44f3 AR	411	if (err < 0) {
	412	dev_err(&dev->dev, "sta2x11 gpio: Can't request irq (%i)\n",
	413	-err);
7ad63c79	414	return err;
7b0d44f3 AR	415	}
7b0d44f3 AR	416
5fa734cc	417	err = devm_gpiochip_add_data(&dev->dev, &chip->gpio, chip);
7b0d44f3 AR	418	if (err < 0) {
	419	dev_err(&dev->dev, "sta2x11 gpio: Can't register (%i)\n",
	420	-err);
7ad63c79	421	return err;
7b0d44f3 AR	422	}
	423
	424	platform_set_drvdata(dev, chip);
	425	return 0;
7b0d44f3 AR	426	}
	427
	428	static struct platform_driver sta2x11_gpio_platform_driver = {
	429	.driver = {
	430	.name = "sta2x11-gpio",
a6f5f1b9	431	.suppress_bind_attrs = true,
7b0d44f3 AR	432	},
	433	.probe = gsta_probe,
	434	};
3c90c6d6	435	builtin_platform_driver(sta2x11_gpio_platform_driver);