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b43ab901 SAS |
1 | /* |
2 | * GPIO interface for Intel Sodaville SoCs. | |
3 | * | |
4 | * Copyright (c) 2010, 2011 Intel Corporation | |
5 | * | |
6a5ead91 PG |
6 | * Author: Hans J. Koch <hjk@linutronix.de> |
7 | * | |
b43ab901 SAS |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License 2 as published | |
10 | * by the Free Software Foundation. | |
11 | * | |
12 | */ | |
13 | ||
14 | #include <linux/errno.h> | |
b43ab901 SAS |
15 | #include <linux/init.h> |
16 | #include <linux/io.h> | |
17 | #include <linux/irq.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/kernel.h> | |
b43ab901 SAS |
20 | #include <linux/pci.h> |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/of_irq.h> | |
0f4630f3 | 23 | #include <linux/gpio/driver.h> |
b43ab901 SAS |
24 | |
25 | #define DRV_NAME "sdv_gpio" | |
26 | #define SDV_NUM_PUB_GPIOS 12 | |
27 | #define PCI_DEVICE_ID_SDV_GPIO 0x2e67 | |
28 | #define GPIO_BAR 0 | |
29 | ||
30 | #define GPOUTR 0x00 | |
31 | #define GPOER 0x04 | |
32 | #define GPINR 0x08 | |
33 | ||
34 | #define GPSTR 0x0c | |
35 | #define GPIT1R0 0x10 | |
36 | #define GPIO_INT 0x14 | |
37 | #define GPIT1R1 0x18 | |
38 | ||
39 | #define GPMUXCTL 0x1c | |
40 | ||
41 | struct sdv_gpio_chip_data { | |
42 | int irq_base; | |
43 | void __iomem *gpio_pub_base; | |
3ffc9ceb | 44 | struct irq_domain *id; |
b43ab901 | 45 | struct irq_chip_generic *gc; |
0f4630f3 | 46 | struct gpio_chip chip; |
b43ab901 SAS |
47 | }; |
48 | ||
49 | static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type) | |
50 | { | |
51 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
52 | struct sdv_gpio_chip_data *sd = gc->private; | |
53 | void __iomem *type_reg; | |
b43ab901 SAS |
54 | u32 reg; |
55 | ||
3ffc9ceb | 56 | if (d->hwirq < 8) |
b43ab901 SAS |
57 | type_reg = sd->gpio_pub_base + GPIT1R0; |
58 | else | |
59 | type_reg = sd->gpio_pub_base + GPIT1R1; | |
60 | ||
61 | reg = readl(type_reg); | |
62 | ||
63 | switch (type) { | |
64 | case IRQ_TYPE_LEVEL_HIGH: | |
3ffc9ceb | 65 | reg &= ~BIT(4 * (d->hwirq % 8)); |
b43ab901 SAS |
66 | break; |
67 | ||
68 | case IRQ_TYPE_LEVEL_LOW: | |
3ffc9ceb | 69 | reg |= BIT(4 * (d->hwirq % 8)); |
b43ab901 SAS |
70 | break; |
71 | ||
72 | default: | |
73 | return -EINVAL; | |
74 | } | |
75 | ||
76 | writel(reg, type_reg); | |
77 | return 0; | |
78 | } | |
79 | ||
80 | static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data) | |
81 | { | |
82 | struct sdv_gpio_chip_data *sd = data; | |
83 | u32 irq_stat = readl(sd->gpio_pub_base + GPSTR); | |
84 | ||
85 | irq_stat &= readl(sd->gpio_pub_base + GPIO_INT); | |
86 | if (!irq_stat) | |
87 | return IRQ_NONE; | |
88 | ||
89 | while (irq_stat) { | |
90 | u32 irq_bit = __fls(irq_stat); | |
91 | ||
92 | irq_stat &= ~BIT(irq_bit); | |
3ffc9ceb | 93 | generic_handle_irq(irq_find_mapping(sd->id, irq_bit)); |
b43ab901 SAS |
94 | } |
95 | ||
96 | return IRQ_HANDLED; | |
97 | } | |
98 | ||
99 | static int sdv_xlate(struct irq_domain *h, struct device_node *node, | |
100 | const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq, | |
101 | u32 *out_type) | |
102 | { | |
103 | u32 line, type; | |
104 | ||
5d4c9bc7 | 105 | if (node != irq_domain_get_of_node(h)) |
b43ab901 SAS |
106 | return -EINVAL; |
107 | ||
108 | if (intsize < 2) | |
109 | return -EINVAL; | |
110 | ||
111 | line = *intspec; | |
112 | *out_hwirq = line; | |
113 | ||
114 | intspec++; | |
115 | type = *intspec; | |
116 | ||
117 | switch (type) { | |
118 | case IRQ_TYPE_LEVEL_LOW: | |
119 | case IRQ_TYPE_LEVEL_HIGH: | |
120 | *out_type = type; | |
121 | break; | |
122 | default: | |
123 | return -EINVAL; | |
124 | } | |
125 | return 0; | |
126 | } | |
127 | ||
0b354dc4 | 128 | static const struct irq_domain_ops irq_domain_sdv_ops = { |
3ffc9ceb | 129 | .xlate = sdv_xlate, |
b43ab901 SAS |
130 | }; |
131 | ||
3836309d | 132 | static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd, |
b43ab901 SAS |
133 | struct pci_dev *pdev) |
134 | { | |
135 | struct irq_chip_type *ct; | |
136 | int ret; | |
137 | ||
74dd9ebf BG |
138 | sd->irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, |
139 | SDV_NUM_PUB_GPIOS, -1); | |
b43ab901 SAS |
140 | if (sd->irq_base < 0) |
141 | return sd->irq_base; | |
142 | ||
143 | /* mask + ACK all interrupt sources */ | |
144 | writel(0, sd->gpio_pub_base + GPIO_INT); | |
145 | writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR); | |
146 | ||
74dd9ebf BG |
147 | ret = devm_request_irq(&pdev->dev, pdev->irq, |
148 | sdv_gpio_pub_irq_handler, IRQF_SHARED, | |
149 | "sdv_gpio", sd); | |
b43ab901 | 150 | if (ret) |
74dd9ebf | 151 | return ret; |
b43ab901 | 152 | |
b43ab901 SAS |
153 | /* |
154 | * This gpio irq controller latches level irqs. Testing shows that if | |
155 | * we unmask & ACK the IRQ before the source of the interrupt is gone | |
156 | * then the interrupt is active again. | |
157 | */ | |
158 | sd->gc = irq_alloc_generic_chip("sdv-gpio", 1, sd->irq_base, | |
159 | sd->gpio_pub_base, handle_fasteoi_irq); | |
74dd9ebf BG |
160 | if (!sd->gc) |
161 | return -ENOMEM; | |
b43ab901 SAS |
162 | |
163 | sd->gc->private = sd; | |
164 | ct = sd->gc->chip_types; | |
165 | ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; | |
166 | ct->regs.eoi = GPSTR; | |
167 | ct->regs.mask = GPIO_INT; | |
168 | ct->chip.irq_mask = irq_gc_mask_clr_bit; | |
169 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | |
170 | ct->chip.irq_eoi = irq_gc_eoi; | |
171 | ct->chip.irq_set_type = sdv_gpio_pub_set_type; | |
172 | ||
173 | irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS), | |
174 | IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, | |
175 | IRQ_LEVEL | IRQ_NOPROBE); | |
176 | ||
3ffc9ceb GL |
177 | sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS, |
178 | sd->irq_base, 0, &irq_domain_sdv_ops, sd); | |
74dd9ebf BG |
179 | if (!sd->id) |
180 | return -ENODEV; | |
181 | ||
b43ab901 | 182 | return 0; |
b43ab901 SAS |
183 | } |
184 | ||
3836309d | 185 | static int sdv_gpio_probe(struct pci_dev *pdev, |
b43ab901 SAS |
186 | const struct pci_device_id *pci_id) |
187 | { | |
188 | struct sdv_gpio_chip_data *sd; | |
189 | unsigned long addr; | |
190 | const void *prop; | |
191 | int len; | |
192 | int ret; | |
193 | u32 mux_val; | |
194 | ||
195 | sd = kzalloc(sizeof(struct sdv_gpio_chip_data), GFP_KERNEL); | |
196 | if (!sd) | |
197 | return -ENOMEM; | |
198 | ret = pci_enable_device(pdev); | |
199 | if (ret) { | |
200 | dev_err(&pdev->dev, "can't enable device.\n"); | |
201 | goto done; | |
202 | } | |
203 | ||
204 | ret = pci_request_region(pdev, GPIO_BAR, DRV_NAME); | |
205 | if (ret) { | |
206 | dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR); | |
207 | goto disable_pci; | |
208 | } | |
209 | ||
210 | addr = pci_resource_start(pdev, GPIO_BAR); | |
e6ae9195 WY |
211 | if (!addr) { |
212 | ret = -ENODEV; | |
b43ab901 | 213 | goto release_reg; |
e6ae9195 | 214 | } |
b43ab901 SAS |
215 | sd->gpio_pub_base = ioremap(addr, pci_resource_len(pdev, GPIO_BAR)); |
216 | ||
217 | prop = of_get_property(pdev->dev.of_node, "intel,muxctl", &len); | |
218 | if (prop && len == 4) { | |
219 | mux_val = of_read_number(prop, 1); | |
220 | writel(mux_val, sd->gpio_pub_base + GPMUXCTL); | |
221 | } | |
222 | ||
0f4630f3 | 223 | ret = bgpio_init(&sd->chip, &pdev->dev, 4, |
b43ab901 | 224 | sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR, |
3e11f7b8 | 225 | NULL, sd->gpio_pub_base + GPOER, NULL, 0); |
b43ab901 SAS |
226 | if (ret) |
227 | goto unmap; | |
0f4630f3 | 228 | sd->chip.ngpio = SDV_NUM_PUB_GPIOS; |
b43ab901 | 229 | |
0f4630f3 | 230 | ret = gpiochip_add_data(&sd->chip, sd); |
b43ab901 SAS |
231 | if (ret < 0) { |
232 | dev_err(&pdev->dev, "gpiochip_add() failed.\n"); | |
233 | goto unmap; | |
234 | } | |
235 | ||
236 | ret = sdv_register_irqsupport(sd, pdev); | |
237 | if (ret) | |
238 | goto unmap; | |
239 | ||
240 | pci_set_drvdata(pdev, sd); | |
241 | dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n"); | |
242 | return 0; | |
243 | ||
244 | unmap: | |
245 | iounmap(sd->gpio_pub_base); | |
246 | release_reg: | |
247 | pci_release_region(pdev, GPIO_BAR); | |
248 | disable_pci: | |
249 | pci_disable_device(pdev); | |
250 | done: | |
251 | kfree(sd); | |
252 | return ret; | |
253 | } | |
254 | ||
14f4a883 | 255 | static const struct pci_device_id sdv_gpio_pci_ids[] = { |
b43ab901 SAS |
256 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) }, |
257 | { 0, }, | |
258 | }; | |
259 | ||
260 | static struct pci_driver sdv_gpio_driver = { | |
6a5ead91 PG |
261 | .driver = { |
262 | .suppress_bind_attrs = true, | |
263 | }, | |
b43ab901 SAS |
264 | .name = DRV_NAME, |
265 | .id_table = sdv_gpio_pci_ids, | |
266 | .probe = sdv_gpio_probe, | |
b43ab901 | 267 | }; |
6a5ead91 | 268 | builtin_pci_driver(sdv_gpio_driver); |