[linux-block.git] / drivers / gpio / gpio-sodaville.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  GPIO interface for Intel Sodaville SoCs.
 *
 *  Copyright (c) 2010, 2011 Intel Corporation
 *
 *  Author: Hans J. Koch <hjk@linutronix.de>
 */

#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/of_irq.h>
#include <linux/pci.h>
#include <linux/platform_device.h>

#define DRV_NAME		"sdv_gpio"
#define SDV_NUM_PUB_GPIOS	12
#define PCI_DEVICE_ID_SDV_GPIO	0x2e67
#define GPIO_BAR		0

#define GPOUTR		0x00
#define GPOER		0x04
#define GPINR		0x08

#define GPSTR		0x0c
#define GPIT1R0		0x10
#define GPIO_INT	0x14
#define GPIT1R1		0x18

#define GPMUXCTL	0x1c

struct sdv_gpio_chip_data {
	int irq_base;
	void __iomem *gpio_pub_base;
	struct irq_domain *id;
	struct irq_chip_generic *gc;
	struct gpio_chip chip;
};

static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct sdv_gpio_chip_data *sd = gc->private;
	void __iomem *type_reg;
	u32 reg;

	if (d->hwirq < 8)
		type_reg = sd->gpio_pub_base + GPIT1R0;
	else
		type_reg = sd->gpio_pub_base + GPIT1R1;

	reg = readl(type_reg);

	switch (type) {
	case IRQ_TYPE_LEVEL_HIGH:
		reg &= ~BIT(4 * (d->hwirq % 8));
		break;

	case IRQ_TYPE_LEVEL_LOW:
		reg |= BIT(4 * (d->hwirq % 8));
		break;

	default:
		return -EINVAL;
	}

	writel(reg, type_reg);
	return 0;
}

static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
{
	struct sdv_gpio_chip_data *sd = data;
	unsigned long irq_stat = readl(sd->gpio_pub_base + GPSTR);
	int irq_bit;

	irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
	if (!irq_stat)
		return IRQ_NONE;

	for_each_set_bit(irq_bit, &irq_stat, 32)
		generic_handle_domain_irq(sd->id, irq_bit);

	return IRQ_HANDLED;
}

static int sdv_xlate(struct irq_domain *h, struct device_node *node,
		const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
		u32 *out_type)
{
	u32 line, type;

	if (node != irq_domain_get_of_node(h))
		return -EINVAL;

	if (intsize < 2)
		return -EINVAL;

	line = *intspec;
	*out_hwirq = line;

	intspec++;
	type = *intspec;

	switch (type) {
	case IRQ_TYPE_LEVEL_LOW:
	case IRQ_TYPE_LEVEL_HIGH:
		*out_type = type;
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

static const struct irq_domain_ops irq_domain_sdv_ops = {
	.xlate = sdv_xlate,
};

static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
		struct pci_dev *pdev)
{
	struct irq_chip_type *ct;
	int ret;

	sd->irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
					    SDV_NUM_PUB_GPIOS, -1);
	if (sd->irq_base < 0)
		return sd->irq_base;

	/* mask + ACK all interrupt sources */
	writel(0, sd->gpio_pub_base + GPIO_INT);
	writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);

	ret = devm_request_irq(&pdev->dev, pdev->irq,
			       sdv_gpio_pub_irq_handler, IRQF_SHARED,
			       "sdv_gpio", sd);
	if (ret)
		return ret;

	/*
	 * This gpio irq controller latches level irqs. Testing shows that if
	 * we unmask & ACK the IRQ before the source of the interrupt is gone
	 * then the interrupt is active again.
	 */
	sd->gc = devm_irq_alloc_generic_chip(&pdev->dev, "sdv-gpio", 1,
					     sd->irq_base,
					     sd->gpio_pub_base,
					     handle_fasteoi_irq);
	if (!sd->gc)
		return -ENOMEM;

	sd->gc->private = sd;
	ct = sd->gc->chip_types;
	ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
	ct->regs.eoi = GPSTR;
	ct->regs.mask = GPIO_INT;
	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	ct->chip.irq_eoi = irq_gc_eoi;
	ct->chip.irq_set_type = sdv_gpio_pub_set_type;

	irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
			IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
			IRQ_LEVEL | IRQ_NOPROBE);

	sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
				sd->irq_base, 0, &irq_domain_sdv_ops, sd);
	if (!sd->id)
		return -ENODEV;

	return 0;
}

static int sdv_gpio_probe(struct pci_dev *pdev,
					const struct pci_device_id *pci_id)
{
	struct sdv_gpio_chip_data *sd;
	int ret;
	u32 mux_val;

	sd = devm_kzalloc(&pdev->dev, sizeof(*sd), GFP_KERNEL);
	if (!sd)
		return -ENOMEM;

	ret = pcim_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "can't enable device.\n");
		return ret;
	}

	ret = pcim_iomap_regions(pdev, 1 << GPIO_BAR, DRV_NAME);
	if (ret) {
		dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
		return ret;
	}

	sd->gpio_pub_base = pcim_iomap_table(pdev)[GPIO_BAR];

	ret = of_property_read_u32(pdev->dev.of_node, "intel,muxctl", &mux_val);
	if (!ret)
		writel(mux_val, sd->gpio_pub_base + GPMUXCTL);

	ret = bgpio_init(&sd->chip, &pdev->dev, 4,
			sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
			NULL, sd->gpio_pub_base + GPOER, NULL, 0);
	if (ret)
		return ret;

	sd->chip.ngpio = SDV_NUM_PUB_GPIOS;

	ret = devm_gpiochip_add_data(&pdev->dev, &sd->chip, sd);
	if (ret < 0) {
		dev_err(&pdev->dev, "gpiochip_add() failed.\n");
		return ret;
	}

	ret = sdv_register_irqsupport(sd, pdev);
	if (ret)
		return ret;

	pci_set_drvdata(pdev, sd);
	dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
	return 0;
}

static const struct pci_device_id sdv_gpio_pci_ids[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
	{ 0, },
};

static struct pci_driver sdv_gpio_driver = {
	.driver = {
		.suppress_bind_attrs = true,
	},
	.name = DRV_NAME,
	.id_table = sdv_gpio_pci_ids,
	.probe = sdv_gpio_probe,
};
builtin_pci_driver(sdv_gpio_driver);
Commit	Line	Data
aaa21231	1	// SPDX-License-Identifier: GPL-2.0
b43ab901 SAS	2	/*
	3	* GPIO interface for Intel Sodaville SoCs.
	4	*
	5	* Copyright (c) 2010, 2011 Intel Corporation
	6	*
6a5ead91	7	* Author: Hans J. Koch <hjk@linutronix.de>
b43ab901 SAS	8	*/
	9
	10	#include <linux/errno.h>
8700998f	11	#include <linux/gpio/driver.h>
b43ab901	12	#include <linux/init.h>
8700998f	13	#include <linux/interrupt.h>
b43ab901 SAS	14	#include <linux/io.h>
b43ab901 SAS	15	#include <linux/irq.h>
b43ab901	16	#include <linux/kernel.h>
8700998f	17	#include <linux/of_irq.h>
b43ab901 SAS	18	#include <linux/pci.h>
b43ab901 SAS	19	#include <linux/platform_device.h>
b43ab901 SAS	20
	21	#define DRV_NAME "sdv_gpio"
	22	#define SDV_NUM_PUB_GPIOS 12
	23	#define PCI_DEVICE_ID_SDV_GPIO 0x2e67
	24	#define GPIO_BAR 0
	25
	26	#define GPOUTR 0x00
	27	#define GPOER 0x04
	28	#define GPINR 0x08
	29
	30	#define GPSTR 0x0c
	31	#define GPIT1R0 0x10
	32	#define GPIO_INT 0x14
	33	#define GPIT1R1 0x18
	34
	35	#define GPMUXCTL 0x1c
	36
	37	struct sdv_gpio_chip_data {
	38	int irq_base;
	39	void __iomem *gpio_pub_base;
3ffc9ceb	40	struct irq_domain *id;
b43ab901	41	struct irq_chip_generic *gc;
0f4630f3	42	struct gpio_chip chip;
b43ab901 SAS	43	};
	44
	45	static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
	46	{
	47	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	48	struct sdv_gpio_chip_data *sd = gc->private;
	49	void __iomem *type_reg;
b43ab901 SAS	50	u32 reg;
b43ab901 SAS	51
3ffc9ceb	52	if (d->hwirq < 8)
b43ab901 SAS	53	type_reg = sd->gpio_pub_base + GPIT1R0;
	54	else
	55	type_reg = sd->gpio_pub_base + GPIT1R1;
	56
	57	reg = readl(type_reg);
	58
	59	switch (type) {
	60	case IRQ_TYPE_LEVEL_HIGH:
3ffc9ceb	61	reg &= ~BIT(4 * (d->hwirq % 8));
b43ab901 SAS	62	break;
	63
	64	case IRQ_TYPE_LEVEL_LOW:
3ffc9ceb	65	reg \|= BIT(4 * (d->hwirq % 8));
b43ab901 SAS	66	break;
	67
	68	default:
	69	return -EINVAL;
	70	}
	71
	72	writel(reg, type_reg);
	73	return 0;
	74	}
	75
	76	static irqreturn_t sdv_gpio_pub_irq_handler(int irq, void *data)
	77	{
	78	struct sdv_gpio_chip_data *sd = data;
f3af44f0 AS	79	unsigned long irq_stat = readl(sd->gpio_pub_base + GPSTR);
f3af44f0 AS	80	int irq_bit;
b43ab901 SAS	81
	82	irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
	83	if (!irq_stat)
	84	return IRQ_NONE;
	85
f3af44f0	86	for_each_set_bit(irq_bit, &irq_stat, 32)
dbd1c54f	87	generic_handle_domain_irq(sd->id, irq_bit);
b43ab901 SAS	88
	89	return IRQ_HANDLED;
	90	}
	91
	92	static int sdv_xlate(struct irq_domain h, struct device_node node,
	93	const u32 intspec, u32 intsize, irq_hw_number_t out_hwirq,
	94	u32 *out_type)
	95	{
	96	u32 line, type;
	97
5d4c9bc7	98	if (node != irq_domain_get_of_node(h))
b43ab901 SAS	99	return -EINVAL;
	100
	101	if (intsize < 2)
	102	return -EINVAL;
	103
	104	line = *intspec;
	105	*out_hwirq = line;
	106
	107	intspec++;
	108	type = *intspec;
	109
	110	switch (type) {
	111	case IRQ_TYPE_LEVEL_LOW:
	112	case IRQ_TYPE_LEVEL_HIGH:
	113	*out_type = type;
	114	break;
	115	default:
	116	return -EINVAL;
	117	}
	118	return 0;
	119	}
	120
0b354dc4	121	static const struct irq_domain_ops irq_domain_sdv_ops = {
3ffc9ceb	122	.xlate = sdv_xlate,
b43ab901 SAS	123	};
b43ab901 SAS	124
3836309d	125	static int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
b43ab901 SAS	126	struct pci_dev *pdev)
	127	{
	128	struct irq_chip_type *ct;
	129	int ret;
	130
74dd9ebf BG	131	sd->irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
74dd9ebf BG	132	SDV_NUM_PUB_GPIOS, -1);
b43ab901 SAS	133	if (sd->irq_base < 0)
	134	return sd->irq_base;
	135
	136	/* mask + ACK all interrupt sources */
	137	writel(0, sd->gpio_pub_base + GPIO_INT);
	138	writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
	139
74dd9ebf BG	140	ret = devm_request_irq(&pdev->dev, pdev->irq,
	141	sdv_gpio_pub_irq_handler, IRQF_SHARED,
	142	"sdv_gpio", sd);
b43ab901	143	if (ret)
74dd9ebf	144	return ret;
b43ab901	145
b43ab901 SAS	146	/*
	147	* This gpio irq controller latches level irqs. Testing shows that if
	148	* we unmask & ACK the IRQ before the source of the interrupt is gone
	149	* then the interrupt is active again.
	150	*/
9381fc5d AS	151	sd->gc = devm_irq_alloc_generic_chip(&pdev->dev, "sdv-gpio", 1,
	152	sd->irq_base,
	153	sd->gpio_pub_base,
	154	handle_fasteoi_irq);
74dd9ebf BG	155	if (!sd->gc)
74dd9ebf BG	156	return -ENOMEM;
b43ab901 SAS	157
	158	sd->gc->private = sd;
	159	ct = sd->gc->chip_types;
	160	ct->type = IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW;
	161	ct->regs.eoi = GPSTR;
	162	ct->regs.mask = GPIO_INT;
	163	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	164	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	165	ct->chip.irq_eoi = irq_gc_eoi;
	166	ct->chip.irq_set_type = sdv_gpio_pub_set_type;
	167
	168	irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
	169	IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
	170	IRQ_LEVEL \| IRQ_NOPROBE);
	171
3ffc9ceb GL	172	sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
3ffc9ceb GL	173	sd->irq_base, 0, &irq_domain_sdv_ops, sd);
74dd9ebf BG	174	if (!sd->id)
	175	return -ENODEV;
	176
b43ab901	177	return 0;
b43ab901 SAS	178	}
b43ab901 SAS	179
3836309d	180	static int sdv_gpio_probe(struct pci_dev *pdev,
b43ab901 SAS	181	const struct pci_device_id *pci_id)
	182	{
	183	struct sdv_gpio_chip_data *sd;
b43ab901 SAS	184	int ret;
	185	u32 mux_val;
	186
9381fc5d	187	sd = devm_kzalloc(&pdev->dev, sizeof(*sd), GFP_KERNEL);
b43ab901 SAS	188	if (!sd)
b43ab901 SAS	189	return -ENOMEM;
9381fc5d AS	190
9381fc5d AS	191	ret = pcim_enable_device(pdev);
b43ab901 SAS	192	if (ret) {
b43ab901 SAS	193	dev_err(&pdev->dev, "can't enable device.\n");
9381fc5d	194	return ret;
b43ab901 SAS	195	}
b43ab901 SAS	196
9381fc5d	197	ret = pcim_iomap_regions(pdev, 1 << GPIO_BAR, DRV_NAME);
b43ab901 SAS	198	if (ret) {
b43ab901 SAS	199	dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", GPIO_BAR);
9381fc5d	200	return ret;
b43ab901 SAS	201	}
b43ab901 SAS	202
9381fc5d	203	sd->gpio_pub_base = pcim_iomap_table(pdev)[GPIO_BAR];
b43ab901	204
9381fc5d AS	205	ret = of_property_read_u32(pdev->dev.of_node, "intel,muxctl", &mux_val);
9381fc5d AS	206	if (!ret)
b43ab901	207	writel(mux_val, sd->gpio_pub_base + GPMUXCTL);
b43ab901	208
0f4630f3	209	ret = bgpio_init(&sd->chip, &pdev->dev, 4,
b43ab901	210	sd->gpio_pub_base + GPINR, sd->gpio_pub_base + GPOUTR,
3e11f7b8	211	NULL, sd->gpio_pub_base + GPOER, NULL, 0);
b43ab901	212	if (ret)
9381fc5d AS	213	return ret;
9381fc5d AS	214
0f4630f3	215	sd->chip.ngpio = SDV_NUM_PUB_GPIOS;
b43ab901	216
9381fc5d	217	ret = devm_gpiochip_add_data(&pdev->dev, &sd->chip, sd);
b43ab901 SAS	218	if (ret < 0) {
b43ab901 SAS	219	dev_err(&pdev->dev, "gpiochip_add() failed.\n");
9381fc5d	220	return ret;
b43ab901 SAS	221	}
	222
	223	ret = sdv_register_irqsupport(sd, pdev);
	224	if (ret)
9381fc5d	225	return ret;
b43ab901 SAS	226
	227	pci_set_drvdata(pdev, sd);
	228	dev_info(&pdev->dev, "Sodaville GPIO driver registered.\n");
	229	return 0;
b43ab901 SAS	230	}
b43ab901 SAS	231
14f4a883	232	static const struct pci_device_id sdv_gpio_pci_ids[] = {
b43ab901 SAS	233	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SDV_GPIO) },
	234	{ 0, },
	235	};
	236
	237	static struct pci_driver sdv_gpio_driver = {
6a5ead91 PG	238	.driver = {
	239	.suppress_bind_attrs = true,
	240	},
b43ab901 SAS	241	.name = DRV_NAME,
	242	.id_table = sdv_gpio_pci_ids,
	243	.probe = sdv_gpio_probe,
b43ab901	244	};
6a5ead91	245	builtin_pci_driver(sdv_gpio_driver);