Commit | Line | Data |
---|---|---|
be8c8fac UKK |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright (C) 2015-2018 Pengutronix, Uwe Kleine-König <kernel@pengutronix.de> | |
4 | */ | |
5 | ||
6 | #include <linux/module.h> | |
7 | #include <linux/siox.h> | |
8 | #include <linux/gpio/driver.h> | |
9 | #include <linux/of.h> | |
10 | ||
11 | struct gpio_siox_ddata { | |
12 | struct gpio_chip gchip; | |
be8c8fac UKK |
13 | struct mutex lock; |
14 | u8 setdata[1]; | |
15 | u8 getdata[3]; | |
16 | ||
023892ec | 17 | raw_spinlock_t irqlock; |
be8c8fac UKK |
18 | u32 irq_enable; |
19 | u32 irq_status; | |
20 | u32 irq_type[20]; | |
21 | }; | |
22 | ||
23 | /* | |
24 | * Note that this callback only sets the value that is clocked out in the next | |
25 | * cycle. | |
26 | */ | |
27 | static int gpio_siox_set_data(struct siox_device *sdevice, u8 status, u8 buf[]) | |
28 | { | |
29 | struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev); | |
30 | ||
31 | mutex_lock(&ddata->lock); | |
32 | buf[0] = ddata->setdata[0]; | |
33 | mutex_unlock(&ddata->lock); | |
34 | ||
35 | return 0; | |
36 | } | |
37 | ||
38 | static int gpio_siox_get_data(struct siox_device *sdevice, const u8 buf[]) | |
39 | { | |
40 | struct gpio_siox_ddata *ddata = dev_get_drvdata(&sdevice->dev); | |
41 | size_t offset; | |
42 | u32 trigger; | |
43 | ||
44 | mutex_lock(&ddata->lock); | |
45 | ||
023892ec | 46 | raw_spin_lock_irq(&ddata->irqlock); |
be8c8fac UKK |
47 | |
48 | for (offset = 0; offset < 12; ++offset) { | |
49 | unsigned int bitpos = 11 - offset; | |
50 | unsigned int gpiolevel = buf[bitpos / 8] & (1 << bitpos % 8); | |
51 | unsigned int prev_level = | |
52 | ddata->getdata[bitpos / 8] & (1 << (bitpos % 8)); | |
53 | u32 irq_type = ddata->irq_type[offset]; | |
54 | ||
55 | if (gpiolevel) { | |
56 | if ((irq_type & IRQ_TYPE_LEVEL_HIGH) || | |
57 | ((irq_type & IRQ_TYPE_EDGE_RISING) && !prev_level)) | |
58 | ddata->irq_status |= 1 << offset; | |
59 | } else { | |
60 | if ((irq_type & IRQ_TYPE_LEVEL_LOW) || | |
61 | ((irq_type & IRQ_TYPE_EDGE_FALLING) && prev_level)) | |
62 | ddata->irq_status |= 1 << offset; | |
63 | } | |
64 | } | |
65 | ||
66 | trigger = ddata->irq_status & ddata->irq_enable; | |
67 | ||
023892ec | 68 | raw_spin_unlock_irq(&ddata->irqlock); |
be8c8fac UKK |
69 | |
70 | ddata->getdata[0] = buf[0]; | |
71 | ddata->getdata[1] = buf[1]; | |
72 | ddata->getdata[2] = buf[2]; | |
73 | ||
74 | mutex_unlock(&ddata->lock); | |
75 | ||
76 | for (offset = 0; offset < 12; ++offset) { | |
77 | if (trigger & (1 << offset)) { | |
78 | struct irq_domain *irqdomain = ddata->gchip.irq.domain; | |
79 | unsigned int irq = irq_find_mapping(irqdomain, offset); | |
80 | ||
81 | /* | |
82 | * Conceptually handle_nested_irq should call the flow | |
83 | * handler of the irq chip. But it doesn't, so we have | |
84 | * to clean the irq_status here. | |
85 | */ | |
023892ec | 86 | raw_spin_lock_irq(&ddata->irqlock); |
be8c8fac | 87 | ddata->irq_status &= ~(1 << offset); |
023892ec | 88 | raw_spin_unlock_irq(&ddata->irqlock); |
be8c8fac UKK |
89 | |
90 | handle_nested_irq(irq); | |
91 | } | |
92 | } | |
93 | ||
94 | return 0; | |
95 | } | |
96 | ||
97 | static void gpio_siox_irq_ack(struct irq_data *d) | |
98 | { | |
5ff8240e LW |
99 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
100 | struct gpio_siox_ddata *ddata = gpiochip_get_data(gc); | |
be8c8fac | 101 | |
023892ec | 102 | raw_spin_lock(&ddata->irqlock); |
be8c8fac | 103 | ddata->irq_status &= ~(1 << d->hwirq); |
023892ec | 104 | raw_spin_unlock(&ddata->irqlock); |
be8c8fac UKK |
105 | } |
106 | ||
107 | static void gpio_siox_irq_mask(struct irq_data *d) | |
108 | { | |
5ff8240e LW |
109 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
110 | struct gpio_siox_ddata *ddata = gpiochip_get_data(gc); | |
be8c8fac | 111 | |
023892ec | 112 | raw_spin_lock(&ddata->irqlock); |
be8c8fac | 113 | ddata->irq_enable &= ~(1 << d->hwirq); |
023892ec | 114 | raw_spin_unlock(&ddata->irqlock); |
5ff8240e | 115 | gpiochip_disable_irq(gc, irqd_to_hwirq(d)); |
be8c8fac UKK |
116 | } |
117 | ||
118 | static void gpio_siox_irq_unmask(struct irq_data *d) | |
119 | { | |
5ff8240e LW |
120 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
121 | struct gpio_siox_ddata *ddata = gpiochip_get_data(gc); | |
be8c8fac | 122 | |
5ff8240e | 123 | gpiochip_enable_irq(gc, irqd_to_hwirq(d)); |
023892ec | 124 | raw_spin_lock(&ddata->irqlock); |
be8c8fac | 125 | ddata->irq_enable |= 1 << d->hwirq; |
023892ec | 126 | raw_spin_unlock(&ddata->irqlock); |
be8c8fac UKK |
127 | } |
128 | ||
129 | static int gpio_siox_irq_set_type(struct irq_data *d, u32 type) | |
130 | { | |
5ff8240e LW |
131 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
132 | struct gpio_siox_ddata *ddata = gpiochip_get_data(gc); | |
be8c8fac | 133 | |
023892ec | 134 | raw_spin_lock(&ddata->irqlock); |
be8c8fac | 135 | ddata->irq_type[d->hwirq] = type; |
023892ec | 136 | raw_spin_unlock(&ddata->irqlock); |
be8c8fac UKK |
137 | |
138 | return 0; | |
139 | } | |
140 | ||
141 | static int gpio_siox_get(struct gpio_chip *chip, unsigned int offset) | |
142 | { | |
5ff8240e | 143 | struct gpio_siox_ddata *ddata = gpiochip_get_data(chip); |
be8c8fac UKK |
144 | int ret; |
145 | ||
146 | mutex_lock(&ddata->lock); | |
147 | ||
148 | if (offset >= 12) { | |
149 | unsigned int bitpos = 19 - offset; | |
150 | ||
151 | ret = ddata->setdata[0] & (1 << bitpos); | |
152 | } else { | |
153 | unsigned int bitpos = 11 - offset; | |
154 | ||
155 | ret = ddata->getdata[bitpos / 8] & (1 << (bitpos % 8)); | |
156 | } | |
157 | ||
158 | mutex_unlock(&ddata->lock); | |
159 | ||
160 | return ret; | |
161 | } | |
162 | ||
163 | static void gpio_siox_set(struct gpio_chip *chip, | |
164 | unsigned int offset, int value) | |
165 | { | |
5ff8240e | 166 | struct gpio_siox_ddata *ddata = gpiochip_get_data(chip); |
be8c8fac UKK |
167 | u8 mask = 1 << (19 - offset); |
168 | ||
169 | mutex_lock(&ddata->lock); | |
170 | ||
171 | if (value) | |
172 | ddata->setdata[0] |= mask; | |
173 | else | |
174 | ddata->setdata[0] &= ~mask; | |
175 | ||
176 | mutex_unlock(&ddata->lock); | |
177 | } | |
178 | ||
179 | static int gpio_siox_direction_input(struct gpio_chip *chip, | |
180 | unsigned int offset) | |
181 | { | |
182 | if (offset >= 12) | |
183 | return -EINVAL; | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
188 | static int gpio_siox_direction_output(struct gpio_chip *chip, | |
189 | unsigned int offset, int value) | |
190 | { | |
191 | if (offset < 12) | |
192 | return -EINVAL; | |
193 | ||
194 | gpio_siox_set(chip, offset, value); | |
195 | return 0; | |
196 | } | |
197 | ||
198 | static int gpio_siox_get_direction(struct gpio_chip *chip, unsigned int offset) | |
199 | { | |
200 | if (offset < 12) | |
e42615ec | 201 | return GPIO_LINE_DIRECTION_IN; |
be8c8fac | 202 | else |
e42615ec | 203 | return GPIO_LINE_DIRECTION_OUT; |
be8c8fac UKK |
204 | } |
205 | ||
5ff8240e LW |
206 | static const struct irq_chip gpio_siox_irq_chip = { |
207 | .name = "siox-gpio", | |
208 | .irq_ack = gpio_siox_irq_ack, | |
209 | .irq_mask = gpio_siox_irq_mask, | |
210 | .irq_unmask = gpio_siox_irq_unmask, | |
211 | .irq_set_type = gpio_siox_irq_set_type, | |
212 | .flags = IRQCHIP_IMMUTABLE, | |
213 | GPIOCHIP_IRQ_RESOURCE_HELPERS, | |
214 | }; | |
215 | ||
be8c8fac UKK |
216 | static int gpio_siox_probe(struct siox_device *sdevice) |
217 | { | |
218 | struct gpio_siox_ddata *ddata; | |
b25e10f8 | 219 | struct gpio_irq_chip *girq; |
acc14137 | 220 | struct device *dev = &sdevice->dev; |
5ff8240e | 221 | struct gpio_chip *gc; |
be8c8fac UKK |
222 | int ret; |
223 | ||
acc14137 | 224 | ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); |
be8c8fac UKK |
225 | if (!ddata) |
226 | return -ENOMEM; | |
227 | ||
acc14137 | 228 | dev_set_drvdata(dev, ddata); |
be8c8fac UKK |
229 | |
230 | mutex_init(&ddata->lock); | |
023892ec | 231 | raw_spin_lock_init(&ddata->irqlock); |
be8c8fac | 232 | |
5ff8240e LW |
233 | gc = &ddata->gchip; |
234 | gc->base = -1; | |
235 | gc->can_sleep = 1; | |
236 | gc->parent = dev; | |
237 | gc->owner = THIS_MODULE; | |
238 | gc->get = gpio_siox_get; | |
239 | gc->set = gpio_siox_set; | |
240 | gc->direction_input = gpio_siox_direction_input; | |
241 | gc->direction_output = gpio_siox_direction_output; | |
242 | gc->get_direction = gpio_siox_get_direction; | |
243 | gc->ngpio = 20; | |
244 | ||
245 | girq = &gc->irq; | |
246 | gpio_irq_chip_set_chip(girq, &gpio_siox_irq_chip); | |
b25e10f8 LW |
247 | girq->default_type = IRQ_TYPE_NONE; |
248 | girq->handler = handle_level_irq; | |
45ccf655 | 249 | girq->threaded = true; |
be8c8fac | 250 | |
5ff8240e | 251 | ret = devm_gpiochip_add_data(dev, gc, ddata); |
4c0a8899 | 252 | if (ret) |
acc14137 | 253 | dev_err(dev, "Failed to register gpio chip (%d)\n", ret); |
be8c8fac UKK |
254 | |
255 | return ret; | |
256 | } | |
257 | ||
be8c8fac UKK |
258 | static struct siox_driver gpio_siox_driver = { |
259 | .probe = gpio_siox_probe, | |
be8c8fac UKK |
260 | .set_data = gpio_siox_set_data, |
261 | .get_data = gpio_siox_get_data, | |
262 | .driver = { | |
263 | .name = "gpio-siox", | |
264 | }, | |
265 | }; | |
f79047b1 | 266 | module_siox_driver(gpio_siox_driver); |
be8c8fac UKK |
267 | |
268 | MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>"); | |
269 | MODULE_DESCRIPTION("SIOX gpio driver"); | |
270 | MODULE_LICENSE("GPL v2"); |