Commit | Line | Data |
---|---|---|
be9b06b2 | 1 | /* |
c103de24 | 2 | * GPIO interface for Intel Poulsbo SCH |
be9b06b2 DT |
3 | * |
4 | * Copyright (c) 2010 CompuLab Ltd | |
5 | * Author: Denis Turischev <denis@compulab.co.il> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License 2 as published | |
9 | * by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; see the file COPYING. If not, write to | |
18 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/init.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/io.h> | |
25 | #include <linux/errno.h> | |
26 | #include <linux/acpi.h> | |
27 | #include <linux/platform_device.h> | |
f04ddfcd | 28 | #include <linux/pci_ids.h> |
be9b06b2 DT |
29 | |
30 | #include <linux/gpio.h> | |
31 | ||
c479ff09 MW |
32 | #define GEN 0x00 |
33 | #define GIO 0x04 | |
34 | #define GLV 0x08 | |
35 | ||
36 | struct sch_gpio { | |
37 | struct gpio_chip chip; | |
38 | spinlock_t lock; | |
39 | unsigned short iobase; | |
40 | unsigned short core_base; | |
41 | unsigned short resume_base; | |
42 | }; | |
be9b06b2 | 43 | |
c479ff09 MW |
44 | static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio, |
45 | unsigned reg) | |
be9b06b2 | 46 | { |
c479ff09 | 47 | unsigned base = 0; |
be9b06b2 | 48 | |
c479ff09 MW |
49 | if (gpio >= sch->resume_base) { |
50 | gpio -= sch->resume_base; | |
51 | base += 0x20; | |
52 | } | |
be9b06b2 | 53 | |
c479ff09 | 54 | return base + reg + gpio / 8; |
be9b06b2 DT |
55 | } |
56 | ||
c479ff09 | 57 | static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio) |
be9b06b2 | 58 | { |
c479ff09 MW |
59 | if (gpio >= sch->resume_base) |
60 | gpio -= sch->resume_base; | |
61 | return gpio % 8; | |
be9b06b2 DT |
62 | } |
63 | ||
87041a58 | 64 | static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned gpio, unsigned reg) |
be9b06b2 | 65 | { |
be9b06b2 | 66 | unsigned short offset, bit; |
920dfd82 | 67 | u8 reg_val; |
be9b06b2 | 68 | |
920dfd82 | 69 | offset = sch_gpio_offset(sch, gpio, reg); |
c479ff09 | 70 | bit = sch_gpio_bit(sch, gpio); |
be9b06b2 | 71 | |
920dfd82 | 72 | reg_val = !!(inb(sch->iobase + offset) & BIT(bit)); |
1e0d9823 | 73 | |
920dfd82 | 74 | return reg_val; |
be9b06b2 DT |
75 | } |
76 | ||
87041a58 | 77 | static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned gpio, unsigned reg, |
920dfd82 | 78 | int val) |
be9b06b2 | 79 | { |
3cbf1822 | 80 | unsigned short offset, bit; |
920dfd82 | 81 | u8 reg_val; |
be9b06b2 | 82 | |
920dfd82 CRSF |
83 | offset = sch_gpio_offset(sch, gpio, reg); |
84 | bit = sch_gpio_bit(sch, gpio); | |
be9b06b2 | 85 | |
920dfd82 | 86 | reg_val = inb(sch->iobase + offset); |
3cbf1822 | 87 | |
920dfd82 CRSF |
88 | if (val) |
89 | outb(reg_val | BIT(bit), sch->iobase + offset); | |
90 | else | |
91 | outb((reg_val & ~BIT(bit)), sch->iobase + offset); | |
92 | } | |
be9b06b2 | 93 | |
920dfd82 CRSF |
94 | static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num) |
95 | { | |
737c8fcc | 96 | struct sch_gpio *sch = gpiochip_get_data(gc); |
be9b06b2 | 97 | |
920dfd82 | 98 | spin_lock(&sch->lock); |
87041a58 | 99 | sch_gpio_reg_set(sch, gpio_num, GIO, 1); |
c479ff09 | 100 | spin_unlock(&sch->lock); |
be9b06b2 DT |
101 | return 0; |
102 | } | |
103 | ||
c479ff09 | 104 | static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num) |
be9b06b2 | 105 | { |
87041a58 CP |
106 | struct sch_gpio *sch = gpiochip_get_data(gc); |
107 | return sch_gpio_reg_get(sch, gpio_num, GLV); | |
be9b06b2 DT |
108 | } |
109 | ||
c479ff09 | 110 | static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val) |
be9b06b2 | 111 | { |
737c8fcc | 112 | struct sch_gpio *sch = gpiochip_get_data(gc); |
be9b06b2 | 113 | |
c479ff09 | 114 | spin_lock(&sch->lock); |
87041a58 | 115 | sch_gpio_reg_set(sch, gpio_num, GLV, val); |
c479ff09 | 116 | spin_unlock(&sch->lock); |
be9b06b2 DT |
117 | } |
118 | ||
c479ff09 MW |
119 | static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num, |
120 | int val) | |
be9b06b2 | 121 | { |
737c8fcc | 122 | struct sch_gpio *sch = gpiochip_get_data(gc); |
be9b06b2 | 123 | |
c479ff09 | 124 | spin_lock(&sch->lock); |
87041a58 | 125 | sch_gpio_reg_set(sch, gpio_num, GIO, 0); |
c479ff09 | 126 | spin_unlock(&sch->lock); |
1e0d9823 DK |
127 | |
128 | /* | |
c479ff09 MW |
129 | * according to the datasheet, writing to the level register has no |
130 | * effect when GPIO is programmed as input. | |
131 | * Actually the the level register is read-only when configured as input. | |
132 | * Thus presetting the output level before switching to output is _NOT_ possible. | |
133 | * Hence we set the level after configuring the GPIO as output. | |
134 | * But we cannot prevent a short low pulse if direction is set to high | |
135 | * and an external pull-up is connected. | |
136 | */ | |
137 | sch_gpio_set(gc, gpio_num, val); | |
be9b06b2 DT |
138 | return 0; |
139 | } | |
140 | ||
e35b5ab0 | 141 | static const struct gpio_chip sch_gpio_chip = { |
c479ff09 | 142 | .label = "sch_gpio", |
be9b06b2 | 143 | .owner = THIS_MODULE, |
c479ff09 MW |
144 | .direction_input = sch_gpio_direction_in, |
145 | .get = sch_gpio_get, | |
146 | .direction_output = sch_gpio_direction_out, | |
147 | .set = sch_gpio_set, | |
be9b06b2 DT |
148 | }; |
149 | ||
3836309d | 150 | static int sch_gpio_probe(struct platform_device *pdev) |
be9b06b2 | 151 | { |
c479ff09 | 152 | struct sch_gpio *sch; |
be9b06b2 | 153 | struct resource *res; |
f04ddfcd | 154 | |
c479ff09 MW |
155 | sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL); |
156 | if (!sch) | |
157 | return -ENOMEM; | |
be9b06b2 DT |
158 | |
159 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
160 | if (!res) | |
161 | return -EBUSY; | |
162 | ||
c479ff09 MW |
163 | if (!devm_request_region(&pdev->dev, res->start, resource_size(res), |
164 | pdev->name)) | |
be9b06b2 DT |
165 | return -EBUSY; |
166 | ||
c479ff09 MW |
167 | spin_lock_init(&sch->lock); |
168 | sch->iobase = res->start; | |
169 | sch->chip = sch_gpio_chip; | |
170 | sch->chip.label = dev_name(&pdev->dev); | |
58383c78 | 171 | sch->chip.parent = &pdev->dev; |
be9b06b2 | 172 | |
c479ff09 | 173 | switch (pdev->id) { |
be41cf58 | 174 | case PCI_DEVICE_ID_INTEL_SCH_LPC: |
c479ff09 MW |
175 | sch->core_base = 0; |
176 | sch->resume_base = 10; | |
177 | sch->chip.ngpio = 14; | |
178 | ||
be41cf58 LN |
179 | /* |
180 | * GPIO[6:0] enabled by default | |
181 | * GPIO7 is configured by the CMC as SLPIOVR | |
182 | * Enable GPIO[9:8] core powered gpios explicitly | |
183 | */ | |
87041a58 CP |
184 | sch_gpio_reg_set(sch, 8, GEN, 1); |
185 | sch_gpio_reg_set(sch, 9, GEN, 1); | |
be41cf58 LN |
186 | /* |
187 | * SUS_GPIO[2:0] enabled by default | |
188 | * Enable SUS_GPIO3 resume powered gpio explicitly | |
189 | */ | |
87041a58 | 190 | sch_gpio_reg_set(sch, 13, GEN, 1); |
be41cf58 LN |
191 | break; |
192 | ||
193 | case PCI_DEVICE_ID_INTEL_ITC_LPC: | |
c479ff09 MW |
194 | sch->core_base = 0; |
195 | sch->resume_base = 5; | |
196 | sch->chip.ngpio = 14; | |
be41cf58 LN |
197 | break; |
198 | ||
199 | case PCI_DEVICE_ID_INTEL_CENTERTON_ILB: | |
c479ff09 MW |
200 | sch->core_base = 0; |
201 | sch->resume_base = 21; | |
202 | sch->chip.ngpio = 30; | |
be41cf58 LN |
203 | break; |
204 | ||
92021490 CRSF |
205 | case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB: |
206 | sch->core_base = 0; | |
207 | sch->resume_base = 2; | |
208 | sch->chip.ngpio = 8; | |
209 | break; | |
210 | ||
be41cf58 | 211 | default: |
c479ff09 | 212 | return -ENODEV; |
f04ddfcd | 213 | } |
be9b06b2 | 214 | |
c479ff09 | 215 | platform_set_drvdata(pdev, sch); |
be9b06b2 | 216 | |
c1411464 | 217 | return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch); |
be9b06b2 DT |
218 | } |
219 | ||
220 | static struct platform_driver sch_gpio_driver = { | |
221 | .driver = { | |
222 | .name = "sch_gpio", | |
be9b06b2 DT |
223 | }, |
224 | .probe = sch_gpio_probe, | |
be9b06b2 DT |
225 | }; |
226 | ||
6f61415e | 227 | module_platform_driver(sch_gpio_driver); |
be9b06b2 DT |
228 | |
229 | MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>"); | |
230 | MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH"); | |
231 | MODULE_LICENSE("GPL"); | |
232 | MODULE_ALIAS("platform:sch_gpio"); |