Commit | Line | Data |
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cb0e9a7b | 1 | // SPDX-License-Identifier: GPL-2.0 |
be9b06b2 | 2 | /* |
c103de24 | 3 | * GPIO interface for Intel Poulsbo SCH |
be9b06b2 DT |
4 | * |
5 | * Copyright (c) 2010 CompuLab Ltd | |
6 | * Author: Denis Turischev <denis@compulab.co.il> | |
be9b06b2 DT |
7 | */ |
8 | ||
47091b05 AS |
9 | #include <linux/acpi.h> |
10 | #include <linux/errno.h> | |
11 | #include <linux/gpio/driver.h> | |
12 | #include <linux/io.h> | |
be9b06b2 DT |
13 | #include <linux/kernel.h> |
14 | #include <linux/module.h> | |
f04ddfcd | 15 | #include <linux/pci_ids.h> |
47091b05 | 16 | #include <linux/platform_device.h> |
be9b06b2 | 17 | |
c479ff09 MW |
18 | #define GEN 0x00 |
19 | #define GIO 0x04 | |
20 | #define GLV 0x08 | |
21 | ||
22 | struct sch_gpio { | |
23 | struct gpio_chip chip; | |
24 | spinlock_t lock; | |
25 | unsigned short iobase; | |
c479ff09 MW |
26 | unsigned short resume_base; |
27 | }; | |
be9b06b2 | 28 | |
2c58e44a AS |
29 | static unsigned int sch_gpio_offset(struct sch_gpio *sch, unsigned int gpio, |
30 | unsigned int reg) | |
be9b06b2 | 31 | { |
2c58e44a | 32 | unsigned int base = 0; |
be9b06b2 | 33 | |
c479ff09 MW |
34 | if (gpio >= sch->resume_base) { |
35 | gpio -= sch->resume_base; | |
36 | base += 0x20; | |
37 | } | |
be9b06b2 | 38 | |
c479ff09 | 39 | return base + reg + gpio / 8; |
be9b06b2 DT |
40 | } |
41 | ||
2c58e44a | 42 | static unsigned int sch_gpio_bit(struct sch_gpio *sch, unsigned int gpio) |
be9b06b2 | 43 | { |
c479ff09 MW |
44 | if (gpio >= sch->resume_base) |
45 | gpio -= sch->resume_base; | |
46 | return gpio % 8; | |
be9b06b2 DT |
47 | } |
48 | ||
2c58e44a | 49 | static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned int gpio, unsigned int reg) |
be9b06b2 | 50 | { |
be9b06b2 | 51 | unsigned short offset, bit; |
920dfd82 | 52 | u8 reg_val; |
be9b06b2 | 53 | |
920dfd82 | 54 | offset = sch_gpio_offset(sch, gpio, reg); |
c479ff09 | 55 | bit = sch_gpio_bit(sch, gpio); |
be9b06b2 | 56 | |
920dfd82 | 57 | reg_val = !!(inb(sch->iobase + offset) & BIT(bit)); |
1e0d9823 | 58 | |
920dfd82 | 59 | return reg_val; |
be9b06b2 DT |
60 | } |
61 | ||
2c58e44a | 62 | static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned int gpio, unsigned int reg, |
920dfd82 | 63 | int val) |
be9b06b2 | 64 | { |
3cbf1822 | 65 | unsigned short offset, bit; |
920dfd82 | 66 | u8 reg_val; |
be9b06b2 | 67 | |
920dfd82 CRSF |
68 | offset = sch_gpio_offset(sch, gpio, reg); |
69 | bit = sch_gpio_bit(sch, gpio); | |
be9b06b2 | 70 | |
920dfd82 | 71 | reg_val = inb(sch->iobase + offset); |
3cbf1822 | 72 | |
920dfd82 CRSF |
73 | if (val) |
74 | outb(reg_val | BIT(bit), sch->iobase + offset); | |
75 | else | |
76 | outb((reg_val & ~BIT(bit)), sch->iobase + offset); | |
77 | } | |
be9b06b2 | 78 | |
2c58e44a | 79 | static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned int gpio_num) |
920dfd82 | 80 | { |
737c8fcc | 81 | struct sch_gpio *sch = gpiochip_get_data(gc); |
be9b06b2 | 82 | |
920dfd82 | 83 | spin_lock(&sch->lock); |
87041a58 | 84 | sch_gpio_reg_set(sch, gpio_num, GIO, 1); |
c479ff09 | 85 | spin_unlock(&sch->lock); |
be9b06b2 DT |
86 | return 0; |
87 | } | |
88 | ||
2c58e44a | 89 | static int sch_gpio_get(struct gpio_chip *gc, unsigned int gpio_num) |
be9b06b2 | 90 | { |
87041a58 | 91 | struct sch_gpio *sch = gpiochip_get_data(gc); |
4941b8de | 92 | |
87041a58 | 93 | return sch_gpio_reg_get(sch, gpio_num, GLV); |
be9b06b2 DT |
94 | } |
95 | ||
2c58e44a | 96 | static void sch_gpio_set(struct gpio_chip *gc, unsigned int gpio_num, int val) |
be9b06b2 | 97 | { |
737c8fcc | 98 | struct sch_gpio *sch = gpiochip_get_data(gc); |
be9b06b2 | 99 | |
c479ff09 | 100 | spin_lock(&sch->lock); |
87041a58 | 101 | sch_gpio_reg_set(sch, gpio_num, GLV, val); |
c479ff09 | 102 | spin_unlock(&sch->lock); |
be9b06b2 DT |
103 | } |
104 | ||
2c58e44a | 105 | static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned int gpio_num, |
c479ff09 | 106 | int val) |
be9b06b2 | 107 | { |
737c8fcc | 108 | struct sch_gpio *sch = gpiochip_get_data(gc); |
be9b06b2 | 109 | |
c479ff09 | 110 | spin_lock(&sch->lock); |
87041a58 | 111 | sch_gpio_reg_set(sch, gpio_num, GIO, 0); |
c479ff09 | 112 | spin_unlock(&sch->lock); |
1e0d9823 DK |
113 | |
114 | /* | |
c479ff09 MW |
115 | * according to the datasheet, writing to the level register has no |
116 | * effect when GPIO is programmed as input. | |
117 | * Actually the the level register is read-only when configured as input. | |
118 | * Thus presetting the output level before switching to output is _NOT_ possible. | |
119 | * Hence we set the level after configuring the GPIO as output. | |
120 | * But we cannot prevent a short low pulse if direction is set to high | |
121 | * and an external pull-up is connected. | |
122 | */ | |
123 | sch_gpio_set(gc, gpio_num, val); | |
be9b06b2 DT |
124 | return 0; |
125 | } | |
126 | ||
2c58e44a | 127 | static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio_num) |
d8e764c2 LW |
128 | { |
129 | struct sch_gpio *sch = gpiochip_get_data(gc); | |
130 | ||
e42615ec MV |
131 | if (sch_gpio_reg_get(sch, gpio_num, GIO)) |
132 | return GPIO_LINE_DIRECTION_IN; | |
133 | ||
134 | return GPIO_LINE_DIRECTION_OUT; | |
d8e764c2 LW |
135 | } |
136 | ||
e35b5ab0 | 137 | static const struct gpio_chip sch_gpio_chip = { |
c479ff09 | 138 | .label = "sch_gpio", |
be9b06b2 | 139 | .owner = THIS_MODULE, |
c479ff09 MW |
140 | .direction_input = sch_gpio_direction_in, |
141 | .get = sch_gpio_get, | |
142 | .direction_output = sch_gpio_direction_out, | |
143 | .set = sch_gpio_set, | |
d8e764c2 | 144 | .get_direction = sch_gpio_get_direction, |
be9b06b2 DT |
145 | }; |
146 | ||
3836309d | 147 | static int sch_gpio_probe(struct platform_device *pdev) |
be9b06b2 | 148 | { |
c479ff09 | 149 | struct sch_gpio *sch; |
be9b06b2 | 150 | struct resource *res; |
f04ddfcd | 151 | |
c479ff09 MW |
152 | sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL); |
153 | if (!sch) | |
154 | return -ENOMEM; | |
be9b06b2 DT |
155 | |
156 | res = platform_get_resource(pdev, IORESOURCE_IO, 0); | |
157 | if (!res) | |
158 | return -EBUSY; | |
159 | ||
c479ff09 MW |
160 | if (!devm_request_region(&pdev->dev, res->start, resource_size(res), |
161 | pdev->name)) | |
be9b06b2 DT |
162 | return -EBUSY; |
163 | ||
c479ff09 MW |
164 | spin_lock_init(&sch->lock); |
165 | sch->iobase = res->start; | |
166 | sch->chip = sch_gpio_chip; | |
167 | sch->chip.label = dev_name(&pdev->dev); | |
58383c78 | 168 | sch->chip.parent = &pdev->dev; |
be9b06b2 | 169 | |
c479ff09 | 170 | switch (pdev->id) { |
be41cf58 | 171 | case PCI_DEVICE_ID_INTEL_SCH_LPC: |
c479ff09 MW |
172 | sch->resume_base = 10; |
173 | sch->chip.ngpio = 14; | |
174 | ||
be41cf58 LN |
175 | /* |
176 | * GPIO[6:0] enabled by default | |
177 | * GPIO7 is configured by the CMC as SLPIOVR | |
178 | * Enable GPIO[9:8] core powered gpios explicitly | |
179 | */ | |
87041a58 CP |
180 | sch_gpio_reg_set(sch, 8, GEN, 1); |
181 | sch_gpio_reg_set(sch, 9, GEN, 1); | |
be41cf58 LN |
182 | /* |
183 | * SUS_GPIO[2:0] enabled by default | |
184 | * Enable SUS_GPIO3 resume powered gpio explicitly | |
185 | */ | |
87041a58 | 186 | sch_gpio_reg_set(sch, 13, GEN, 1); |
be41cf58 LN |
187 | break; |
188 | ||
189 | case PCI_DEVICE_ID_INTEL_ITC_LPC: | |
c479ff09 MW |
190 | sch->resume_base = 5; |
191 | sch->chip.ngpio = 14; | |
be41cf58 LN |
192 | break; |
193 | ||
194 | case PCI_DEVICE_ID_INTEL_CENTERTON_ILB: | |
c479ff09 MW |
195 | sch->resume_base = 21; |
196 | sch->chip.ngpio = 30; | |
be41cf58 LN |
197 | break; |
198 | ||
92021490 | 199 | case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB: |
92021490 CRSF |
200 | sch->resume_base = 2; |
201 | sch->chip.ngpio = 8; | |
202 | break; | |
203 | ||
be41cf58 | 204 | default: |
c479ff09 | 205 | return -ENODEV; |
f04ddfcd | 206 | } |
be9b06b2 | 207 | |
c479ff09 | 208 | platform_set_drvdata(pdev, sch); |
be9b06b2 | 209 | |
c1411464 | 210 | return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch); |
be9b06b2 DT |
211 | } |
212 | ||
213 | static struct platform_driver sch_gpio_driver = { | |
214 | .driver = { | |
215 | .name = "sch_gpio", | |
be9b06b2 DT |
216 | }, |
217 | .probe = sch_gpio_probe, | |
be9b06b2 DT |
218 | }; |
219 | ||
6f61415e | 220 | module_platform_driver(sch_gpio_driver); |
be9b06b2 DT |
221 | |
222 | MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>"); | |
223 | MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH"); | |
cb0e9a7b | 224 | MODULE_LICENSE("GPL v2"); |
be9b06b2 | 225 | MODULE_ALIAS("platform:sch_gpio"); |