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gpio: samsung: Fix input mode setting function for GPIO int
[linux-2.6-block.git] / drivers / gpio / gpio-samsung.c
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1b39d5f2
KK		 1/*
2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * SAMSUNG - GPIOlib support
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/irq.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/init.h>
22#include <linux/spinlock.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
edbaa603 25#include <linux/device.h>
1b39d5f2 26#include <linux/ioport.h>
659d73ad
TA		 27#include <linux/of.h>
28#include <linux/slab.h>
29#include <linux/of_address.h>
1b39d5f2
KK		 30
31#include <asm/irq.h>
32
33#include <mach/hardware.h>
34#include <mach/map.h>
35#include <mach/regs-clock.h>
36#include <mach/regs-gpio.h>
37
38#include <plat/cpu.h>
39#include <plat/gpio-core.h>
40#include <plat/gpio-cfg.h>
41#include <plat/gpio-cfg-helpers.h>
42#include <plat/gpio-fns.h>
43#include <plat/pm.h>
44
45#ifndef DEBUG_GPIO
46#define gpio_dbg(x...) do { } while (0)
47#else
48#define gpio_dbg(x...) printk(KERN_DEBUG x)
49#endif
50
51int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
52 unsigned int off, samsung_gpio_pull_t pull)
53{
54 void __iomem *reg = chip->base + 0x08;
55 int shift = off * 2;
56 u32 pup;
57
58 pup = __raw_readl(reg);
59 pup &= ~(3 << shift);
60 pup |= pull << shift;
61 __raw_writel(pup, reg);
62
63 return 0;
64}
65
66samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
67 unsigned int off)
68{
69 void __iomem *reg = chip->base + 0x08;
70 int shift = off * 2;
71 u32 pup = __raw_readl(reg);
72
73 pup >>= shift;
74 pup &= 0x3;
75
76 return (__force samsung_gpio_pull_t)pup;
77}
78
79int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
80 unsigned int off, samsung_gpio_pull_t pull)
81{
82 switch (pull) {
83 case S3C_GPIO_PULL_NONE:
84 pull = 0x01;
85 break;
86 case S3C_GPIO_PULL_UP:
87 pull = 0x00;
88 break;
89 case S3C_GPIO_PULL_DOWN:
90 pull = 0x02;
91 break;
92 }
93 return samsung_gpio_setpull_updown(chip, off, pull);
94}
95
96samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
97 unsigned int off)
98{
99 samsung_gpio_pull_t pull;
100
101 pull = samsung_gpio_getpull_updown(chip, off);
102
103 switch (pull) {
104 case 0x00:
105 pull = S3C_GPIO_PULL_UP;
106 break;
107 case 0x01:
108 case 0x03:
109 pull = S3C_GPIO_PULL_NONE;
110 break;
111 case 0x02:
112 pull = S3C_GPIO_PULL_DOWN;
113 break;
114 }
115
116 return pull;
117}
118
119static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
120 unsigned int off, samsung_gpio_pull_t pull,
121 samsung_gpio_pull_t updown)
122{
123 void __iomem *reg = chip->base + 0x08;
124 u32 pup = __raw_readl(reg);
125
126 if (pull == updown)
127 pup &= ~(1 << off);
128 else if (pull == S3C_GPIO_PULL_NONE)
129 pup |= (1 << off);
130 else
131 return -EINVAL;
132
133 __raw_writel(pup, reg);
134 return 0;
135}
136
137static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
138 unsigned int off,
139 samsung_gpio_pull_t updown)
140{
141 void __iomem *reg = chip->base + 0x08;
142 u32 pup = __raw_readl(reg);
143
144 pup &= (1 << off);
145 return pup ? S3C_GPIO_PULL_NONE : updown;
146}
147
148samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
149 unsigned int off)
150{
151 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
152}
153
154int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
155 unsigned int off, samsung_gpio_pull_t pull)
156{
157 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
158}
159
160samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
161 unsigned int off)
162{
163 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
164}
165
166int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
167 unsigned int off, samsung_gpio_pull_t pull)
168{
169 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
170}
171
a9696d84 172static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
1b39d5f2
KK		 173 unsigned int off, samsung_gpio_pull_t pull)
174{
175 if (pull == S3C_GPIO_PULL_UP)
176 pull = 3;
177
178 return samsung_gpio_setpull_updown(chip, off, pull);
179}
180
a9696d84 181static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
1b39d5f2
KK		 182 unsigned int off)
183{
184 samsung_gpio_pull_t pull;
185
186 pull = samsung_gpio_getpull_updown(chip, off);
187
188 if (pull == 3)
189 pull = S3C_GPIO_PULL_UP;
190
191 return pull;
192}
193
194/*
195 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
196 * @chip: The gpio chip that is being configured.
197 * @off: The offset for the GPIO being configured.
198 * @cfg: The configuration value to set.
199 *
200 * This helper deal with the GPIO cases where the control register
201 * has two bits of configuration per gpio, which have the following
202 * functions:
203 * 00 = input
204 * 01 = output
205 * 1x = special function
206 */
207
208static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
209 unsigned int off, unsigned int cfg)
210{
211 void __iomem *reg = chip->base;
212 unsigned int shift = off * 2;
213 u32 con;
214
215 if (samsung_gpio_is_cfg_special(cfg)) {
216 cfg &= 0xf;
217 if (cfg > 3)
218 return -EINVAL;
219
220 cfg <<= shift;
221 }
222
223 con = __raw_readl(reg);
224 con &= ~(0x3 << shift);
225 con |= cfg;
226 __raw_writel(con, reg);
227
228 return 0;
229}
230
231/*
232 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
233 * @chip: The gpio chip that is being configured.
234 * @off: The offset for the GPIO being configured.
235 *
f1347599 236 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
1b39d5f2
KK		 237 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
238 * S3C_GPIO_SPECIAL() macro.
239 */
240
241static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
242 unsigned int off)
243{
244 u32 con;
245
246 con = __raw_readl(chip->base);
247 con >>= off * 2;
248 con &= 3;
249
250 /* this conversion works for IN and OUT as well as special mode */
251 return S3C_GPIO_SPECIAL(con);
252}
253
254/*
255 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
256 * @chip: The gpio chip that is being configured.
257 * @off: The offset for the GPIO being configured.
258 * @cfg: The configuration value to set.
259 *
260 * This helper deal with the GPIO cases where the control register has 4 bits
261 * of control per GPIO, generally in the form of:
262 * 0000 = Input
263 * 0001 = Output
264 * others = Special functions (dependent on bank)
265 *
266 * Note, since the code to deal with the case where there are two control
267 * registers instead of one, we do not have a separate set of functions for
268 * each case.
269 */
270
271static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
272 unsigned int off, unsigned int cfg)
273{
274 void __iomem *reg = chip->base;
275 unsigned int shift = (off & 7) * 4;
276 u32 con;
277
278 if (off < 8 && chip->chip.ngpio > 8)
279 reg -= 4;
280
281 if (samsung_gpio_is_cfg_special(cfg)) {
282 cfg &= 0xf;
283 cfg <<= shift;
284 }
285
286 con = __raw_readl(reg);
287 con &= ~(0xf << shift);
288 con |= cfg;
289 __raw_writel(con, reg);
290
291 return 0;
292}
293
294/*
295 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
296 * @chip: The gpio chip that is being configured.
297 * @off: The offset for the GPIO being configured.
298 *
299 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
300 * register setting into a value the software can use, such as could be passed
301 * to samsung_gpio_setcfg_4bit().
302 *
303 * @sa samsung_gpio_getcfg_2bit
304 */
305
306static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
307 unsigned int off)
308{
309 void __iomem *reg = chip->base;
310 unsigned int shift = (off & 7) * 4;
311 u32 con;
312
313 if (off < 8 && chip->chip.ngpio > 8)
314 reg -= 4;
315
316 con = __raw_readl(reg);
317 con >>= shift;
318 con &= 0xf;
319
320 /* this conversion works for IN and OUT as well as special mode */
321 return S3C_GPIO_SPECIAL(con);
322}
323
c034b184 324#ifdef CONFIG_PLAT_S3C24XX
1b39d5f2
KK		 325/*
326 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
327 * @chip: The gpio chip that is being configured.
328 * @off: The offset for the GPIO being configured.
329 * @cfg: The configuration value to set.
330 *
331 * This helper deal with the GPIO cases where the control register
332 * has one bit of configuration for the gpio, where setting the bit
333 * means the pin is in special function mode and unset means output.
334 */
335
336static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
337 unsigned int off, unsigned int cfg)
338{
339 void __iomem *reg = chip->base;
340 unsigned int shift = off;
341 u32 con;
342
343 if (samsung_gpio_is_cfg_special(cfg)) {
344 cfg &= 0xf;
345
346 /* Map output to 0, and SFN2 to 1 */
347 cfg -= 1;
348 if (cfg > 1)
349 return -EINVAL;
350
351 cfg <<= shift;
352 }
353
354 con = __raw_readl(reg);
355 con &= ~(0x1 << shift);
356 con |= cfg;
357 __raw_writel(con, reg);
358
359 return 0;
360}
361
362/*
363 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
364 * @chip: The gpio chip that is being configured.
365 * @off: The offset for the GPIO being configured.
366 *
367 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
368 * GPIO configuration value.
369 *
370 * @sa samsung_gpio_getcfg_2bit
371 * @sa samsung_gpio_getcfg_4bit
372 */
373
374static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
375 unsigned int off)
376{
377 u32 con;
378
379 con = __raw_readl(chip->base);
380 con >>= off;
381 con &= 1;
382 con++;
383
384 return S3C_GPIO_SFN(con);
385}
c034b184 386#endif
1b39d5f2 387
c034b184 388#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
1b39d5f2
KK		 389static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
390 unsigned int off, unsigned int cfg)
391{
392 void __iomem *reg = chip->base;
393 unsigned int shift;
394 u32 con;
395
396 switch (off) {
397 case 0:
398 case 1:
399 case 2:
400 case 3:
401 case 4:
402 case 5:
403 shift = (off & 7) * 4;
404 reg -= 4;
405 break;
406 case 6:
407 shift = ((off + 1) & 7) * 4;
408 reg -= 4;
409 default:
410 shift = ((off + 1) & 7) * 4;
411 break;
412 }
413
414 if (samsung_gpio_is_cfg_special(cfg)) {
415 cfg &= 0xf;
416 cfg <<= shift;
417 }
418
419 con = __raw_readl(reg);
420 con &= ~(0xf << shift);
421 con |= cfg;
422 __raw_writel(con, reg);
423
424 return 0;
425}
c034b184 426#endif
1b39d5f2
KK		 427
428static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
429 int nr_chips)
430{
431 for (; nr_chips > 0; nr_chips--, chipcfg++) {
432 if (!chipcfg->set_config)
433 chipcfg->set_config = samsung_gpio_setcfg_4bit;
434 if (!chipcfg->get_config)
435 chipcfg->get_config = samsung_gpio_getcfg_4bit;
436 if (!chipcfg->set_pull)
437 chipcfg->set_pull = samsung_gpio_setpull_updown;
438 if (!chipcfg->get_pull)
439 chipcfg->get_pull = samsung_gpio_getpull_updown;
440 }
441}
442
443struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
444 .set_config = samsung_gpio_setcfg_2bit,
445 .get_config = samsung_gpio_getcfg_2bit,
446};
447
c034b184 448#ifdef CONFIG_PLAT_S3C24XX
1b39d5f2
KK		 449static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
450 .set_config = s3c24xx_gpio_setcfg_abank,
451 .get_config = s3c24xx_gpio_getcfg_abank,
452};
c034b184 453#endif
1b39d5f2 454
2760f7ad 455#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_ARCH_EXYNOS5)
a9696d84
SP		 456static struct samsung_gpio_cfg exynos_gpio_cfg = {
457 .set_pull = exynos_gpio_setpull,
458 .get_pull = exynos_gpio_getpull,
f79e40eb
MS		 459 .set_config = samsung_gpio_setcfg_4bit,
460 .get_config = samsung_gpio_getcfg_4bit,
1b39d5f2 461};
2760f7ad 462#endif
1b39d5f2 463
c034b184 464#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
1b39d5f2
KK		 465static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
466 .cfg_eint = 0x3,
467 .set_config = s5p64x0_gpio_setcfg_rbank,
468 .get_config = samsung_gpio_getcfg_4bit,
469 .set_pull = samsung_gpio_setpull_updown,
470 .get_pull = samsung_gpio_getpull_updown,
471};
c034b184 472#endif
1b39d5f2
KK		 473
474static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
2985479f 475 [0] = {
1b39d5f2 476 .cfg_eint = 0x0,
2985479f
MB		 477 },
478 [1] = {
1b39d5f2 479 .cfg_eint = 0x3,
2985479f
MB		 480 },
481 [2] = {
1b39d5f2 482 .cfg_eint = 0x7,
2985479f
MB		 483 },
484 [3] = {
1b39d5f2 485 .cfg_eint = 0xF,
2985479f
MB		 486 },
487 [4] = {
1b39d5f2
KK		 488 .cfg_eint = 0x0,
489 .set_config = samsung_gpio_setcfg_2bit,
490 .get_config = samsung_gpio_getcfg_2bit,
2985479f
MB		 491 },
492 [5] = {
1b39d5f2
KK		 493 .cfg_eint = 0x2,
494 .set_config = samsung_gpio_setcfg_2bit,
495 .get_config = samsung_gpio_getcfg_2bit,
2985479f
MB		 496 },
497 [6] = {
1b39d5f2
KK		 498 .cfg_eint = 0x3,
499 .set_config = samsung_gpio_setcfg_2bit,
500 .get_config = samsung_gpio_getcfg_2bit,
2985479f
MB		 501 },
502 [7] = {
1b39d5f2
KK		 503 .set_config = samsung_gpio_setcfg_2bit,
504 .get_config = samsung_gpio_getcfg_2bit,
2985479f
MB		 505 },
506 [8] = {
a9696d84
SP		 507 .set_pull = exynos_gpio_setpull,
508 .get_pull = exynos_gpio_getpull,
2985479f
MB		 509 },
510 [9] = {
b82cee24 511 .cfg_eint = 0x3,
a9696d84
SP		 512 .set_pull = exynos_gpio_setpull,
513 .get_pull = exynos_gpio_getpull,
b82cee24 514 }
1b39d5f2
KK		 515};
516
517/*
518 * Default routines for controlling GPIO, based on the original S3C24XX
519 * GPIO functions which deal with the case where each gpio bank of the
520 * chip is as following:
521 *
522 * base + 0x00: Control register, 2 bits per gpio
523 * gpio n: 2 bits starting at (2*n)
524 * 00 = input, 01 = output, others mean special-function
525 * base + 0x04: Data register, 1 bit per gpio
526 * bit n: data bit n
527*/
528
529static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
530{
531 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
532 void __iomem *base = ourchip->base;
533 unsigned long flags;
534 unsigned long con;
535
536 samsung_gpio_lock(ourchip, flags);
537
538 con = __raw_readl(base + 0x00);
539 con &= ~(3 << (offset * 2));
540
541 __raw_writel(con, base + 0x00);
542
543 samsung_gpio_unlock(ourchip, flags);
544 return 0;
545}
546
547static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
548 unsigned offset, int value)
549{
550 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
551 void __iomem *base = ourchip->base;
552 unsigned long flags;
553 unsigned long dat;
554 unsigned long con;
555
556 samsung_gpio_lock(ourchip, flags);
557
558 dat = __raw_readl(base + 0x04);
559 dat &= ~(1 << offset);
560 if (value)
561 dat |= 1 << offset;
562 __raw_writel(dat, base + 0x04);
563
564 con = __raw_readl(base + 0x00);
565 con &= ~(3 << (offset * 2));
566 con |= 1 << (offset * 2);
567
568 __raw_writel(con, base + 0x00);
569 __raw_writel(dat, base + 0x04);
570
571 samsung_gpio_unlock(ourchip, flags);
572 return 0;
573}
574
575/*
576 * The samsung_gpiolib_4bit routines are to control the gpio banks where
577 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
578 * following example:
579 *
580 * base + 0x00: Control register, 4 bits per gpio
581 * gpio n: 4 bits starting at (4*n)
582 * 0000 = input, 0001 = output, others mean special-function
583 * base + 0x04: Data register, 1 bit per gpio
584 * bit n: data bit n
585 *
586 * Note, since the data register is one bit per gpio and is at base + 0x4
587 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
588 * state of the output.
589 */
590
591static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
592 unsigned int offset)
593{
594 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
595 void __iomem *base = ourchip->base;
596 unsigned long con;
597
598 con = __raw_readl(base + GPIOCON_OFF);
2b88ff4a
EK		 599 if (ourchip->bitmap_gpio_int & BIT(offset))
600 con |= 0xf << con_4bit_shift(offset);
601 else
602 con &= ~(0xf << con_4bit_shift(offset));
1b39d5f2
KK		 603 __raw_writel(con, base + GPIOCON_OFF);
604
605 gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
606
607 return 0;
608}
609
610static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
611 unsigned int offset, int value)
612{
613 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
614 void __iomem *base = ourchip->base;
615 unsigned long con;
616 unsigned long dat;
617
618 con = __raw_readl(base + GPIOCON_OFF);
619 con &= ~(0xf << con_4bit_shift(offset));
620 con |= 0x1 << con_4bit_shift(offset);
621
622 dat = __raw_readl(base + GPIODAT_OFF);
623
624 if (value)
625 dat |= 1 << offset;
626 else
627 dat &= ~(1 << offset);
628
629 __raw_writel(dat, base + GPIODAT_OFF);
630 __raw_writel(con, base + GPIOCON_OFF);
631 __raw_writel(dat, base + GPIODAT_OFF);
632
633 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
634
635 return 0;
636}
637
638/*
639 * The next set of routines are for the case where the GPIO configuration
640 * registers are 4 bits per GPIO but there is more than one register (the
641 * bank has more than 8 GPIOs.
642 *
643 * This case is the similar to the 4 bit case, but the registers are as
644 * follows:
645 *
646 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
647 * gpio n: 4 bits starting at (4*n)
648 * 0000 = input, 0001 = output, others mean special-function
649 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
650 * gpio n: 4 bits starting at (4*n)
651 * 0000 = input, 0001 = output, others mean special-function
652 * base + 0x08: Data register, 1 bit per gpio
653 * bit n: data bit n
654 *
655 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
656 * routines we store the 'base + 0x4' address so that these routines see
657 * the data register at ourchip->base + 0x04.
658 */
659
660static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
661 unsigned int offset)
662{
663 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
664 void __iomem *base = ourchip->base;
665 void __iomem *regcon = base;
666 unsigned long con;
667
668 if (offset > 7)
669 offset -= 8;
670 else
671 regcon -= 4;
672
673 con = __raw_readl(regcon);
674 con &= ~(0xf << con_4bit_shift(offset));
675 __raw_writel(con, regcon);
676
677 gpio_dbg("%s: %p: CON %08lx\n", __func__, base, con);
678
679 return 0;
680}
681
682static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
683 unsigned int offset, int value)
684{
685 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
686 void __iomem *base = ourchip->base;
687 void __iomem *regcon = base;
688 unsigned long con;
689 unsigned long dat;
690 unsigned con_offset = offset;
691
692 if (con_offset > 7)
693 con_offset -= 8;
694 else
695 regcon -= 4;
696
697 con = __raw_readl(regcon);
698 con &= ~(0xf << con_4bit_shift(con_offset));
699 con |= 0x1 << con_4bit_shift(con_offset);
700
701 dat = __raw_readl(base + GPIODAT_OFF);
702
703 if (value)
704 dat |= 1 << offset;
705 else
706 dat &= ~(1 << offset);
707
708 __raw_writel(dat, base + GPIODAT_OFF);
709 __raw_writel(con, regcon);
710 __raw_writel(dat, base + GPIODAT_OFF);
711
712 gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
713
714 return 0;
715}
716
c034b184 717#ifdef CONFIG_PLAT_S3C24XX
1b39d5f2
KK		 718/* The next set of routines are for the case of s3c24xx bank a */
719
720static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
721{
722 return -EINVAL;
723}
724
725static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
726 unsigned offset, int value)
727{
728 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
729 void __iomem *base = ourchip->base;
730 unsigned long flags;
731 unsigned long dat;
732 unsigned long con;
733
734 local_irq_save(flags);
735
736 con = __raw_readl(base + 0x00);
737 dat = __raw_readl(base + 0x04);
738
739 dat &= ~(1 << offset);
740 if (value)
741 dat |= 1 << offset;
742
743 __raw_writel(dat, base + 0x04);
744
745 con &= ~(1 << offset);
746
747 __raw_writel(con, base + 0x00);
748 __raw_writel(dat, base + 0x04);
749
750 local_irq_restore(flags);
751 return 0;
752}
c034b184 753#endif
1b39d5f2
KK		 754
755/* The next set of routines are for the case of s5p64x0 bank r */
756
757static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
758 unsigned int offset)
759{
760 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
761 void __iomem *base = ourchip->base;
762 void __iomem *regcon = base;
763 unsigned long con;
764 unsigned long flags;
765
766 switch (offset) {
767 case 6:
768 offset += 1;
769 case 0:
770 case 1:
771 case 2:
772 case 3:
773 case 4:
774 case 5:
775 regcon -= 4;
776 break;
777 default:
778 offset -= 7;
779 break;
780 }
781
782 samsung_gpio_lock(ourchip, flags);
783
784 con = __raw_readl(regcon);
785 con &= ~(0xf << con_4bit_shift(offset));
786 __raw_writel(con, regcon);
787
788 samsung_gpio_unlock(ourchip, flags);
789
790 return 0;
791}
792
793static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
794 unsigned int offset, int value)
795{
796 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
797 void __iomem *base = ourchip->base;
798 void __iomem *regcon = base;
799 unsigned long con;
800 unsigned long dat;
801 unsigned long flags;
802 unsigned con_offset = offset;
803
804 switch (con_offset) {
805 case 6:
806 con_offset += 1;
807 case 0:
808 case 1:
809 case 2:
810 case 3:
811 case 4:
812 case 5:
813 regcon -= 4;
814 break;
815 default:
816 con_offset -= 7;
817 break;
818 }
819
820 samsung_gpio_lock(ourchip, flags);
821
822 con = __raw_readl(regcon);
823 con &= ~(0xf << con_4bit_shift(con_offset));
824 con |= 0x1 << con_4bit_shift(con_offset);
825
826 dat = __raw_readl(base + GPIODAT_OFF);
827 if (value)
828 dat |= 1 << offset;
829 else
830 dat &= ~(1 << offset);
831
832 __raw_writel(con, regcon);
833 __raw_writel(dat, base + GPIODAT_OFF);
834
835 samsung_gpio_unlock(ourchip, flags);
836
837 return 0;
838}
839
840static void samsung_gpiolib_set(struct gpio_chip *chip,
841 unsigned offset, int value)
842{
843 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
844 void __iomem *base = ourchip->base;
845 unsigned long flags;
846 unsigned long dat;
847
848 samsung_gpio_lock(ourchip, flags);
849
850 dat = __raw_readl(base + 0x04);
851 dat &= ~(1 << offset);
852 if (value)
853 dat |= 1 << offset;
854 __raw_writel(dat, base + 0x04);
855
856 samsung_gpio_unlock(ourchip, flags);
857}
858
859static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
860{
861 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
862 unsigned long val;
863
864 val = __raw_readl(ourchip->base + 0x04);
865 val >>= offset;
866 val &= 1;
867
868 return val;
869}
870
871/*
872 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
873 * for use with the configuration calls, and other parts of the s3c gpiolib
874 * support code.
875 *
876 * Not all s3c support code will need this, as some configurations of cpu
877 * may only support one or two different configuration options and have an
878 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
879 * the machine support file should provide its own samsung_gpiolib_getchip()
880 * and any other necessary functions.
881 */
882
883#ifdef CONFIG_S3C_GPIO_TRACK
884struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
885
886static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
887{
888 unsigned int gpn;
889 int i;
890
891 gpn = chip->chip.base;
892 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
893 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
894 s3c_gpios[gpn] = chip;
895 }
896}
897#endif /* CONFIG_S3C_GPIO_TRACK */
898
899/*
900 * samsung_gpiolib_add() - add the Samsung gpio_chip.
901 * @chip: The chip to register
902 *
903 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
904 * information and makes the necessary alterations for the platform and
905 * notes the information for use with the configuration systems and any
906 * other parts of the system.
907 */
908
909static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
910{
911 struct gpio_chip *gc = &chip->chip;
912 int ret;
913
914 BUG_ON(!chip->base);
915 BUG_ON(!gc->label);
916 BUG_ON(!gc->ngpio);
917
918 spin_lock_init(&chip->lock);
919
920 if (!gc->direction_input)
921 gc->direction_input = samsung_gpiolib_2bit_input;
922 if (!gc->direction_output)
923 gc->direction_output = samsung_gpiolib_2bit_output;
924 if (!gc->set)
925 gc->set = samsung_gpiolib_set;
926 if (!gc->get)
927 gc->get = samsung_gpiolib_get;
928
929#ifdef CONFIG_PM
930 if (chip->pm != NULL) {
931 if (!chip->pm->save || !chip->pm->resume)
932 printk(KERN_ERR "gpio: %s has missing PM functions\n",
933 gc->label);
934 } else
935 printk(KERN_ERR "gpio: %s has no PM function\n", gc->label);
936#endif
937
938 /* gpiochip_add() prints own failure message on error. */
939 ret = gpiochip_add(gc);
940 if (ret >= 0)
941 s3c_gpiolib_track(chip);
942}
943
172c6a13
HS		 944#if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
945static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
946 const struct of_phandle_args *gpiospec, u32 *flags)
947{
948 unsigned int pin;
949
950 if (WARN_ON(gc->of_gpio_n_cells < 3))
951 return -EINVAL;
952
953 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
954 return -EINVAL;
955
956 if (gpiospec->args[0] > gc->ngpio)
957 return -EINVAL;
958
959 pin = gc->base + gpiospec->args[0];
960
961 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
962 pr_warn("gpio_xlate: failed to set pin function\n");
963 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
964 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
965
966 if (flags)
967 *flags = gpiospec->args[2] >> 16;
968
969 return gpiospec->args[0];
970}
971
972static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
973 { .compatible = "samsung,s3c24xx-gpio", },
974 {}
975};
976
977static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
978 u64 base, u64 offset)
979{
980 struct gpio_chip *gc = &chip->chip;
981 u64 address;
982
983 if (!of_have_populated_dt())
984 return;
985
986 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
987 gc->of_node = of_find_matching_node_by_address(NULL,
988 s3c24xx_gpio_dt_match, address);
989 if (!gc->of_node) {
990 pr_info("gpio: device tree node not found for gpio controller"
991 " with base address %08llx\n", address);
992 return;
993 }
994 gc->of_gpio_n_cells = 3;
995 gc->of_xlate = s3c24xx_gpio_xlate;
996}
997#else
998static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
999 u64 base, u64 offset)
1000{
1001 return;
1002}
1003#endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
1004
1b39d5f2
KK		 1005static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
1006 int nr_chips, void __iomem *base)
1007{
1008 int i;
1009 struct gpio_chip *gc = &chip->chip;
1010
1011 for (i = 0 ; i < nr_chips; i++, chip++) {
8a8ab2e6
PK		 1012 /* skip banks not present on SoC */
1013 if (chip->chip.base >= S3C_GPIO_END)
1014 continue;
1015
1b39d5f2
KK		 1016 if (!chip->config)
1017 chip->config = &s3c24xx_gpiocfg_default;
1018 if (!chip->pm)
1019 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1020 if ((base != NULL) && (chip->base == NULL))
1021 chip->base = base + ((i) * 0x10);
1022
1023 if (!gc->direction_input)
1024 gc->direction_input = samsung_gpiolib_2bit_input;
1025 if (!gc->direction_output)
1026 gc->direction_output = samsung_gpiolib_2bit_output;
1027
1028 samsung_gpiolib_add(chip);
172c6a13
HS		 1029
1030 s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
1b39d5f2
KK		 1031 }
1032}
1033
1034static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
1035 int nr_chips, void __iomem *base,
1036 unsigned int offset)
1037{
1038 int i;
1039
1040 for (i = 0 ; i < nr_chips; i++, chip++) {
1041 chip->chip.direction_input = samsung_gpiolib_2bit_input;
1042 chip->chip.direction_output = samsung_gpiolib_2bit_output;
1043
1044 if (!chip->config)
1045 chip->config = &samsung_gpio_cfgs[7];
1046 if (!chip->pm)
1047 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1048 if ((base != NULL) && (chip->base == NULL))
1049 chip->base = base + ((i) * offset);
1050
1051 samsung_gpiolib_add(chip);
1052 }
1053}
1054
1055/*
1056 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
1057 * @chip: The gpio chip that is being configured.
1058 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
1059 *
1060 * This helper deal with the GPIO cases where the control register has 4 bits
1061 * of control per GPIO, generally in the form of:
1062 * 0000 = Input
1063 * 0001 = Output
1064 * others = Special functions (dependent on bank)
1065 *
1066 * Note, since the code to deal with the case where there are two control
1067 * registers instead of one, we do not have a separate set of function
1068 * (samsung_gpiolib_add_4bit2_chips)for each case.
1069 */
1070
1071static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
1072 int nr_chips, void __iomem *base)
1073{
1074 int i;
1075
1076 for (i = 0 ; i < nr_chips; i++, chip++) {
1077 chip->chip.direction_input = samsung_gpiolib_4bit_input;
1078 chip->chip.direction_output = samsung_gpiolib_4bit_output;
1079
1080 if (!chip->config)
1081 chip->config = &samsung_gpio_cfgs[2];
1082 if (!chip->pm)
1083 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1084 if ((base != NULL) && (chip->base == NULL))
1085 chip->base = base + ((i) * 0x20);
1086
2b88ff4a
EK		 1087 chip->bitmap_gpio_int = 0;
1088
1b39d5f2
KK		 1089 samsung_gpiolib_add(chip);
1090 }
1091}
1092
1093static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
1094 int nr_chips)
1095{
1096 for (; nr_chips > 0; nr_chips--, chip++) {
1097 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
1098 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
1099
1100 if (!chip->config)
1101 chip->config = &samsung_gpio_cfgs[2];
1102 if (!chip->pm)
1103 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1104
1105 samsung_gpiolib_add(chip);
1106 }
1107}
1108
1109static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1110 int nr_chips)
1111{
1112 for (; nr_chips > 0; nr_chips--, chip++) {
1113 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1114 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1115
1116 if (!chip->pm)
1117 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1118
1119 samsung_gpiolib_add(chip);
1120 }
1121}
1122
1123int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1124{
1125 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1126
1127 return samsung_chip->irq_base + offset;
1128}
1129
1130#ifdef CONFIG_PLAT_S3C24XX
1131static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1132{
1133 if (offset < 4)
1134 return IRQ_EINT0 + offset;
1135
1136 if (offset < 8)
1137 return IRQ_EINT4 + offset - 4;
1138
1139 return -EINVAL;
1140}
1141#endif
1142
1143#ifdef CONFIG_PLAT_S3C64XX
1144static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1145{
1146 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1147}
1148
1149static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1150{
1151 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1152}
1153#endif
1154
1155struct samsung_gpio_chip s3c24xx_gpios[] = {
1156#ifdef CONFIG_PLAT_S3C24XX
1157 {
1158 .config = &s3c24xx_gpiocfg_banka,
1159 .chip = {
1160 .base = S3C2410_GPA(0),
1161 .owner = THIS_MODULE,
1162 .label = "GPIOA",
1163 .ngpio = 24,
1164 .direction_input = s3c24xx_gpiolib_banka_input,
1165 .direction_output = s3c24xx_gpiolib_banka_output,
1166 },
1167 }, {
1168 .chip = {
1169 .base = S3C2410_GPB(0),
1170 .owner = THIS_MODULE,
1171 .label = "GPIOB",
1172 .ngpio = 16,
1173 },
1174 }, {
1175 .chip = {
1176 .base = S3C2410_GPC(0),
1177 .owner = THIS_MODULE,
1178 .label = "GPIOC",
1179 .ngpio = 16,
1180 },
1181 }, {
1182 .chip = {
1183 .base = S3C2410_GPD(0),
1184 .owner = THIS_MODULE,
1185 .label = "GPIOD",
1186 .ngpio = 16,
1187 },
1188 }, {
1189 .chip = {
1190 .base = S3C2410_GPE(0),
1191 .label = "GPIOE",
1192 .owner = THIS_MODULE,
1193 .ngpio = 16,
1194 },
1195 }, {
1196 .chip = {
1197 .base = S3C2410_GPF(0),
1198 .owner = THIS_MODULE,
1199 .label = "GPIOF",
1200 .ngpio = 8,
1201 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1202 },
1203 }, {
1204 .irq_base = IRQ_EINT8,
1205 .chip = {
1206 .base = S3C2410_GPG(0),
1207 .owner = THIS_MODULE,
1208 .label = "GPIOG",
1209 .ngpio = 16,
1210 .to_irq = samsung_gpiolib_to_irq,
1211 },
1212 }, {
1213 .chip = {
1214 .base = S3C2410_GPH(0),
1215 .owner = THIS_MODULE,
1216 .label = "GPIOH",
1217 .ngpio = 11,
1218 },
1219 },
1220 /* GPIOS for the S3C2443 and later devices. */
1221 {
1222 .base = S3C2440_GPJCON,
1223 .chip = {
1224 .base = S3C2410_GPJ(0),
1225 .owner = THIS_MODULE,
1226 .label = "GPIOJ",
1227 .ngpio = 16,
1228 },
1229 }, {
1230 .base = S3C2443_GPKCON,
1231 .chip = {
1232 .base = S3C2410_GPK(0),
1233 .owner = THIS_MODULE,
1234 .label = "GPIOK",
1235 .ngpio = 16,
1236 },
1237 }, {
1238 .base = S3C2443_GPLCON,
1239 .chip = {
1240 .base = S3C2410_GPL(0),
1241 .owner = THIS_MODULE,
1242 .label = "GPIOL",
1243 .ngpio = 15,
1244 },
1245 }, {
1246 .base = S3C2443_GPMCON,
1247 .chip = {
1248 .base = S3C2410_GPM(0),
1249 .owner = THIS_MODULE,
1250 .label = "GPIOM",
1251 .ngpio = 2,
1252 },
1253 },
1254#endif
1255};
1256
1257/*
1258 * GPIO bank summary:
1259 *
1260 * Bank GPIOs Style SlpCon ExtInt Group
1261 * A 8 4Bit Yes 1
1262 * B 7 4Bit Yes 1
1263 * C 8 4Bit Yes 2
1264 * D 5 4Bit Yes 3
1265 * E 5 4Bit Yes None
1266 * F 16 2Bit Yes 4 [1]
1267 * G 7 4Bit Yes 5
1268 * H 10 4Bit[2] Yes 6
1269 * I 16 2Bit Yes None
1270 * J 12 2Bit Yes None
1271 * K 16 4Bit[2] No None
1272 * L 15 4Bit[2] No None
1273 * M 6 4Bit No IRQ_EINT
1274 * N 16 2Bit No IRQ_EINT
1275 * O 16 2Bit Yes 7
1276 * P 15 2Bit Yes 8
1277 * Q 9 2Bit Yes 9
1278 *
1279 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1280 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1281 */
1282
1283static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1284#ifdef CONFIG_PLAT_S3C64XX
1285 {
1286 .chip = {
1287 .base = S3C64XX_GPA(0),
1288 .ngpio = S3C64XX_GPIO_A_NR,
1289 .label = "GPA",
1290 },
1291 }, {
1292 .chip = {
1293 .base = S3C64XX_GPB(0),
1294 .ngpio = S3C64XX_GPIO_B_NR,
1295 .label = "GPB",
1296 },
1297 }, {
1298 .chip = {
1299 .base = S3C64XX_GPC(0),
1300 .ngpio = S3C64XX_GPIO_C_NR,
1301 .label = "GPC",
1302 },
1303 }, {
1304 .chip = {
1305 .base = S3C64XX_GPD(0),
1306 .ngpio = S3C64XX_GPIO_D_NR,
1307 .label = "GPD",
1308 },
1309 }, {
1310 .config = &samsung_gpio_cfgs[0],
1311 .chip = {
1312 .base = S3C64XX_GPE(0),
1313 .ngpio = S3C64XX_GPIO_E_NR,
1314 .label = "GPE",
1315 },
1316 }, {
1317 .base = S3C64XX_GPG_BASE,
1318 .chip = {
1319 .base = S3C64XX_GPG(0),
1320 .ngpio = S3C64XX_GPIO_G_NR,
1321 .label = "GPG",
1322 },
1323 }, {
1324 .base = S3C64XX_GPM_BASE,
1325 .config = &samsung_gpio_cfgs[1],
1326 .chip = {
1327 .base = S3C64XX_GPM(0),
1328 .ngpio = S3C64XX_GPIO_M_NR,
1329 .label = "GPM",
1330 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1331 },
1332 },
1333#endif
1334};
1335
1336static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1337#ifdef CONFIG_PLAT_S3C64XX
1338 {
1339 .base = S3C64XX_GPH_BASE + 0x4,
1340 .chip = {
1341 .base = S3C64XX_GPH(0),
1342 .ngpio = S3C64XX_GPIO_H_NR,
1343 .label = "GPH",
1344 },
1345 }, {
1346 .base = S3C64XX_GPK_BASE + 0x4,
1347 .config = &samsung_gpio_cfgs[0],
1348 .chip = {
1349 .base = S3C64XX_GPK(0),
1350 .ngpio = S3C64XX_GPIO_K_NR,
1351 .label = "GPK",
1352 },
1353 }, {
1354 .base = S3C64XX_GPL_BASE + 0x4,
1355 .config = &samsung_gpio_cfgs[1],
1356 .chip = {
1357 .base = S3C64XX_GPL(0),
1358 .ngpio = S3C64XX_GPIO_L_NR,
1359 .label = "GPL",
1360 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1361 },
1362 },
1363#endif
1364};
1365
1366static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1367#ifdef CONFIG_PLAT_S3C64XX
1368 {
1369 .base = S3C64XX_GPF_BASE,
1370 .config = &samsung_gpio_cfgs[6],
1371 .chip = {
1372 .base = S3C64XX_GPF(0),
1373 .ngpio = S3C64XX_GPIO_F_NR,
1374 .label = "GPF",
1375 },
1376 }, {
1377 .config = &samsung_gpio_cfgs[7],
1378 .chip = {
1379 .base = S3C64XX_GPI(0),
1380 .ngpio = S3C64XX_GPIO_I_NR,
1381 .label = "GPI",
1382 },
1383 }, {
1384 .config = &samsung_gpio_cfgs[7],
1385 .chip = {
1386 .base = S3C64XX_GPJ(0),
1387 .ngpio = S3C64XX_GPIO_J_NR,
1388 .label = "GPJ",
1389 },
1390 }, {
1391 .config = &samsung_gpio_cfgs[6],
1392 .chip = {
1393 .base = S3C64XX_GPO(0),
1394 .ngpio = S3C64XX_GPIO_O_NR,
1395 .label = "GPO",
1396 },
1397 }, {
1398 .config = &samsung_gpio_cfgs[6],
1399 .chip = {
1400 .base = S3C64XX_GPP(0),
1401 .ngpio = S3C64XX_GPIO_P_NR,
1402 .label = "GPP",
1403 },
1404 }, {
1405 .config = &samsung_gpio_cfgs[6],
1406 .chip = {
1407 .base = S3C64XX_GPQ(0),
1408 .ngpio = S3C64XX_GPIO_Q_NR,
1409 .label = "GPQ",
1410 },
1411 }, {
1412 .base = S3C64XX_GPN_BASE,
1413 .irq_base = IRQ_EINT(0),
1414 .config = &samsung_gpio_cfgs[5],
1415 .chip = {
1416 .base = S3C64XX_GPN(0),
1417 .ngpio = S3C64XX_GPIO_N_NR,
1418 .label = "GPN",
1419 .to_irq = samsung_gpiolib_to_irq,
1420 },
1421 },
1422#endif
1423};
1424
1425/*
1426 * S5P6440 GPIO bank summary:
1427 *
1428 * Bank GPIOs Style SlpCon ExtInt Group
1429 * A 6 4Bit Yes 1
1430 * B 7 4Bit Yes 1
1431 * C 8 4Bit Yes 2
1432 * F 2 2Bit Yes 4 [1]
1433 * G 7 4Bit Yes 5
1434 * H 10 4Bit[2] Yes 6
1435 * I 16 2Bit Yes None
1436 * J 12 2Bit Yes None
1437 * N 16 2Bit No IRQ_EINT
1438 * P 8 2Bit Yes 8
1439 * R 15 4Bit[2] Yes 8
1440 */
1441
1442static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1443#ifdef CONFIG_CPU_S5P6440
1444 {
1445 .chip = {
1446 .base = S5P6440_GPA(0),
1447 .ngpio = S5P6440_GPIO_A_NR,
1448 .label = "GPA",
1449 },
1450 }, {
1451 .chip = {
1452 .base = S5P6440_GPB(0),
1453 .ngpio = S5P6440_GPIO_B_NR,
1454 .label = "GPB",
1455 },
1456 }, {
1457 .chip = {
1458 .base = S5P6440_GPC(0),
1459 .ngpio = S5P6440_GPIO_C_NR,
1460 .label = "GPC",
1461 },
1462 }, {
1463 .base = S5P64X0_GPG_BASE,
1464 .chip = {
1465 .base = S5P6440_GPG(0),
1466 .ngpio = S5P6440_GPIO_G_NR,
1467 .label = "GPG",
1468 },
1469 },
1470#endif
1471};
1472
1473static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1474#ifdef CONFIG_CPU_S5P6440
1475 {
1476 .base = S5P64X0_GPH_BASE + 0x4,
1477 .chip = {
1478 .base = S5P6440_GPH(0),
1479 .ngpio = S5P6440_GPIO_H_NR,
1480 .label = "GPH",
1481 },
1482 },
1483#endif
1484};
1485
1486static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1487#ifdef CONFIG_CPU_S5P6440
1488 {
1489 .base = S5P64X0_GPR_BASE + 0x4,
1490 .config = &s5p64x0_gpio_cfg_rbank,
1491 .chip = {
1492 .base = S5P6440_GPR(0),
1493 .ngpio = S5P6440_GPIO_R_NR,
1494 .label = "GPR",
1495 },
1496 },
1497#endif
1498};
1499
1500static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1501#ifdef CONFIG_CPU_S5P6440
1502 {
1503 .base = S5P64X0_GPF_BASE,
1504 .config = &samsung_gpio_cfgs[6],
1505 .chip = {
1506 .base = S5P6440_GPF(0),
1507 .ngpio = S5P6440_GPIO_F_NR,
1508 .label = "GPF",
1509 },
1510 }, {
1511 .base = S5P64X0_GPI_BASE,
1512 .config = &samsung_gpio_cfgs[4],
1513 .chip = {
1514 .base = S5P6440_GPI(0),
1515 .ngpio = S5P6440_GPIO_I_NR,
1516 .label = "GPI",
1517 },
1518 }, {
1519 .base = S5P64X0_GPJ_BASE,
1520 .config = &samsung_gpio_cfgs[4],
1521 .chip = {
1522 .base = S5P6440_GPJ(0),
1523 .ngpio = S5P6440_GPIO_J_NR,
1524 .label = "GPJ",
1525 },
1526 }, {
1527 .base = S5P64X0_GPN_BASE,
1528 .config = &samsung_gpio_cfgs[5],
1529 .chip = {
1530 .base = S5P6440_GPN(0),
1531 .ngpio = S5P6440_GPIO_N_NR,
1532 .label = "GPN",
1533 },
1534 }, {
1535 .base = S5P64X0_GPP_BASE,
1536 .config = &samsung_gpio_cfgs[6],
1537 .chip = {
1538 .base = S5P6440_GPP(0),
1539 .ngpio = S5P6440_GPIO_P_NR,
1540 .label = "GPP",
1541 },
1542 },
1543#endif
1544};
1545
1546/*
1547 * S5P6450 GPIO bank summary:
1548 *
1549 * Bank GPIOs Style SlpCon ExtInt Group
1550 * A 6 4Bit Yes 1
1551 * B 7 4Bit Yes 1
1552 * C 8 4Bit Yes 2
1553 * D 8 4Bit Yes None
1554 * F 2 2Bit Yes None
1555 * G 14 4Bit[2] Yes 5
1556 * H 10 4Bit[2] Yes 6
1557 * I 16 2Bit Yes None
1558 * J 12 2Bit Yes None
1559 * K 5 4Bit Yes None
1560 * N 16 2Bit No IRQ_EINT
1561 * P 11 2Bit Yes 8
1562 * Q 14 2Bit Yes None
1563 * R 15 4Bit[2] Yes None
1564 * S 8 2Bit Yes None
1565 *
1566 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1567 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1568 */
1569
1570static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1571#ifdef CONFIG_CPU_S5P6450
1572 {
1573 .chip = {
1574 .base = S5P6450_GPA(0),
1575 .ngpio = S5P6450_GPIO_A_NR,
1576 .label = "GPA",
1577 },
1578 }, {
1579 .chip = {
1580 .base = S5P6450_GPB(0),
1581 .ngpio = S5P6450_GPIO_B_NR,
1582 .label = "GPB",
1583 },
1584 }, {
1585 .chip = {
1586 .base = S5P6450_GPC(0),
1587 .ngpio = S5P6450_GPIO_C_NR,
1588 .label = "GPC",
1589 },
1590 }, {
1591 .chip = {
1592 .base = S5P6450_GPD(0),
1593 .ngpio = S5P6450_GPIO_D_NR,
1594 .label = "GPD",
1595 },
1596 }, {
1597 .base = S5P6450_GPK_BASE,
1598 .chip = {
1599 .base = S5P6450_GPK(0),
1600 .ngpio = S5P6450_GPIO_K_NR,
1601 .label = "GPK",
1602 },
1603 },
1604#endif
1605};
1606
1607static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1608#ifdef CONFIG_CPU_S5P6450
1609 {
1610 .base = S5P64X0_GPG_BASE + 0x4,
1611 .chip = {
1612 .base = S5P6450_GPG(0),
1613 .ngpio = S5P6450_GPIO_G_NR,
1614 .label = "GPG",
1615 },
1616 }, {
1617 .base = S5P64X0_GPH_BASE + 0x4,
1618 .chip = {
1619 .base = S5P6450_GPH(0),
1620 .ngpio = S5P6450_GPIO_H_NR,
1621 .label = "GPH",
1622 },
1623 },
1624#endif
1625};
1626
1627static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1628#ifdef CONFIG_CPU_S5P6450
1629 {
1630 .base = S5P64X0_GPR_BASE + 0x4,
1631 .config = &s5p64x0_gpio_cfg_rbank,
1632 .chip = {
1633 .base = S5P6450_GPR(0),
1634 .ngpio = S5P6450_GPIO_R_NR,
1635 .label = "GPR",
1636 },
1637 },
1638#endif
1639};
1640
1641static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1642#ifdef CONFIG_CPU_S5P6450
1643 {
1644 .base = S5P64X0_GPF_BASE,
1645 .config = &samsung_gpio_cfgs[6],
1646 .chip = {
1647 .base = S5P6450_GPF(0),
1648 .ngpio = S5P6450_GPIO_F_NR,
1649 .label = "GPF",
1650 },
1651 }, {
1652 .base = S5P64X0_GPI_BASE,
1653 .config = &samsung_gpio_cfgs[4],
1654 .chip = {
1655 .base = S5P6450_GPI(0),
1656 .ngpio = S5P6450_GPIO_I_NR,
1657 .label = "GPI",
1658 },
1659 }, {
1660 .base = S5P64X0_GPJ_BASE,
1661 .config = &samsung_gpio_cfgs[4],
1662 .chip = {
1663 .base = S5P6450_GPJ(0),
1664 .ngpio = S5P6450_GPIO_J_NR,
1665 .label = "GPJ",
1666 },
1667 }, {
1668 .base = S5P64X0_GPN_BASE,
1669 .config = &samsung_gpio_cfgs[5],
1670 .chip = {
1671 .base = S5P6450_GPN(0),
1672 .ngpio = S5P6450_GPIO_N_NR,
1673 .label = "GPN",
1674 },
1675 }, {
1676 .base = S5P64X0_GPP_BASE,
1677 .config = &samsung_gpio_cfgs[6],
1678 .chip = {
1679 .base = S5P6450_GPP(0),
1680 .ngpio = S5P6450_GPIO_P_NR,
1681 .label = "GPP",
1682 },
1683 }, {
1684 .base = S5P6450_GPQ_BASE,
1685 .config = &samsung_gpio_cfgs[5],
1686 .chip = {
1687 .base = S5P6450_GPQ(0),
1688 .ngpio = S5P6450_GPIO_Q_NR,
1689 .label = "GPQ",
1690 },
1691 }, {
1692 .base = S5P6450_GPS_BASE,
1693 .config = &samsung_gpio_cfgs[6],
1694 .chip = {
1695 .base = S5P6450_GPS(0),
1696 .ngpio = S5P6450_GPIO_S_NR,
1697 .label = "GPS",
1698 },
1699 },
1700#endif
1701};
1702
1703/*
1704 * S5PC100 GPIO bank summary:
1705 *
1706 * Bank GPIOs Style INT Type
1707 * A0 8 4Bit GPIO_INT0
1708 * A1 5 4Bit GPIO_INT1
1709 * B 8 4Bit GPIO_INT2
1710 * C 5 4Bit GPIO_INT3
1711 * D 7 4Bit GPIO_INT4
1712 * E0 8 4Bit GPIO_INT5
1713 * E1 6 4Bit GPIO_INT6
1714 * F0 8 4Bit GPIO_INT7
1715 * F1 8 4Bit GPIO_INT8
1716 * F2 8 4Bit GPIO_INT9
1717 * F3 4 4Bit GPIO_INT10
1718 * G0 8 4Bit GPIO_INT11
1719 * G1 3 4Bit GPIO_INT12
1720 * G2 7 4Bit GPIO_INT13
1721 * G3 7 4Bit GPIO_INT14
1722 * H0 8 4Bit WKUP_INT
1723 * H1 8 4Bit WKUP_INT
1724 * H2 8 4Bit WKUP_INT
1725 * H3 8 4Bit WKUP_INT
1726 * I 8 4Bit GPIO_INT15
1727 * J0 8 4Bit GPIO_INT16
1728 * J1 5 4Bit GPIO_INT17
1729 * J2 8 4Bit GPIO_INT18
1730 * J3 8 4Bit GPIO_INT19
1731 * J4 4 4Bit GPIO_INT20
1732 * K0 8 4Bit None
1733 * K1 6 4Bit None
1734 * K2 8 4Bit None
1735 * K3 8 4Bit None
1736 * L0 8 4Bit None
1737 * L1 8 4Bit None
1738 * L2 8 4Bit None
1739 * L3 8 4Bit None
1740 */
1741
1742static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1743#ifdef CONFIG_CPU_S5PC100
1744 {
1745 .chip = {
1746 .base = S5PC100_GPA0(0),
1747 .ngpio = S5PC100_GPIO_A0_NR,
1748 .label = "GPA0",
1749 },
1750 }, {
1751 .chip = {
1752 .base = S5PC100_GPA1(0),
1753 .ngpio = S5PC100_GPIO_A1_NR,
1754 .label = "GPA1",
1755 },
1756 }, {
1757 .chip = {
1758 .base = S5PC100_GPB(0),
1759 .ngpio = S5PC100_GPIO_B_NR,
1760 .label = "GPB",
1761 },
1762 }, {
1763 .chip = {
1764 .base = S5PC100_GPC(0),
1765 .ngpio = S5PC100_GPIO_C_NR,
1766 .label = "GPC",
1767 },
1768 }, {
1769 .chip = {
1770 .base = S5PC100_GPD(0),
1771 .ngpio = S5PC100_GPIO_D_NR,
1772 .label = "GPD",
1773 },
1774 }, {
1775 .chip = {
1776 .base = S5PC100_GPE0(0),
1777 .ngpio = S5PC100_GPIO_E0_NR,
1778 .label = "GPE0",
1779 },
1780 }, {
1781 .chip = {
1782 .base = S5PC100_GPE1(0),
1783 .ngpio = S5PC100_GPIO_E1_NR,
1784 .label = "GPE1",
1785 },
1786 }, {
1787 .chip = {
1788 .base = S5PC100_GPF0(0),
1789 .ngpio = S5PC100_GPIO_F0_NR,
1790 .label = "GPF0",
1791 },
1792 }, {
1793 .chip = {
1794 .base = S5PC100_GPF1(0),
1795 .ngpio = S5PC100_GPIO_F1_NR,
1796 .label = "GPF1",
1797 },
1798 }, {
1799 .chip = {
1800 .base = S5PC100_GPF2(0),
1801 .ngpio = S5PC100_GPIO_F2_NR,
1802 .label = "GPF2",
1803 },
1804 }, {
1805 .chip = {
1806 .base = S5PC100_GPF3(0),
1807 .ngpio = S5PC100_GPIO_F3_NR,
1808 .label = "GPF3",
1809 },
1810 }, {
1811 .chip = {
1812 .base = S5PC100_GPG0(0),
1813 .ngpio = S5PC100_GPIO_G0_NR,
1814 .label = "GPG0",
1815 },
1816 }, {
1817 .chip = {
1818 .base = S5PC100_GPG1(0),
1819 .ngpio = S5PC100_GPIO_G1_NR,
1820 .label = "GPG1",
1821 },
1822 }, {
1823 .chip = {
1824 .base = S5PC100_GPG2(0),
1825 .ngpio = S5PC100_GPIO_G2_NR,
1826 .label = "GPG2",
1827 },
1828 }, {
1829 .chip = {
1830 .base = S5PC100_GPG3(0),
1831 .ngpio = S5PC100_GPIO_G3_NR,
1832 .label = "GPG3",
1833 },
1834 }, {
1835 .chip = {
1836 .base = S5PC100_GPI(0),
1837 .ngpio = S5PC100_GPIO_I_NR,
1838 .label = "GPI",
1839 },
1840 }, {
1841 .chip = {
1842 .base = S5PC100_GPJ0(0),
1843 .ngpio = S5PC100_GPIO_J0_NR,
1844 .label = "GPJ0",
1845 },
1846 }, {
1847 .chip = {
1848 .base = S5PC100_GPJ1(0),
1849 .ngpio = S5PC100_GPIO_J1_NR,
1850 .label = "GPJ1",
1851 },
1852 }, {
1853 .chip = {
1854 .base = S5PC100_GPJ2(0),
1855 .ngpio = S5PC100_GPIO_J2_NR,
1856 .label = "GPJ2",
1857 },
1858 }, {
1859 .chip = {
1860 .base = S5PC100_GPJ3(0),
1861 .ngpio = S5PC100_GPIO_J3_NR,
1862 .label = "GPJ3",
1863 },
1864 }, {
1865 .chip = {
1866 .base = S5PC100_GPJ4(0),
1867 .ngpio = S5PC100_GPIO_J4_NR,
1868 .label = "GPJ4",
1869 },
1870 }, {
1871 .chip = {
1872 .base = S5PC100_GPK0(0),
1873 .ngpio = S5PC100_GPIO_K0_NR,
1874 .label = "GPK0",
1875 },
1876 }, {
1877 .chip = {
1878 .base = S5PC100_GPK1(0),
1879 .ngpio = S5PC100_GPIO_K1_NR,
1880 .label = "GPK1",
1881 },
1882 }, {
1883 .chip = {
1884 .base = S5PC100_GPK2(0),
1885 .ngpio = S5PC100_GPIO_K2_NR,
1886 .label = "GPK2",
1887 },
1888 }, {
1889 .chip = {
1890 .base = S5PC100_GPK3(0),
1891 .ngpio = S5PC100_GPIO_K3_NR,
1892 .label = "GPK3",
1893 },
1894 }, {
1895 .chip = {
1896 .base = S5PC100_GPL0(0),
1897 .ngpio = S5PC100_GPIO_L0_NR,
1898 .label = "GPL0",
1899 },
1900 }, {
1901 .chip = {
1902 .base = S5PC100_GPL1(0),
1903 .ngpio = S5PC100_GPIO_L1_NR,
1904 .label = "GPL1",
1905 },
1906 }, {
1907 .chip = {
1908 .base = S5PC100_GPL2(0),
1909 .ngpio = S5PC100_GPIO_L2_NR,
1910 .label = "GPL2",
1911 },
1912 }, {
1913 .chip = {
1914 .base = S5PC100_GPL3(0),
1915 .ngpio = S5PC100_GPIO_L3_NR,
1916 .label = "GPL3",
1917 },
1918 }, {
1919 .chip = {
1920 .base = S5PC100_GPL4(0),
1921 .ngpio = S5PC100_GPIO_L4_NR,
1922 .label = "GPL4",
1923 },
1924 }, {
1925 .base = (S5P_VA_GPIO + 0xC00),
1926 .irq_base = IRQ_EINT(0),
1927 .chip = {
1928 .base = S5PC100_GPH0(0),
1929 .ngpio = S5PC100_GPIO_H0_NR,
1930 .label = "GPH0",
1931 .to_irq = samsung_gpiolib_to_irq,
1932 },
1933 }, {
1934 .base = (S5P_VA_GPIO + 0xC20),
1935 .irq_base = IRQ_EINT(8),
1936 .chip = {
1937 .base = S5PC100_GPH1(0),
1938 .ngpio = S5PC100_GPIO_H1_NR,
1939 .label = "GPH1",
1940 .to_irq = samsung_gpiolib_to_irq,
1941 },
1942 }, {
1943 .base = (S5P_VA_GPIO + 0xC40),
1944 .irq_base = IRQ_EINT(16),
1945 .chip = {
1946 .base = S5PC100_GPH2(0),
1947 .ngpio = S5PC100_GPIO_H2_NR,
1948 .label = "GPH2",
1949 .to_irq = samsung_gpiolib_to_irq,
1950 },
1951 }, {
1952 .base = (S5P_VA_GPIO + 0xC60),
1953 .irq_base = IRQ_EINT(24),
1954 .chip = {
1955 .base = S5PC100_GPH3(0),
1956 .ngpio = S5PC100_GPIO_H3_NR,
1957 .label = "GPH3",
1958 .to_irq = samsung_gpiolib_to_irq,
1959 },
1960 },
1961#endif
1962};
1963
1964/*
1965 * Followings are the gpio banks in S5PV210/S5PC110
1966 *
1967 * The 'config' member when left to NULL, is initialized to the default
b391f8cf 1968 * structure samsung_gpio_cfgs[3] in the init function below.
1b39d5f2
KK		 1969 *
1970 * The 'base' member is also initialized in the init function below.
1971 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1972 * uses the above macro and depends on the banks being listed in order here.
1973 */
1974
1975static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1976#ifdef CONFIG_CPU_S5PV210
1977 {
1978 .chip = {
1979 .base = S5PV210_GPA0(0),
1980 .ngpio = S5PV210_GPIO_A0_NR,
1981 .label = "GPA0",
1982 },
1983 }, {
1984 .chip = {
1985 .base = S5PV210_GPA1(0),
1986 .ngpio = S5PV210_GPIO_A1_NR,
1987 .label = "GPA1",
1988 },
1989 }, {
1990 .chip = {
1991 .base = S5PV210_GPB(0),
1992 .ngpio = S5PV210_GPIO_B_NR,
1993 .label = "GPB",
1994 },
1995 }, {
1996 .chip = {
1997 .base = S5PV210_GPC0(0),
1998 .ngpio = S5PV210_GPIO_C0_NR,
1999 .label = "GPC0",
2000 },
2001 }, {
2002 .chip = {
2003 .base = S5PV210_GPC1(0),
2004 .ngpio = S5PV210_GPIO_C1_NR,
2005 .label = "GPC1",
2006 },
2007 }, {
2008 .chip = {
2009 .base = S5PV210_GPD0(0),
2010 .ngpio = S5PV210_GPIO_D0_NR,
2011 .label = "GPD0",
2012 },
2013 }, {
2014 .chip = {
2015 .base = S5PV210_GPD1(0),
2016 .ngpio = S5PV210_GPIO_D1_NR,
2017 .label = "GPD1",
2018 },
2019 }, {
2020 .chip = {
2021 .base = S5PV210_GPE0(0),
2022 .ngpio = S5PV210_GPIO_E0_NR,
2023 .label = "GPE0",
2024 },
2025 }, {
2026 .chip = {
2027 .base = S5PV210_GPE1(0),
2028 .ngpio = S5PV210_GPIO_E1_NR,
2029 .label = "GPE1",
2030 },
2031 }, {
2032 .chip = {
2033 .base = S5PV210_GPF0(0),
2034 .ngpio = S5PV210_GPIO_F0_NR,
2035 .label = "GPF0",
2036 },
2037 }, {
2038 .chip = {
2039 .base = S5PV210_GPF1(0),
2040 .ngpio = S5PV210_GPIO_F1_NR,
2041 .label = "GPF1",
2042 },
2043 }, {
2044 .chip = {
2045 .base = S5PV210_GPF2(0),
2046 .ngpio = S5PV210_GPIO_F2_NR,
2047 .label = "GPF2",
2048 },
2049 }, {
2050 .chip = {
2051 .base = S5PV210_GPF3(0),
2052 .ngpio = S5PV210_GPIO_F3_NR,
2053 .label = "GPF3",
2054 },
2055 }, {
2056 .chip = {
2057 .base = S5PV210_GPG0(0),
2058 .ngpio = S5PV210_GPIO_G0_NR,
2059 .label = "GPG0",
2060 },
2061 }, {
2062 .chip = {
2063 .base = S5PV210_GPG1(0),
2064 .ngpio = S5PV210_GPIO_G1_NR,
2065 .label = "GPG1",
2066 },
2067 }, {
2068 .chip = {
2069 .base = S5PV210_GPG2(0),
2070 .ngpio = S5PV210_GPIO_G2_NR,
2071 .label = "GPG2",
2072 },
2073 }, {
2074 .chip = {
2075 .base = S5PV210_GPG3(0),
2076 .ngpio = S5PV210_GPIO_G3_NR,
2077 .label = "GPG3",
2078 },
2079 }, {
2080 .chip = {
2081 .base = S5PV210_GPI(0),
2082 .ngpio = S5PV210_GPIO_I_NR,
2083 .label = "GPI",
2084 },
2085 }, {
2086 .chip = {
2087 .base = S5PV210_GPJ0(0),
2088 .ngpio = S5PV210_GPIO_J0_NR,
2089 .label = "GPJ0",
2090 },
2091 }, {
2092 .chip = {
2093 .base = S5PV210_GPJ1(0),
2094 .ngpio = S5PV210_GPIO_J1_NR,
2095 .label = "GPJ1",
2096 },
2097 }, {
2098 .chip = {
2099 .base = S5PV210_GPJ2(0),
2100 .ngpio = S5PV210_GPIO_J2_NR,
2101 .label = "GPJ2",
2102 },
2103 }, {
2104 .chip = {
2105 .base = S5PV210_GPJ3(0),
2106 .ngpio = S5PV210_GPIO_J3_NR,
2107 .label = "GPJ3",
2108 },
2109 }, {
2110 .chip = {
2111 .base = S5PV210_GPJ4(0),
2112 .ngpio = S5PV210_GPIO_J4_NR,
2113 .label = "GPJ4",
2114 },
2115 }, {
2116 .chip = {
2117 .base = S5PV210_MP01(0),
2118 .ngpio = S5PV210_GPIO_MP01_NR,
2119 .label = "MP01",
2120 },
2121 }, {
2122 .chip = {
2123 .base = S5PV210_MP02(0),
2124 .ngpio = S5PV210_GPIO_MP02_NR,
2125 .label = "MP02",
2126 },
2127 }, {
2128 .chip = {
2129 .base = S5PV210_MP03(0),
2130 .ngpio = S5PV210_GPIO_MP03_NR,
2131 .label = "MP03",
2132 },
2133 }, {
2134 .chip = {
2135 .base = S5PV210_MP04(0),
2136 .ngpio = S5PV210_GPIO_MP04_NR,
2137 .label = "MP04",
2138 },
2139 }, {
2140 .chip = {
2141 .base = S5PV210_MP05(0),
2142 .ngpio = S5PV210_GPIO_MP05_NR,
2143 .label = "MP05",
2144 },
2145 }, {
2146 .base = (S5P_VA_GPIO + 0xC00),
2147 .irq_base = IRQ_EINT(0),
2148 .chip = {
2149 .base = S5PV210_GPH0(0),
2150 .ngpio = S5PV210_GPIO_H0_NR,
2151 .label = "GPH0",
2152 .to_irq = samsung_gpiolib_to_irq,
2153 },
2154 }, {
2155 .base = (S5P_VA_GPIO + 0xC20),
2156 .irq_base = IRQ_EINT(8),
2157 .chip = {
2158 .base = S5PV210_GPH1(0),
2159 .ngpio = S5PV210_GPIO_H1_NR,
2160 .label = "GPH1",
2161 .to_irq = samsung_gpiolib_to_irq,
2162 },
2163 }, {
2164 .base = (S5P_VA_GPIO + 0xC40),
2165 .irq_base = IRQ_EINT(16),
2166 .chip = {
2167 .base = S5PV210_GPH2(0),
2168 .ngpio = S5PV210_GPIO_H2_NR,
2169 .label = "GPH2",
2170 .to_irq = samsung_gpiolib_to_irq,
2171 },
2172 }, {
2173 .base = (S5P_VA_GPIO + 0xC60),
2174 .irq_base = IRQ_EINT(24),
2175 .chip = {
2176 .base = S5PV210_GPH3(0),
2177 .ngpio = S5PV210_GPIO_H3_NR,
2178 .label = "GPH3",
2179 .to_irq = samsung_gpiolib_to_irq,
2180 },
2181 },
2182#endif
2183};
2184
2185/*
a9696d84 2186 * Followings are the gpio banks in EXYNOS SoCs
1b39d5f2
KK		 2187 *
2188 * The 'config' member when left to NULL, is initialized to the default
a9696d84 2189 * structure exynos_gpio_cfg in the init function below.
1b39d5f2
KK		 2190 *
2191 * The 'base' member is also initialized in the init function below.
2192 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2193 * uses the above macro and depends on the banks being listed in order here.
2194 */
2195
1b39d5f2 2196#ifdef CONFIG_ARCH_EXYNOS4
2760f7ad 2197static struct samsung_gpio_chip exynos4_gpios_1[] = {
1b39d5f2
KK		 2198 {
2199 .chip = {
2200 .base = EXYNOS4_GPA0(0),
2201 .ngpio = EXYNOS4_GPIO_A0_NR,
2202 .label = "GPA0",
2203 },
2204 }, {
2205 .chip = {
2206 .base = EXYNOS4_GPA1(0),
2207 .ngpio = EXYNOS4_GPIO_A1_NR,
2208 .label = "GPA1",
2209 },
2210 }, {
2211 .chip = {
2212 .base = EXYNOS4_GPB(0),
2213 .ngpio = EXYNOS4_GPIO_B_NR,
2214 .label = "GPB",
2215 },
2216 }, {
2217 .chip = {
2218 .base = EXYNOS4_GPC0(0),
2219 .ngpio = EXYNOS4_GPIO_C0_NR,
2220 .label = "GPC0",
2221 },
2222 }, {
2223 .chip = {
2224 .base = EXYNOS4_GPC1(0),
2225 .ngpio = EXYNOS4_GPIO_C1_NR,
2226 .label = "GPC1",
2227 },
2228 }, {
2229 .chip = {
2230 .base = EXYNOS4_GPD0(0),
2231 .ngpio = EXYNOS4_GPIO_D0_NR,
2232 .label = "GPD0",
2233 },
2234 }, {
2235 .chip = {
2236 .base = EXYNOS4_GPD1(0),
2237 .ngpio = EXYNOS4_GPIO_D1_NR,
2238 .label = "GPD1",
2239 },
2240 }, {
2241 .chip = {
2242 .base = EXYNOS4_GPE0(0),
2243 .ngpio = EXYNOS4_GPIO_E0_NR,
2244 .label = "GPE0",
2245 },
2246 }, {
2247 .chip = {
2248 .base = EXYNOS4_GPE1(0),
2249 .ngpio = EXYNOS4_GPIO_E1_NR,
2250 .label = "GPE1",
2251 },
2252 }, {
2253 .chip = {
2254 .base = EXYNOS4_GPE2(0),
2255 .ngpio = EXYNOS4_GPIO_E2_NR,
2256 .label = "GPE2",
2257 },
2258 }, {
2259 .chip = {
2260 .base = EXYNOS4_GPE3(0),
2261 .ngpio = EXYNOS4_GPIO_E3_NR,
2262 .label = "GPE3",
2263 },
2264 }, {
2265 .chip = {
2266 .base = EXYNOS4_GPE4(0),
2267 .ngpio = EXYNOS4_GPIO_E4_NR,
2268 .label = "GPE4",
2269 },
2270 }, {
2271 .chip = {
2272 .base = EXYNOS4_GPF0(0),
2273 .ngpio = EXYNOS4_GPIO_F0_NR,
2274 .label = "GPF0",
2275 },
2276 }, {
2277 .chip = {
2278 .base = EXYNOS4_GPF1(0),
2279 .ngpio = EXYNOS4_GPIO_F1_NR,
2280 .label = "GPF1",
2281 },
2282 }, {
2283 .chip = {
2284 .base = EXYNOS4_GPF2(0),
2285 .ngpio = EXYNOS4_GPIO_F2_NR,
2286 .label = "GPF2",
2287 },
2288 }, {
2289 .chip = {
2290 .base = EXYNOS4_GPF3(0),
2291 .ngpio = EXYNOS4_GPIO_F3_NR,
2292 .label = "GPF3",
2293 },
2294 },
1b39d5f2 2295};
2760f7ad 2296#endif
1b39d5f2 2297
1b39d5f2 2298#ifdef CONFIG_ARCH_EXYNOS4
2760f7ad 2299static struct samsung_gpio_chip exynos4_gpios_2[] = {
1b39d5f2
KK		 2300 {
2301 .chip = {
2302 .base = EXYNOS4_GPJ0(0),
2303 .ngpio = EXYNOS4_GPIO_J0_NR,
2304 .label = "GPJ0",
2305 },
2306 }, {
2307 .chip = {
2308 .base = EXYNOS4_GPJ1(0),
2309 .ngpio = EXYNOS4_GPIO_J1_NR,
2310 .label = "GPJ1",
2311 },
2312 }, {
2313 .chip = {
2314 .base = EXYNOS4_GPK0(0),
2315 .ngpio = EXYNOS4_GPIO_K0_NR,
2316 .label = "GPK0",
2317 },
2318 }, {
2319 .chip = {
2320 .base = EXYNOS4_GPK1(0),
2321 .ngpio = EXYNOS4_GPIO_K1_NR,
2322 .label = "GPK1",
2323 },
2324 }, {
2325 .chip = {
2326 .base = EXYNOS4_GPK2(0),
2327 .ngpio = EXYNOS4_GPIO_K2_NR,
2328 .label = "GPK2",
2329 },
2330 }, {
2331 .chip = {
2332 .base = EXYNOS4_GPK3(0),
2333 .ngpio = EXYNOS4_GPIO_K3_NR,
2334 .label = "GPK3",
2335 },
2336 }, {
2337 .chip = {
2338 .base = EXYNOS4_GPL0(0),
2339 .ngpio = EXYNOS4_GPIO_L0_NR,
2340 .label = "GPL0",
2341 },
2342 }, {
2343 .chip = {
2344 .base = EXYNOS4_GPL1(0),
2345 .ngpio = EXYNOS4_GPIO_L1_NR,
2346 .label = "GPL1",
2347 },
2348 }, {
2349 .chip = {
2350 .base = EXYNOS4_GPL2(0),
2351 .ngpio = EXYNOS4_GPIO_L2_NR,
2352 .label = "GPL2",
2353 },
2354 }, {
b82cee24 2355 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2356 .chip = {
2357 .base = EXYNOS4_GPY0(0),
2358 .ngpio = EXYNOS4_GPIO_Y0_NR,
2359 .label = "GPY0",
2360 },
2361 }, {
b82cee24 2362 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2363 .chip = {
2364 .base = EXYNOS4_GPY1(0),
2365 .ngpio = EXYNOS4_GPIO_Y1_NR,
2366 .label = "GPY1",
2367 },
2368 }, {
b82cee24 2369 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2370 .chip = {
2371 .base = EXYNOS4_GPY2(0),
2372 .ngpio = EXYNOS4_GPIO_Y2_NR,
2373 .label = "GPY2",
2374 },
2375 }, {
b82cee24 2376 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2377 .chip = {
2378 .base = EXYNOS4_GPY3(0),
2379 .ngpio = EXYNOS4_GPIO_Y3_NR,
2380 .label = "GPY3",
2381 },
2382 }, {
b82cee24 2383 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2384 .chip = {
2385 .base = EXYNOS4_GPY4(0),
2386 .ngpio = EXYNOS4_GPIO_Y4_NR,
2387 .label = "GPY4",
2388 },
2389 }, {
b82cee24 2390 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2391 .chip = {
2392 .base = EXYNOS4_GPY5(0),
2393 .ngpio = EXYNOS4_GPIO_Y5_NR,
2394 .label = "GPY5",
2395 },
2396 }, {
b82cee24 2397 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2398 .chip = {
2399 .base = EXYNOS4_GPY6(0),
2400 .ngpio = EXYNOS4_GPIO_Y6_NR,
2401 .label = "GPY6",
2402 },
2403 }, {
b82cee24 2404 .config = &samsung_gpio_cfgs[9],
1b39d5f2
KK		 2405 .irq_base = IRQ_EINT(0),
2406 .chip = {
2407 .base = EXYNOS4_GPX0(0),
2408 .ngpio = EXYNOS4_GPIO_X0_NR,
2409 .label = "GPX0",
2410 .to_irq = samsung_gpiolib_to_irq,
2411 },
2412 }, {
b82cee24 2413 .config = &samsung_gpio_cfgs[9],
1b39d5f2
KK		 2414 .irq_base = IRQ_EINT(8),
2415 .chip = {
2416 .base = EXYNOS4_GPX1(0),
2417 .ngpio = EXYNOS4_GPIO_X1_NR,
2418 .label = "GPX1",
2419 .to_irq = samsung_gpiolib_to_irq,
2420 },
2421 }, {
b82cee24 2422 .config = &samsung_gpio_cfgs[9],
1b39d5f2
KK		 2423 .irq_base = IRQ_EINT(16),
2424 .chip = {
2425 .base = EXYNOS4_GPX2(0),
2426 .ngpio = EXYNOS4_GPIO_X2_NR,
2427 .label = "GPX2",
2428 .to_irq = samsung_gpiolib_to_irq,
2429 },
2430 }, {
b82cee24 2431 .config = &samsung_gpio_cfgs[9],
1b39d5f2
KK		 2432 .irq_base = IRQ_EINT(24),
2433 .chip = {
2434 .base = EXYNOS4_GPX3(0),
2435 .ngpio = EXYNOS4_GPIO_X3_NR,
2436 .label = "GPX3",
2437 .to_irq = samsung_gpiolib_to_irq,
2438 },
2439 },
1b39d5f2 2440};
2760f7ad 2441#endif
1b39d5f2 2442
1b39d5f2 2443#ifdef CONFIG_ARCH_EXYNOS4
2760f7ad 2444static struct samsung_gpio_chip exynos4_gpios_3[] = {
1b39d5f2
KK		 2445 {
2446 .chip = {
2447 .base = EXYNOS4_GPZ(0),
2448 .ngpio = EXYNOS4_GPIO_Z_NR,
2449 .label = "GPZ",
2450 },
2451 },
1b39d5f2 2452};
2760f7ad 2453#endif
1b39d5f2 2454
a9696d84 2455#ifdef CONFIG_ARCH_EXYNOS5
9a5c7d6e 2456static struct samsung_gpio_chip exynos5_gpios_1[] = {
a9696d84
SP		 2457 {
2458 .chip = {
2459 .base = EXYNOS5_GPA0(0),
2460 .ngpio = EXYNOS5_GPIO_A0_NR,
2461 .label = "GPA0",
2462 },
2463 }, {
2464 .chip = {
2465 .base = EXYNOS5_GPA1(0),
2466 .ngpio = EXYNOS5_GPIO_A1_NR,
2467 .label = "GPA1",
2468 },
2469 }, {
2470 .chip = {
2471 .base = EXYNOS5_GPA2(0),
2472 .ngpio = EXYNOS5_GPIO_A2_NR,
2473 .label = "GPA2",
2474 },
2475 }, {
2476 .chip = {
2477 .base = EXYNOS5_GPB0(0),
2478 .ngpio = EXYNOS5_GPIO_B0_NR,
2479 .label = "GPB0",
2480 },
2481 }, {
2482 .chip = {
2483 .base = EXYNOS5_GPB1(0),
2484 .ngpio = EXYNOS5_GPIO_B1_NR,
2485 .label = "GPB1",
2486 },
2487 }, {
2488 .chip = {
2489 .base = EXYNOS5_GPB2(0),
2490 .ngpio = EXYNOS5_GPIO_B2_NR,
2491 .label = "GPB2",
2492 },
2493 }, {
2494 .chip = {
2495 .base = EXYNOS5_GPB3(0),
2496 .ngpio = EXYNOS5_GPIO_B3_NR,
2497 .label = "GPB3",
2498 },
2499 }, {
2500 .chip = {
2501 .base = EXYNOS5_GPC0(0),
2502 .ngpio = EXYNOS5_GPIO_C0_NR,
2503 .label = "GPC0",
2504 },
2505 }, {
2506 .chip = {
2507 .base = EXYNOS5_GPC1(0),
2508 .ngpio = EXYNOS5_GPIO_C1_NR,
2509 .label = "GPC1",
2510 },
2511 }, {
2512 .chip = {
2513 .base = EXYNOS5_GPC2(0),
2514 .ngpio = EXYNOS5_GPIO_C2_NR,
2515 .label = "GPC2",
2516 },
2517 }, {
2518 .chip = {
2519 .base = EXYNOS5_GPC3(0),
2520 .ngpio = EXYNOS5_GPIO_C3_NR,
2521 .label = "GPC3",
2522 },
2523 }, {
2524 .chip = {
2525 .base = EXYNOS5_GPD0(0),
2526 .ngpio = EXYNOS5_GPIO_D0_NR,
2527 .label = "GPD0",
2528 },
2529 }, {
2530 .chip = {
2531 .base = EXYNOS5_GPD1(0),
2532 .ngpio = EXYNOS5_GPIO_D1_NR,
2533 .label = "GPD1",
2534 },
2535 }, {
2536 .chip = {
2537 .base = EXYNOS5_GPY0(0),
2538 .ngpio = EXYNOS5_GPIO_Y0_NR,
2539 .label = "GPY0",
2540 },
2541 }, {
2542 .chip = {
2543 .base = EXYNOS5_GPY1(0),
2544 .ngpio = EXYNOS5_GPIO_Y1_NR,
2545 .label = "GPY1",
2546 },
2547 }, {
2548 .chip = {
2549 .base = EXYNOS5_GPY2(0),
2550 .ngpio = EXYNOS5_GPIO_Y2_NR,
2551 .label = "GPY2",
2552 },
2553 }, {
2554 .chip = {
2555 .base = EXYNOS5_GPY3(0),
2556 .ngpio = EXYNOS5_GPIO_Y3_NR,
2557 .label = "GPY3",
2558 },
2559 }, {
2560 .chip = {
2561 .base = EXYNOS5_GPY4(0),
2562 .ngpio = EXYNOS5_GPIO_Y4_NR,
2563 .label = "GPY4",
2564 },
2565 }, {
2566 .chip = {
2567 .base = EXYNOS5_GPY5(0),
2568 .ngpio = EXYNOS5_GPIO_Y5_NR,
2569 .label = "GPY5",
2570 },
2571 }, {
2572 .chip = {
2573 .base = EXYNOS5_GPY6(0),
2574 .ngpio = EXYNOS5_GPIO_Y6_NR,
2575 .label = "GPY6",
2576 },
f7093f3e
SP		 2577 }, {
2578 .chip = {
2579 .base = EXYNOS5_GPC4(0),
2580 .ngpio = EXYNOS5_GPIO_C4_NR,
2581 .label = "GPC4",
2582 },
a9696d84
SP		 2583 }, {
2584 .config = &samsung_gpio_cfgs[9],
2585 .irq_base = IRQ_EINT(0),
2586 .chip = {
2587 .base = EXYNOS5_GPX0(0),
2588 .ngpio = EXYNOS5_GPIO_X0_NR,
2589 .label = "GPX0",
2590 .to_irq = samsung_gpiolib_to_irq,
2591 },
2592 }, {
2593 .config = &samsung_gpio_cfgs[9],
2594 .irq_base = IRQ_EINT(8),
2595 .chip = {
2596 .base = EXYNOS5_GPX1(0),
2597 .ngpio = EXYNOS5_GPIO_X1_NR,
2598 .label = "GPX1",
2599 .to_irq = samsung_gpiolib_to_irq,
2600 },
2601 }, {
2602 .config = &samsung_gpio_cfgs[9],
2603 .irq_base = IRQ_EINT(16),
2604 .chip = {
2605 .base = EXYNOS5_GPX2(0),
2606 .ngpio = EXYNOS5_GPIO_X2_NR,
2607 .label = "GPX2",
2608 .to_irq = samsung_gpiolib_to_irq,
2609 },
2610 }, {
2611 .config = &samsung_gpio_cfgs[9],
2612 .irq_base = IRQ_EINT(24),
2613 .chip = {
2614 .base = EXYNOS5_GPX3(0),
2615 .ngpio = EXYNOS5_GPIO_X3_NR,
2616 .label = "GPX3",
2617 .to_irq = samsung_gpiolib_to_irq,
2618 },
2619 },
a9696d84 2620};
9a5c7d6e 2621#endif
a9696d84 2622
a9696d84 2623#ifdef CONFIG_ARCH_EXYNOS5
9a5c7d6e 2624static struct samsung_gpio_chip exynos5_gpios_2[] = {
a9696d84
SP		 2625 {
2626 .chip = {
2627 .base = EXYNOS5_GPE0(0),
2628 .ngpio = EXYNOS5_GPIO_E0_NR,
2629 .label = "GPE0",
2630 },
2631 }, {
2632 .chip = {
2633 .base = EXYNOS5_GPE1(0),
2634 .ngpio = EXYNOS5_GPIO_E1_NR,
2635 .label = "GPE1",
2636 },
2637 }, {
2638 .chip = {
2639 .base = EXYNOS5_GPF0(0),
2640 .ngpio = EXYNOS5_GPIO_F0_NR,
2641 .label = "GPF0",
2642 },
2643 }, {
2644 .chip = {
2645 .base = EXYNOS5_GPF1(0),
2646 .ngpio = EXYNOS5_GPIO_F1_NR,
2647 .label = "GPF1",
2648 },
2649 }, {
2650 .chip = {
2651 .base = EXYNOS5_GPG0(0),
2652 .ngpio = EXYNOS5_GPIO_G0_NR,
2653 .label = "GPG0",
2654 },
2655 }, {
2656 .chip = {
2657 .base = EXYNOS5_GPG1(0),
2658 .ngpio = EXYNOS5_GPIO_G1_NR,
2659 .label = "GPG1",
2660 },
2661 }, {
2662 .chip = {
2663 .base = EXYNOS5_GPG2(0),
2664 .ngpio = EXYNOS5_GPIO_G2_NR,
2665 .label = "GPG2",
2666 },
2667 }, {
2668 .chip = {
2669 .base = EXYNOS5_GPH0(0),
2670 .ngpio = EXYNOS5_GPIO_H0_NR,
2671 .label = "GPH0",
2672 },
2673 }, {
2674 .chip = {
2675 .base = EXYNOS5_GPH1(0),
2676 .ngpio = EXYNOS5_GPIO_H1_NR,
2677 .label = "GPH1",
2678
2679 },
2680 },
a9696d84 2681};
9a5c7d6e 2682#endif
a9696d84 2683
a9696d84 2684#ifdef CONFIG_ARCH_EXYNOS5
9a5c7d6e 2685static struct samsung_gpio_chip exynos5_gpios_3[] = {
a9696d84
SP		 2686 {
2687 .chip = {
2688 .base = EXYNOS5_GPV0(0),
2689 .ngpio = EXYNOS5_GPIO_V0_NR,
2690 .label = "GPV0",
2691 },
2692 }, {
2693 .chip = {
2694 .base = EXYNOS5_GPV1(0),
2695 .ngpio = EXYNOS5_GPIO_V1_NR,
2696 .label = "GPV1",
2697 },
2698 }, {
2699 .chip = {
2700 .base = EXYNOS5_GPV2(0),
2701 .ngpio = EXYNOS5_GPIO_V2_NR,
2702 .label = "GPV2",
2703 },
2704 }, {
2705 .chip = {
2706 .base = EXYNOS5_GPV3(0),
2707 .ngpio = EXYNOS5_GPIO_V3_NR,
2708 .label = "GPV3",
2709 },
2710 }, {
2711 .chip = {
2712 .base = EXYNOS5_GPV4(0),
2713 .ngpio = EXYNOS5_GPIO_V4_NR,
2714 .label = "GPV4",
2715 },
2716 },
a9696d84 2717};
9a5c7d6e 2718#endif
a9696d84 2719
a9696d84 2720#ifdef CONFIG_ARCH_EXYNOS5
9a5c7d6e 2721static struct samsung_gpio_chip exynos5_gpios_4[] = {
a9696d84
SP		 2722 {
2723 .chip = {
2724 .base = EXYNOS5_GPZ(0),
2725 .ngpio = EXYNOS5_GPIO_Z_NR,
2726 .label = "GPZ",
2727 },
2728 },
a9696d84 2729};
9a5c7d6e 2730#endif
a9696d84
SP		 2731
2732
2733#if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
2734static int exynos_gpio_xlate(struct gpio_chip *gc,
876cf5e7 2735 const struct of_phandle_args *gpiospec, u32 *flags)
659d73ad 2736{
876cf5e7 2737 unsigned int pin;
659d73ad
TA		 2738
2739 if (WARN_ON(gc->of_gpio_n_cells < 4))
2740 return -EINVAL;
2741
876cf5e7 2742 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
659d73ad
TA		 2743 return -EINVAL;
2744
876cf5e7
TA		 2745 if (gpiospec->args[0] > gc->ngpio)
2746 return -EINVAL;
2747
2748 pin = gc->base + gpiospec->args[0];
2749
2750 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
659d73ad 2751 pr_warn("gpio_xlate: failed to set pin function\n");
f447ed8b 2752 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
659d73ad 2753 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
876cf5e7 2754 if (s5p_gpio_set_drvstr(pin, gpiospec->args[3]))
659d73ad
TA		 2755 pr_warn("gpio_xlate: failed to set pin drive strength\n");
2756
f447ed8b
OJ		 2757 if (flags)
2758 *flags = gpiospec->args[2] >> 16;
2759
876cf5e7 2760 return gpiospec->args[0];
659d73ad
TA		 2761}
2762
a9696d84 2763static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
659d73ad
TA		 2764 { .compatible = "samsung,exynos4-gpio", },
2765 {}
2766};
2767
a9696d84
SP		 2768static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2769 u64 base, u64 offset)
659d73ad
TA		 2770{
2771 struct gpio_chip *gc = &chip->chip;
2772 u64 address;
2773
2774 if (!of_have_populated_dt())
2775 return;
2776
2777 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2778 gc->of_node = of_find_matching_node_by_address(NULL,
a9696d84 2779 exynos_gpio_dt_match, address);
659d73ad
TA		 2780 if (!gc->of_node) {
2781 pr_info("gpio: device tree node not found for gpio controller"
2782 " with base address %08llx\n", address);
2783 return;
2784 }
2785 gc->of_gpio_n_cells = 4;
a9696d84 2786 gc->of_xlate = exynos_gpio_xlate;
659d73ad 2787}
a9696d84
SP		 2788#elif defined(CONFIG_ARCH_EXYNOS)
2789static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2790 u64 base, u64 offset)
659d73ad
TA		 2791{
2792 return;
2793}
a9696d84 2794#endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
659d73ad 2795
fd454997
OJ		 2796static __init void exynos4_gpiolib_init(void)
2797{
2798#ifdef CONFIG_CPU_EXYNOS4210
2799 struct samsung_gpio_chip *chip;
2800 int i, nr_chips;
2801 void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
2802 int group = 0;
2803 void __iomem *gpx_base;
2804
d0586624
TA		 2805#ifdef CONFIG_PINCTRL_SAMSUNG
2806 /*
2807 * This gpio driver includes support for device tree support and
2808 * there are platforms using it. In order to maintain
2809 * compatibility with those platforms, and to allow non-dt
2810 * Exynos4210 platforms to use this gpiolib support, a check
2811 * is added to find out if there is a active pin-controller
2812 * driver support available. If it is available, this gpiolib
2813 * support is ignored and the gpiolib support available in
2814 * pin-controller driver is used. This is a temporary check and
2815 * will go away when all of the Exynos4210 platforms have
2816 * switched to using device tree and the pin-ctrl driver.
2817 */
2818 struct device_node *pctrl_np;
2819 const char *pctrl_compat = "samsung,pinctrl-exynos4210";
2820 pctrl_np = of_find_compatible_node(NULL, NULL, pctrl_compat);
2821 if (pctrl_np)
2822 if (of_device_is_available(pctrl_np))
2823 return;
2824#endif
2825
fd454997
OJ		 2826 /* gpio part1 */
2827 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2828 if (gpio_base1 == NULL) {
2829 pr_err("unable to ioremap for gpio_base1\n");
2830 goto err_ioremap1;
2831 }
2832
2833 chip = exynos4_gpios_1;
2834 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2835
2836 for (i = 0; i < nr_chips; i++, chip++) {
2837 if (!chip->config) {
2838 chip->config = &exynos_gpio_cfg;
2839 chip->group = group++;
2840 }
2841 exynos_gpiolib_attach_ofnode(chip,
2842 EXYNOS4_PA_GPIO1, i * 0x20);
2843 }
2844 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2845 nr_chips, gpio_base1);
2846
2847 /* gpio part2 */
2848 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2849 if (gpio_base2 == NULL) {
2850 pr_err("unable to ioremap for gpio_base2\n");
2851 goto err_ioremap2;
2852 }
2853
2854 /* need to set base address for gpx */
2855 chip = &exynos4_gpios_2[16];
2856 gpx_base = gpio_base2 + 0xC00;
2857 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2858 chip->base = gpx_base;
2859
2860 chip = exynos4_gpios_2;
2861 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2862
2863 for (i = 0; i < nr_chips; i++, chip++) {
2864 if (!chip->config) {
2865 chip->config = &exynos_gpio_cfg;
2866 chip->group = group++;
2867 }
2868 exynos_gpiolib_attach_ofnode(chip,
2869 EXYNOS4_PA_GPIO2, i * 0x20);
2870 }
2871 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2872 nr_chips, gpio_base2);
2873
2874 /* gpio part3 */
2875 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2876 if (gpio_base3 == NULL) {
2877 pr_err("unable to ioremap for gpio_base3\n");
2878 goto err_ioremap3;
2879 }
2880
2881 chip = exynos4_gpios_3;
2882 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2883
2884 for (i = 0; i < nr_chips; i++, chip++) {
2885 if (!chip->config) {
2886 chip->config = &exynos_gpio_cfg;
2887 chip->group = group++;
2888 }
2889 exynos_gpiolib_attach_ofnode(chip,
2890 EXYNOS4_PA_GPIO3, i * 0x20);
2891 }
2892 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2893 nr_chips, gpio_base3);
2894
2895#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2896 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2897 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2898#endif
2899
2900 return;
2901
2902err_ioremap3:
2903 iounmap(gpio_base2);
2904err_ioremap2:
2905 iounmap(gpio_base1);
2906err_ioremap1:
2907 return;
2908#endif /* CONFIG_CPU_EXYNOS4210 */
2909}
2910
2911static __init void exynos5_gpiolib_init(void)
2912{
2913#ifdef CONFIG_SOC_EXYNOS5250
2914 struct samsung_gpio_chip *chip;
2915 int i, nr_chips;
2916 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2917 int group = 0;
2918 void __iomem *gpx_base;
2919
2920 /* gpio part1 */
2921 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2922 if (gpio_base1 == NULL) {
2923 pr_err("unable to ioremap for gpio_base1\n");
2924 goto err_ioremap1;
2925 }
2926
30b84288 2927 /* need to set base address for gpc4 */
f7093f3e 2928 exynos5_gpios_1[20].base = gpio_base1 + 0x2E0;
30b84288 2929
fd454997 2930 /* need to set base address for gpx */
30b84288 2931 chip = &exynos5_gpios_1[21];
fd454997
OJ		 2932 gpx_base = gpio_base1 + 0xC00;
2933 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2934 chip->base = gpx_base;
2935
2936 chip = exynos5_gpios_1;
2937 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2938
2939 for (i = 0; i < nr_chips; i++, chip++) {
2940 if (!chip->config) {
2941 chip->config = &exynos_gpio_cfg;
2942 chip->group = group++;
2943 }
2944 exynos_gpiolib_attach_ofnode(chip,
2945 EXYNOS5_PA_GPIO1, i * 0x20);
2946 }
2947 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2948 nr_chips, gpio_base1);
2949
2950 /* gpio part2 */
2951 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2952 if (gpio_base2 == NULL) {
2953 pr_err("unable to ioremap for gpio_base2\n");
2954 goto err_ioremap2;
2955 }
2956
2957 chip = exynos5_gpios_2;
2958 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2959
2960 for (i = 0; i < nr_chips; i++, chip++) {
2961 if (!chip->config) {
2962 chip->config = &exynos_gpio_cfg;
2963 chip->group = group++;
2964 }
2965 exynos_gpiolib_attach_ofnode(chip,
2966 EXYNOS5_PA_GPIO2, i * 0x20);
2967 }
2968 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2969 nr_chips, gpio_base2);
2970
2971 /* gpio part3 */
2972 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2973 if (gpio_base3 == NULL) {
2974 pr_err("unable to ioremap for gpio_base3\n");
2975 goto err_ioremap3;
2976 }
2977
2978 /* need to set base address for gpv */
2979 exynos5_gpios_3[0].base = gpio_base3;
2980 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2981 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2982 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2983 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2984
2985 chip = exynos5_gpios_3;
2986 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2987
2988 for (i = 0; i < nr_chips; i++, chip++) {
2989 if (!chip->config) {
2990 chip->config = &exynos_gpio_cfg;
2991 chip->group = group++;
2992 }
2993 exynos_gpiolib_attach_ofnode(chip,
2994 EXYNOS5_PA_GPIO3, i * 0x20);
2995 }
2996 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2997 nr_chips, gpio_base3);
2998
2999 /* gpio part4 */
3000 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
3001 if (gpio_base4 == NULL) {
3002 pr_err("unable to ioremap for gpio_base4\n");
3003 goto err_ioremap4;
3004 }
3005
3006 chip = exynos5_gpios_4;
3007 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
3008
3009 for (i = 0; i < nr_chips; i++, chip++) {
3010 if (!chip->config) {
3011 chip->config = &exynos_gpio_cfg;
3012 chip->group = group++;
3013 }
3014 exynos_gpiolib_attach_ofnode(chip,
3015 EXYNOS5_PA_GPIO4, i * 0x20);
3016 }
3017 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
3018 nr_chips, gpio_base4);
3019 return;
3020
3021err_ioremap4:
3022 iounmap(gpio_base3);
3023err_ioremap3:
3024 iounmap(gpio_base2);
3025err_ioremap2:
3026 iounmap(gpio_base1);
3027err_ioremap1:
3028 return;
3029
3030#endif /* CONFIG_SOC_EXYNOS5250 */
3031}
3032
1b39d5f2
KK		 3033/* TODO: cleanup soc_is_* */
3034static __init int samsung_gpiolib_init(void)
3035{
3036 struct samsung_gpio_chip *chip;
3037 int i, nr_chips;
3038 int group = 0;
3039
3040 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
3041
3042 if (soc_is_s3c24xx()) {
3043 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
3044 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
3045 } else if (soc_is_s3c64xx()) {
3046 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
3047 ARRAY_SIZE(s3c64xx_gpios_2bit),
3048 S3C64XX_VA_GPIO + 0xE0, 0x20);
3049 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
3050 ARRAY_SIZE(s3c64xx_gpios_4bit),
3051 S3C64XX_VA_GPIO);
3052 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
3053 ARRAY_SIZE(s3c64xx_gpios_4bit2));
3054 } else if (soc_is_s5p6440()) {
3055 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
3056 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
3057 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
3058 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
3059 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
3060 ARRAY_SIZE(s5p6440_gpios_4bit2));
3061 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
3062 ARRAY_SIZE(s5p6440_gpios_rbank));
3063 } else if (soc_is_s5p6450()) {
3064 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
3065 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
3066 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
3067 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
3068 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
3069 ARRAY_SIZE(s5p6450_gpios_4bit2));
3070 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
3071 ARRAY_SIZE(s5p6450_gpios_rbank));
3072 } else if (soc_is_s5pc100()) {
3073 group = 0;
3074 chip = s5pc100_gpios_4bit;
3075 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
3076
3077 for (i = 0; i < nr_chips; i++, chip++) {
3078 if (!chip->config) {
b391f8cf 3079 chip->config = &samsung_gpio_cfgs[3];
1b39d5f2
KK		 3080 chip->group = group++;
3081 }
3082 }
3083 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
3084#if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
3085 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3086#endif
3087 } else if (soc_is_s5pv210()) {
3088 group = 0;
3089 chip = s5pv210_gpios_4bit;
3090 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
3091
3092 for (i = 0; i < nr_chips; i++, chip++) {
3093 if (!chip->config) {
b391f8cf 3094 chip->config = &samsung_gpio_cfgs[3];
1b39d5f2
KK		 3095 chip->group = group++;
3096 }
3097 }
3098 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
3099#if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
3100 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3101#endif
3102 } else if (soc_is_exynos4210()) {
fd454997 3103 exynos4_gpiolib_init();
a9696d84 3104 } else if (soc_is_exynos5250()) {
fd454997 3105 exynos5_gpiolib_init();
fbe92fcc
MB		 3106 } else {
3107 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
3108 return -ENODEV;
1b39d5f2
KK		 3109 }
3110
3111 return 0;
3112}
3113core_initcall(samsung_gpiolib_init);
3114
3115int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
3116{
3117 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3118 unsigned long flags;
3119 int offset;
3120 int ret;
3121
3122 if (!chip)
3123 return -EINVAL;
3124
3125 offset = pin - chip->chip.base;
3126
3127 samsung_gpio_lock(chip, flags);
3128 ret = samsung_gpio_do_setcfg(chip, offset, config);
3129 samsung_gpio_unlock(chip, flags);
3130
3131 return ret;
3132}
3133EXPORT_SYMBOL(s3c_gpio_cfgpin);
3134
3135int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
3136 unsigned int cfg)
3137{
3138 int ret;
3139
3140 for (; nr > 0; nr--, start++) {
3141 ret = s3c_gpio_cfgpin(start, cfg);
3142 if (ret != 0)
3143 return ret;
3144 }
3145
3146 return 0;
3147}
3148EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
3149
3150int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
3151 unsigned int cfg, samsung_gpio_pull_t pull)
3152{
3153 int ret;
3154
3155 for (; nr > 0; nr--, start++) {
3156 s3c_gpio_setpull(start, pull);
3157 ret = s3c_gpio_cfgpin(start, cfg);
3158 if (ret != 0)
3159 return ret;
3160 }
3161
3162 return 0;
3163}
3164EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
3165
3166unsigned s3c_gpio_getcfg(unsigned int pin)
3167{
3168 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3169 unsigned long flags;
3170 unsigned ret = 0;
3171 int offset;
3172
3173 if (chip) {
3174 offset = pin - chip->chip.base;
3175
3176 samsung_gpio_lock(chip, flags);
3177 ret = samsung_gpio_do_getcfg(chip, offset);
3178 samsung_gpio_unlock(chip, flags);
3179 }
3180
3181 return ret;
3182}
3183EXPORT_SYMBOL(s3c_gpio_getcfg);
3184
3185int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
3186{
3187 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3188 unsigned long flags;
3189 int offset, ret;
3190
3191 if (!chip)
3192 return -EINVAL;
3193
3194 offset = pin - chip->chip.base;
3195
3196 samsung_gpio_lock(chip, flags);
3197 ret = samsung_gpio_do_setpull(chip, offset, pull);
3198 samsung_gpio_unlock(chip, flags);
3199
3200 return ret;
3201}
3202EXPORT_SYMBOL(s3c_gpio_setpull);
3203
3204samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
3205{
3206 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3207 unsigned long flags;
3208 int offset;
3209 u32 pup = 0;
3210
3211 if (chip) {
3212 offset = pin - chip->chip.base;
3213
3214 samsung_gpio_lock(chip, flags);
3215 pup = samsung_gpio_do_getpull(chip, offset);
3216 samsung_gpio_unlock(chip, flags);
3217 }
3218
3219 return (__force samsung_gpio_pull_t)pup;
3220}
3221EXPORT_SYMBOL(s3c_gpio_getpull);
3222
1b39d5f2
KK		 3223#ifdef CONFIG_S5P_GPIO_DRVSTR
3224s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
3225{
3226 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3227 unsigned int off;
3228 void __iomem *reg;
3229 int shift;
3230 u32 drvstr;
3231
3232 if (!chip)
3233 return -EINVAL;
3234
3235 off = pin - chip->chip.base;
3236 shift = off * 2;
3237 reg = chip->base + 0x0C;
3238
3239 drvstr = __raw_readl(reg);
3240 drvstr = drvstr >> shift;
3241 drvstr &= 0x3;
3242
3243 return (__force s5p_gpio_drvstr_t)drvstr;
3244}
3245EXPORT_SYMBOL(s5p_gpio_get_drvstr);
3246
3247int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
3248{
3249 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3250 unsigned int off;
3251 void __iomem *reg;
3252 int shift;
3253 u32 tmp;
3254
3255 if (!chip)
3256 return -EINVAL;
3257
3258 off = pin - chip->chip.base;
3259 shift = off * 2;
3260 reg = chip->base + 0x0C;
3261
3262 tmp = __raw_readl(reg);
3263 tmp &= ~(0x3 << shift);
3264 tmp |= drvstr << shift;
3265
3266 __raw_writel(tmp, reg);
3267
3268 return 0;
3269}
3270EXPORT_SYMBOL(s5p_gpio_set_drvstr);
3271#endif /* CONFIG_S5P_GPIO_DRVSTR */
3272
3273#ifdef CONFIG_PLAT_S3C24XX
3274unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
3275{
3276 unsigned long flags;
3277 unsigned long misccr;
3278
3279 local_irq_save(flags);
3280 misccr = __raw_readl(S3C24XX_MISCCR);
3281 misccr &= ~clear;
3282 misccr ^= change;
3283 __raw_writel(misccr, S3C24XX_MISCCR);
3284 local_irq_restore(flags);
3285
3286 return misccr;
3287}
3288EXPORT_SYMBOL(s3c2410_modify_misccr);
3289#endif
Linux 6.x block layer and io_uring tree(s)