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ARM: S3C24XX: handle s3c2412 eints using new infrastructure
[linux-2.6-block.git] / drivers / gpio / gpio-samsung.c
CommitLineData
1b39d5f2
KK		 1/*
2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
9 *
10 * SAMSUNG - GPIOlib support
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/irq.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21#include <linux/init.h>
22#include <linux/spinlock.h>
23#include <linux/module.h>
24#include <linux/interrupt.h>
edbaa603 25#include <linux/device.h>
1b39d5f2 26#include <linux/ioport.h>
659d73ad
TA		 27#include <linux/of.h>
28#include <linux/slab.h>
29#include <linux/of_address.h>
1b39d5f2
KK		 30
31#include <asm/irq.h>
32
33#include <mach/hardware.h>
34#include <mach/map.h>
1b39d5f2
KK		 35#include <mach/regs-gpio.h>
36
37#include <plat/cpu.h>
38#include <plat/gpio-core.h>
39#include <plat/gpio-cfg.h>
40#include <plat/gpio-cfg-helpers.h>
1b39d5f2
KK		 41#include <plat/pm.h>
42
1b39d5f2
KK		 43int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
44 unsigned int off, samsung_gpio_pull_t pull)
45{
46 void __iomem *reg = chip->base + 0x08;
47 int shift = off * 2;
48 u32 pup;
49
50 pup = __raw_readl(reg);
51 pup &= ~(3 << shift);
52 pup |= pull << shift;
53 __raw_writel(pup, reg);
54
55 return 0;
56}
57
58samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
59 unsigned int off)
60{
61 void __iomem *reg = chip->base + 0x08;
62 int shift = off * 2;
63 u32 pup = __raw_readl(reg);
64
65 pup >>= shift;
66 pup &= 0x3;
67
68 return (__force samsung_gpio_pull_t)pup;
69}
70
71int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
72 unsigned int off, samsung_gpio_pull_t pull)
73{
74 switch (pull) {
75 case S3C_GPIO_PULL_NONE:
76 pull = 0x01;
77 break;
78 case S3C_GPIO_PULL_UP:
79 pull = 0x00;
80 break;
81 case S3C_GPIO_PULL_DOWN:
82 pull = 0x02;
83 break;
84 }
85 return samsung_gpio_setpull_updown(chip, off, pull);
86}
87
88samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
89 unsigned int off)
90{
91 samsung_gpio_pull_t pull;
92
93 pull = samsung_gpio_getpull_updown(chip, off);
94
95 switch (pull) {
96 case 0x00:
97 pull = S3C_GPIO_PULL_UP;
98 break;
99 case 0x01:
100 case 0x03:
101 pull = S3C_GPIO_PULL_NONE;
102 break;
103 case 0x02:
104 pull = S3C_GPIO_PULL_DOWN;
105 break;
106 }
107
108 return pull;
109}
110
111static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
112 unsigned int off, samsung_gpio_pull_t pull,
113 samsung_gpio_pull_t updown)
114{
115 void __iomem *reg = chip->base + 0x08;
116 u32 pup = __raw_readl(reg);
117
118 if (pull == updown)
119 pup &= ~(1 << off);
120 else if (pull == S3C_GPIO_PULL_NONE)
121 pup |= (1 << off);
122 else
123 return -EINVAL;
124
125 __raw_writel(pup, reg);
126 return 0;
127}
128
129static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
130 unsigned int off,
131 samsung_gpio_pull_t updown)
132{
133 void __iomem *reg = chip->base + 0x08;
134 u32 pup = __raw_readl(reg);
135
136 pup &= (1 << off);
137 return pup ? S3C_GPIO_PULL_NONE : updown;
138}
139
140samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
141 unsigned int off)
142{
143 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
144}
145
146int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
147 unsigned int off, samsung_gpio_pull_t pull)
148{
149 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
150}
151
152samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
153 unsigned int off)
154{
155 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
156}
157
158int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
159 unsigned int off, samsung_gpio_pull_t pull)
160{
161 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
162}
163
a9696d84 164static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
1b39d5f2
KK		 165 unsigned int off, samsung_gpio_pull_t pull)
166{
167 if (pull == S3C_GPIO_PULL_UP)
168 pull = 3;
169
170 return samsung_gpio_setpull_updown(chip, off, pull);
171}
172
a9696d84 173static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
1b39d5f2
KK		 174 unsigned int off)
175{
176 samsung_gpio_pull_t pull;
177
178 pull = samsung_gpio_getpull_updown(chip, off);
179
180 if (pull == 3)
181 pull = S3C_GPIO_PULL_UP;
182
183 return pull;
184}
185
186/*
187 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
188 * @chip: The gpio chip that is being configured.
189 * @off: The offset for the GPIO being configured.
190 * @cfg: The configuration value to set.
191 *
192 * This helper deal with the GPIO cases where the control register
193 * has two bits of configuration per gpio, which have the following
194 * functions:
195 * 00 = input
196 * 01 = output
197 * 1x = special function
198 */
199
200static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
201 unsigned int off, unsigned int cfg)
202{
203 void __iomem *reg = chip->base;
204 unsigned int shift = off * 2;
205 u32 con;
206
207 if (samsung_gpio_is_cfg_special(cfg)) {
208 cfg &= 0xf;
209 if (cfg > 3)
210 return -EINVAL;
211
212 cfg <<= shift;
213 }
214
215 con = __raw_readl(reg);
216 con &= ~(0x3 << shift);
217 con |= cfg;
218 __raw_writel(con, reg);
219
220 return 0;
221}
222
223/*
224 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
225 * @chip: The gpio chip that is being configured.
226 * @off: The offset for the GPIO being configured.
227 *
f1347599 228 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
1b39d5f2
KK		 229 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
230 * S3C_GPIO_SPECIAL() macro.
231 */
232
233static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
234 unsigned int off)
235{
236 u32 con;
237
238 con = __raw_readl(chip->base);
239 con >>= off * 2;
240 con &= 3;
241
242 /* this conversion works for IN and OUT as well as special mode */
243 return S3C_GPIO_SPECIAL(con);
244}
245
246/*
247 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
248 * @chip: The gpio chip that is being configured.
249 * @off: The offset for the GPIO being configured.
250 * @cfg: The configuration value to set.
251 *
252 * This helper deal with the GPIO cases where the control register has 4 bits
253 * of control per GPIO, generally in the form of:
254 * 0000 = Input
255 * 0001 = Output
256 * others = Special functions (dependent on bank)
257 *
258 * Note, since the code to deal with the case where there are two control
259 * registers instead of one, we do not have a separate set of functions for
260 * each case.
261 */
262
263static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
264 unsigned int off, unsigned int cfg)
265{
266 void __iomem *reg = chip->base;
267 unsigned int shift = (off & 7) * 4;
268 u32 con;
269
270 if (off < 8 && chip->chip.ngpio > 8)
271 reg -= 4;
272
273 if (samsung_gpio_is_cfg_special(cfg)) {
274 cfg &= 0xf;
275 cfg <<= shift;
276 }
277
278 con = __raw_readl(reg);
279 con &= ~(0xf << shift);
280 con |= cfg;
281 __raw_writel(con, reg);
282
283 return 0;
284}
285
286/*
287 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
288 * @chip: The gpio chip that is being configured.
289 * @off: The offset for the GPIO being configured.
290 *
291 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
292 * register setting into a value the software can use, such as could be passed
293 * to samsung_gpio_setcfg_4bit().
294 *
295 * @sa samsung_gpio_getcfg_2bit
296 */
297
298static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
299 unsigned int off)
300{
301 void __iomem *reg = chip->base;
302 unsigned int shift = (off & 7) * 4;
303 u32 con;
304
305 if (off < 8 && chip->chip.ngpio > 8)
306 reg -= 4;
307
308 con = __raw_readl(reg);
309 con >>= shift;
310 con &= 0xf;
311
312 /* this conversion works for IN and OUT as well as special mode */
313 return S3C_GPIO_SPECIAL(con);
314}
315
c034b184 316#ifdef CONFIG_PLAT_S3C24XX
1b39d5f2
KK		 317/*
318 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
319 * @chip: The gpio chip that is being configured.
320 * @off: The offset for the GPIO being configured.
321 * @cfg: The configuration value to set.
322 *
323 * This helper deal with the GPIO cases where the control register
324 * has one bit of configuration for the gpio, where setting the bit
325 * means the pin is in special function mode and unset means output.
326 */
327
328static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
329 unsigned int off, unsigned int cfg)
330{
331 void __iomem *reg = chip->base;
332 unsigned int shift = off;
333 u32 con;
334
335 if (samsung_gpio_is_cfg_special(cfg)) {
336 cfg &= 0xf;
337
338 /* Map output to 0, and SFN2 to 1 */
339 cfg -= 1;
340 if (cfg > 1)
341 return -EINVAL;
342
343 cfg <<= shift;
344 }
345
346 con = __raw_readl(reg);
347 con &= ~(0x1 << shift);
348 con |= cfg;
349 __raw_writel(con, reg);
350
351 return 0;
352}
353
354/*
355 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
356 * @chip: The gpio chip that is being configured.
357 * @off: The offset for the GPIO being configured.
358 *
359 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
360 * GPIO configuration value.
361 *
362 * @sa samsung_gpio_getcfg_2bit
363 * @sa samsung_gpio_getcfg_4bit
364 */
365
366static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
367 unsigned int off)
368{
369 u32 con;
370
371 con = __raw_readl(chip->base);
372 con >>= off;
373 con &= 1;
374 con++;
375
376 return S3C_GPIO_SFN(con);
377}
c034b184 378#endif
1b39d5f2 379
c034b184 380#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
1b39d5f2
KK		 381static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
382 unsigned int off, unsigned int cfg)
383{
384 void __iomem *reg = chip->base;
385 unsigned int shift;
386 u32 con;
387
388 switch (off) {
389 case 0:
390 case 1:
391 case 2:
392 case 3:
393 case 4:
394 case 5:
395 shift = (off & 7) * 4;
396 reg -= 4;
397 break;
398 case 6:
399 shift = ((off + 1) & 7) * 4;
400 reg -= 4;
401 default:
402 shift = ((off + 1) & 7) * 4;
403 break;
404 }
405
406 if (samsung_gpio_is_cfg_special(cfg)) {
407 cfg &= 0xf;
408 cfg <<= shift;
409 }
410
411 con = __raw_readl(reg);
412 con &= ~(0xf << shift);
413 con |= cfg;
414 __raw_writel(con, reg);
415
416 return 0;
417}
c034b184 418#endif
1b39d5f2
KK		 419
420static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
421 int nr_chips)
422{
423 for (; nr_chips > 0; nr_chips--, chipcfg++) {
424 if (!chipcfg->set_config)
425 chipcfg->set_config = samsung_gpio_setcfg_4bit;
426 if (!chipcfg->get_config)
427 chipcfg->get_config = samsung_gpio_getcfg_4bit;
428 if (!chipcfg->set_pull)
429 chipcfg->set_pull = samsung_gpio_setpull_updown;
430 if (!chipcfg->get_pull)
431 chipcfg->get_pull = samsung_gpio_getpull_updown;
432 }
433}
434
435struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
436 .set_config = samsung_gpio_setcfg_2bit,
437 .get_config = samsung_gpio_getcfg_2bit,
438};
439
c034b184 440#ifdef CONFIG_PLAT_S3C24XX
1b39d5f2
KK		 441static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
442 .set_config = s3c24xx_gpio_setcfg_abank,
443 .get_config = s3c24xx_gpio_getcfg_abank,
444};
c034b184 445#endif
1b39d5f2 446
dcb9c349 447#if defined(CONFIG_ARCH_EXYNOS4) || defined(CONFIG_SOC_EXYNOS5250)
a9696d84
SP		 448static struct samsung_gpio_cfg exynos_gpio_cfg = {
449 .set_pull = exynos_gpio_setpull,
450 .get_pull = exynos_gpio_getpull,
f79e40eb
MS		 451 .set_config = samsung_gpio_setcfg_4bit,
452 .get_config = samsung_gpio_getcfg_4bit,
1b39d5f2 453};
2760f7ad 454#endif
1b39d5f2 455
c034b184 456#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
1b39d5f2
KK		 457static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
458 .cfg_eint = 0x3,
459 .set_config = s5p64x0_gpio_setcfg_rbank,
460 .get_config = samsung_gpio_getcfg_4bit,
461 .set_pull = samsung_gpio_setpull_updown,
462 .get_pull = samsung_gpio_getpull_updown,
463};
c034b184 464#endif
1b39d5f2
KK		 465
466static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
2985479f 467 [0] = {
1b39d5f2 468 .cfg_eint = 0x0,
2985479f
MB		 469 },
470 [1] = {
1b39d5f2 471 .cfg_eint = 0x3,
2985479f
MB		 472 },
473 [2] = {
1b39d5f2 474 .cfg_eint = 0x7,
2985479f
MB		 475 },
476 [3] = {
1b39d5f2 477 .cfg_eint = 0xF,
2985479f
MB		 478 },
479 [4] = {
1b39d5f2
KK		 480 .cfg_eint = 0x0,
481 .set_config = samsung_gpio_setcfg_2bit,
482 .get_config = samsung_gpio_getcfg_2bit,
2985479f
MB		 483 },
484 [5] = {
1b39d5f2
KK		 485 .cfg_eint = 0x2,
486 .set_config = samsung_gpio_setcfg_2bit,
487 .get_config = samsung_gpio_getcfg_2bit,
2985479f
MB		 488 },
489 [6] = {
1b39d5f2
KK		 490 .cfg_eint = 0x3,
491 .set_config = samsung_gpio_setcfg_2bit,
492 .get_config = samsung_gpio_getcfg_2bit,
2985479f
MB		 493 },
494 [7] = {
1b39d5f2
KK		 495 .set_config = samsung_gpio_setcfg_2bit,
496 .get_config = samsung_gpio_getcfg_2bit,
2985479f
MB		 497 },
498 [8] = {
a9696d84
SP		 499 .set_pull = exynos_gpio_setpull,
500 .get_pull = exynos_gpio_getpull,
2985479f
MB		 501 },
502 [9] = {
b82cee24 503 .cfg_eint = 0x3,
a9696d84
SP		 504 .set_pull = exynos_gpio_setpull,
505 .get_pull = exynos_gpio_getpull,
b82cee24 506 }
1b39d5f2
KK		 507};
508
509/*
510 * Default routines for controlling GPIO, based on the original S3C24XX
511 * GPIO functions which deal with the case where each gpio bank of the
512 * chip is as following:
513 *
514 * base + 0x00: Control register, 2 bits per gpio
515 * gpio n: 2 bits starting at (2*n)
516 * 00 = input, 01 = output, others mean special-function
517 * base + 0x04: Data register, 1 bit per gpio
518 * bit n: data bit n
519*/
520
521static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
522{
523 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
524 void __iomem *base = ourchip->base;
525 unsigned long flags;
526 unsigned long con;
527
528 samsung_gpio_lock(ourchip, flags);
529
530 con = __raw_readl(base + 0x00);
531 con &= ~(3 << (offset * 2));
532
533 __raw_writel(con, base + 0x00);
534
535 samsung_gpio_unlock(ourchip, flags);
536 return 0;
537}
538
539static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
540 unsigned offset, int value)
541{
542 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
543 void __iomem *base = ourchip->base;
544 unsigned long flags;
545 unsigned long dat;
546 unsigned long con;
547
548 samsung_gpio_lock(ourchip, flags);
549
550 dat = __raw_readl(base + 0x04);
551 dat &= ~(1 << offset);
552 if (value)
553 dat |= 1 << offset;
554 __raw_writel(dat, base + 0x04);
555
556 con = __raw_readl(base + 0x00);
557 con &= ~(3 << (offset * 2));
558 con |= 1 << (offset * 2);
559
560 __raw_writel(con, base + 0x00);
561 __raw_writel(dat, base + 0x04);
562
563 samsung_gpio_unlock(ourchip, flags);
564 return 0;
565}
566
567/*
568 * The samsung_gpiolib_4bit routines are to control the gpio banks where
569 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
570 * following example:
571 *
572 * base + 0x00: Control register, 4 bits per gpio
573 * gpio n: 4 bits starting at (4*n)
574 * 0000 = input, 0001 = output, others mean special-function
575 * base + 0x04: Data register, 1 bit per gpio
576 * bit n: data bit n
577 *
578 * Note, since the data register is one bit per gpio and is at base + 0x4
579 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
580 * state of the output.
581 */
582
583static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
584 unsigned int offset)
585{
586 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
587 void __iomem *base = ourchip->base;
588 unsigned long con;
589
590 con = __raw_readl(base + GPIOCON_OFF);
2b88ff4a
EK		 591 if (ourchip->bitmap_gpio_int & BIT(offset))
592 con |= 0xf << con_4bit_shift(offset);
593 else
594 con &= ~(0xf << con_4bit_shift(offset));
1b39d5f2
KK		 595 __raw_writel(con, base + GPIOCON_OFF);
596
343db4bd 597 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
1b39d5f2
KK		 598
599 return 0;
600}
601
602static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
603 unsigned int offset, int value)
604{
605 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
606 void __iomem *base = ourchip->base;
607 unsigned long con;
608 unsigned long dat;
609
610 con = __raw_readl(base + GPIOCON_OFF);
611 con &= ~(0xf << con_4bit_shift(offset));
612 con |= 0x1 << con_4bit_shift(offset);
613
614 dat = __raw_readl(base + GPIODAT_OFF);
615
616 if (value)
617 dat |= 1 << offset;
618 else
619 dat &= ~(1 << offset);
620
621 __raw_writel(dat, base + GPIODAT_OFF);
622 __raw_writel(con, base + GPIOCON_OFF);
623 __raw_writel(dat, base + GPIODAT_OFF);
624
343db4bd 625 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
1b39d5f2
KK		 626
627 return 0;
628}
629
630/*
631 * The next set of routines are for the case where the GPIO configuration
632 * registers are 4 bits per GPIO but there is more than one register (the
633 * bank has more than 8 GPIOs.
634 *
635 * This case is the similar to the 4 bit case, but the registers are as
636 * follows:
637 *
638 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
639 * gpio n: 4 bits starting at (4*n)
640 * 0000 = input, 0001 = output, others mean special-function
641 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
642 * gpio n: 4 bits starting at (4*n)
643 * 0000 = input, 0001 = output, others mean special-function
644 * base + 0x08: Data register, 1 bit per gpio
645 * bit n: data bit n
646 *
647 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
648 * routines we store the 'base + 0x4' address so that these routines see
649 * the data register at ourchip->base + 0x04.
650 */
651
652static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
653 unsigned int offset)
654{
655 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
656 void __iomem *base = ourchip->base;
657 void __iomem *regcon = base;
658 unsigned long con;
659
660 if (offset > 7)
661 offset -= 8;
662 else
663 regcon -= 4;
664
665 con = __raw_readl(regcon);
666 con &= ~(0xf << con_4bit_shift(offset));
667 __raw_writel(con, regcon);
668
343db4bd 669 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
1b39d5f2
KK		 670
671 return 0;
672}
673
674static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
675 unsigned int offset, int value)
676{
677 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
678 void __iomem *base = ourchip->base;
679 void __iomem *regcon = base;
680 unsigned long con;
681 unsigned long dat;
682 unsigned con_offset = offset;
683
684 if (con_offset > 7)
685 con_offset -= 8;
686 else
687 regcon -= 4;
688
689 con = __raw_readl(regcon);
690 con &= ~(0xf << con_4bit_shift(con_offset));
691 con |= 0x1 << con_4bit_shift(con_offset);
692
693 dat = __raw_readl(base + GPIODAT_OFF);
694
695 if (value)
696 dat |= 1 << offset;
697 else
698 dat &= ~(1 << offset);
699
700 __raw_writel(dat, base + GPIODAT_OFF);
701 __raw_writel(con, regcon);
702 __raw_writel(dat, base + GPIODAT_OFF);
703
343db4bd 704 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
1b39d5f2
KK		 705
706 return 0;
707}
708
c034b184 709#ifdef CONFIG_PLAT_S3C24XX
1b39d5f2
KK		 710/* The next set of routines are for the case of s3c24xx bank a */
711
712static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
713{
714 return -EINVAL;
715}
716
717static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
718 unsigned offset, int value)
719{
720 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
721 void __iomem *base = ourchip->base;
722 unsigned long flags;
723 unsigned long dat;
724 unsigned long con;
725
726 local_irq_save(flags);
727
728 con = __raw_readl(base + 0x00);
729 dat = __raw_readl(base + 0x04);
730
731 dat &= ~(1 << offset);
732 if (value)
733 dat |= 1 << offset;
734
735 __raw_writel(dat, base + 0x04);
736
737 con &= ~(1 << offset);
738
739 __raw_writel(con, base + 0x00);
740 __raw_writel(dat, base + 0x04);
741
742 local_irq_restore(flags);
743 return 0;
744}
c034b184 745#endif
1b39d5f2
KK		 746
747/* The next set of routines are for the case of s5p64x0 bank r */
748
749static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
750 unsigned int offset)
751{
752 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
753 void __iomem *base = ourchip->base;
754 void __iomem *regcon = base;
755 unsigned long con;
756 unsigned long flags;
757
758 switch (offset) {
759 case 6:
760 offset += 1;
761 case 0:
762 case 1:
763 case 2:
764 case 3:
765 case 4:
766 case 5:
767 regcon -= 4;
768 break;
769 default:
770 offset -= 7;
771 break;
772 }
773
774 samsung_gpio_lock(ourchip, flags);
775
776 con = __raw_readl(regcon);
777 con &= ~(0xf << con_4bit_shift(offset));
778 __raw_writel(con, regcon);
779
780 samsung_gpio_unlock(ourchip, flags);
781
782 return 0;
783}
784
785static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
786 unsigned int offset, int value)
787{
788 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
789 void __iomem *base = ourchip->base;
790 void __iomem *regcon = base;
791 unsigned long con;
792 unsigned long dat;
793 unsigned long flags;
794 unsigned con_offset = offset;
795
796 switch (con_offset) {
797 case 6:
798 con_offset += 1;
799 case 0:
800 case 1:
801 case 2:
802 case 3:
803 case 4:
804 case 5:
805 regcon -= 4;
806 break;
807 default:
808 con_offset -= 7;
809 break;
810 }
811
812 samsung_gpio_lock(ourchip, flags);
813
814 con = __raw_readl(regcon);
815 con &= ~(0xf << con_4bit_shift(con_offset));
816 con |= 0x1 << con_4bit_shift(con_offset);
817
818 dat = __raw_readl(base + GPIODAT_OFF);
819 if (value)
820 dat |= 1 << offset;
821 else
822 dat &= ~(1 << offset);
823
824 __raw_writel(con, regcon);
825 __raw_writel(dat, base + GPIODAT_OFF);
826
827 samsung_gpio_unlock(ourchip, flags);
828
829 return 0;
830}
831
832static void samsung_gpiolib_set(struct gpio_chip *chip,
833 unsigned offset, int value)
834{
835 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
836 void __iomem *base = ourchip->base;
837 unsigned long flags;
838 unsigned long dat;
839
840 samsung_gpio_lock(ourchip, flags);
841
842 dat = __raw_readl(base + 0x04);
843 dat &= ~(1 << offset);
844 if (value)
845 dat |= 1 << offset;
846 __raw_writel(dat, base + 0x04);
847
848 samsung_gpio_unlock(ourchip, flags);
849}
850
851static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
852{
853 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
854 unsigned long val;
855
856 val = __raw_readl(ourchip->base + 0x04);
857 val >>= offset;
858 val &= 1;
859
860 return val;
861}
862
863/*
864 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
865 * for use with the configuration calls, and other parts of the s3c gpiolib
866 * support code.
867 *
868 * Not all s3c support code will need this, as some configurations of cpu
869 * may only support one or two different configuration options and have an
870 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
871 * the machine support file should provide its own samsung_gpiolib_getchip()
872 * and any other necessary functions.
873 */
874
875#ifdef CONFIG_S3C_GPIO_TRACK
876struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
877
878static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
879{
880 unsigned int gpn;
881 int i;
882
883 gpn = chip->chip.base;
884 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
885 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
886 s3c_gpios[gpn] = chip;
887 }
888}
889#endif /* CONFIG_S3C_GPIO_TRACK */
890
891/*
892 * samsung_gpiolib_add() - add the Samsung gpio_chip.
893 * @chip: The chip to register
894 *
895 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
896 * information and makes the necessary alterations for the platform and
897 * notes the information for use with the configuration systems and any
898 * other parts of the system.
899 */
900
901static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
902{
903 struct gpio_chip *gc = &chip->chip;
904 int ret;
905
906 BUG_ON(!chip->base);
907 BUG_ON(!gc->label);
908 BUG_ON(!gc->ngpio);
909
910 spin_lock_init(&chip->lock);
911
912 if (!gc->direction_input)
913 gc->direction_input = samsung_gpiolib_2bit_input;
914 if (!gc->direction_output)
915 gc->direction_output = samsung_gpiolib_2bit_output;
916 if (!gc->set)
917 gc->set = samsung_gpiolib_set;
918 if (!gc->get)
919 gc->get = samsung_gpiolib_get;
920
921#ifdef CONFIG_PM
922 if (chip->pm != NULL) {
923 if (!chip->pm->save || !chip->pm->resume)
343db4bd 924 pr_err("gpio: %s has missing PM functions\n",
1b39d5f2
KK		 925 gc->label);
926 } else
343db4bd 927 pr_err("gpio: %s has no PM function\n", gc->label);
1b39d5f2
KK		 928#endif
929
930 /* gpiochip_add() prints own failure message on error. */
931 ret = gpiochip_add(gc);
932 if (ret >= 0)
933 s3c_gpiolib_track(chip);
934}
935
172c6a13
HS		 936#if defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF)
937static int s3c24xx_gpio_xlate(struct gpio_chip *gc,
938 const struct of_phandle_args *gpiospec, u32 *flags)
939{
940 unsigned int pin;
941
942 if (WARN_ON(gc->of_gpio_n_cells < 3))
943 return -EINVAL;
944
945 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
946 return -EINVAL;
947
948 if (gpiospec->args[0] > gc->ngpio)
949 return -EINVAL;
950
951 pin = gc->base + gpiospec->args[0];
952
953 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
954 pr_warn("gpio_xlate: failed to set pin function\n");
955 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
956 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
957
958 if (flags)
959 *flags = gpiospec->args[2] >> 16;
960
961 return gpiospec->args[0];
962}
963
964static const struct of_device_id s3c24xx_gpio_dt_match[] __initdata = {
965 { .compatible = "samsung,s3c24xx-gpio", },
966 {}
967};
968
969static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
970 u64 base, u64 offset)
971{
972 struct gpio_chip *gc = &chip->chip;
973 u64 address;
974
975 if (!of_have_populated_dt())
976 return;
977
978 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
979 gc->of_node = of_find_matching_node_by_address(NULL,
980 s3c24xx_gpio_dt_match, address);
981 if (!gc->of_node) {
982 pr_info("gpio: device tree node not found for gpio controller"
983 " with base address %08llx\n", address);
984 return;
985 }
986 gc->of_gpio_n_cells = 3;
987 gc->of_xlate = s3c24xx_gpio_xlate;
988}
989#else
990static __init void s3c24xx_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
991 u64 base, u64 offset)
992{
993 return;
994}
995#endif /* defined(CONFIG_PLAT_S3C24XX) && defined(CONFIG_OF) */
996
1b39d5f2
KK		 997static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
998 int nr_chips, void __iomem *base)
999{
1000 int i;
1001 struct gpio_chip *gc = &chip->chip;
1002
1003 for (i = 0 ; i < nr_chips; i++, chip++) {
8a8ab2e6
PK		 1004 /* skip banks not present on SoC */
1005 if (chip->chip.base >= S3C_GPIO_END)
1006 continue;
1007
1b39d5f2
KK		 1008 if (!chip->config)
1009 chip->config = &s3c24xx_gpiocfg_default;
1010 if (!chip->pm)
1011 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1012 if ((base != NULL) && (chip->base == NULL))
1013 chip->base = base + ((i) * 0x10);
1014
1015 if (!gc->direction_input)
1016 gc->direction_input = samsung_gpiolib_2bit_input;
1017 if (!gc->direction_output)
1018 gc->direction_output = samsung_gpiolib_2bit_output;
1019
1020 samsung_gpiolib_add(chip);
172c6a13
HS		 1021
1022 s3c24xx_gpiolib_attach_ofnode(chip, S3C24XX_PA_GPIO, i * 0x10);
1b39d5f2
KK		 1023 }
1024}
1025
1026static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
1027 int nr_chips, void __iomem *base,
1028 unsigned int offset)
1029{
1030 int i;
1031
1032 for (i = 0 ; i < nr_chips; i++, chip++) {
1033 chip->chip.direction_input = samsung_gpiolib_2bit_input;
1034 chip->chip.direction_output = samsung_gpiolib_2bit_output;
1035
1036 if (!chip->config)
1037 chip->config = &samsung_gpio_cfgs[7];
1038 if (!chip->pm)
1039 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
1040 if ((base != NULL) && (chip->base == NULL))
1041 chip->base = base + ((i) * offset);
1042
1043 samsung_gpiolib_add(chip);
1044 }
1045}
1046
1047/*
1048 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
1049 * @chip: The gpio chip that is being configured.
1050 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
1051 *
1052 * This helper deal with the GPIO cases where the control register has 4 bits
1053 * of control per GPIO, generally in the form of:
1054 * 0000 = Input
1055 * 0001 = Output
1056 * others = Special functions (dependent on bank)
1057 *
1058 * Note, since the code to deal with the case where there are two control
1059 * registers instead of one, we do not have a separate set of function
1060 * (samsung_gpiolib_add_4bit2_chips)for each case.
1061 */
1062
1063static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
1064 int nr_chips, void __iomem *base)
1065{
1066 int i;
1067
1068 for (i = 0 ; i < nr_chips; i++, chip++) {
1069 chip->chip.direction_input = samsung_gpiolib_4bit_input;
1070 chip->chip.direction_output = samsung_gpiolib_4bit_output;
1071
1072 if (!chip->config)
1073 chip->config = &samsung_gpio_cfgs[2];
1074 if (!chip->pm)
1075 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1076 if ((base != NULL) && (chip->base == NULL))
1077 chip->base = base + ((i) * 0x20);
1078
2b88ff4a
EK		 1079 chip->bitmap_gpio_int = 0;
1080
1b39d5f2
KK		 1081 samsung_gpiolib_add(chip);
1082 }
1083}
1084
1085static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
1086 int nr_chips)
1087{
1088 for (; nr_chips > 0; nr_chips--, chip++) {
1089 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
1090 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
1091
1092 if (!chip->config)
1093 chip->config = &samsung_gpio_cfgs[2];
1094 if (!chip->pm)
1095 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1096
1097 samsung_gpiolib_add(chip);
1098 }
1099}
1100
1101static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1102 int nr_chips)
1103{
1104 for (; nr_chips > 0; nr_chips--, chip++) {
1105 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1106 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1107
1108 if (!chip->pm)
1109 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1110
1111 samsung_gpiolib_add(chip);
1112 }
1113}
1114
1115int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1116{
1117 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
1118
1119 return samsung_chip->irq_base + offset;
1120}
1121
1122#ifdef CONFIG_PLAT_S3C24XX
1123static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
1124{
1125 if (offset < 4)
1c8408e3
HS		 1126 if (soc_is_s3c2412())
1127 return IRQ_EINT0_2412 + offset;
1128 else
1129 return IRQ_EINT0 + offset;
1b39d5f2
KK		 1130
1131 if (offset < 8)
1132 return IRQ_EINT4 + offset - 4;
1133
1134 return -EINVAL;
1135}
1136#endif
1137
1138#ifdef CONFIG_PLAT_S3C64XX
1139static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
1140{
1141 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
1142}
1143
1144static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
1145{
1146 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
1147}
1148#endif
1149
1150struct samsung_gpio_chip s3c24xx_gpios[] = {
1151#ifdef CONFIG_PLAT_S3C24XX
1152 {
1153 .config = &s3c24xx_gpiocfg_banka,
1154 .chip = {
1155 .base = S3C2410_GPA(0),
1156 .owner = THIS_MODULE,
1157 .label = "GPIOA",
1158 .ngpio = 24,
1159 .direction_input = s3c24xx_gpiolib_banka_input,
1160 .direction_output = s3c24xx_gpiolib_banka_output,
1161 },
1162 }, {
1163 .chip = {
1164 .base = S3C2410_GPB(0),
1165 .owner = THIS_MODULE,
1166 .label = "GPIOB",
1167 .ngpio = 16,
1168 },
1169 }, {
1170 .chip = {
1171 .base = S3C2410_GPC(0),
1172 .owner = THIS_MODULE,
1173 .label = "GPIOC",
1174 .ngpio = 16,
1175 },
1176 }, {
1177 .chip = {
1178 .base = S3C2410_GPD(0),
1179 .owner = THIS_MODULE,
1180 .label = "GPIOD",
1181 .ngpio = 16,
1182 },
1183 }, {
1184 .chip = {
1185 .base = S3C2410_GPE(0),
1186 .label = "GPIOE",
1187 .owner = THIS_MODULE,
1188 .ngpio = 16,
1189 },
1190 }, {
1191 .chip = {
1192 .base = S3C2410_GPF(0),
1193 .owner = THIS_MODULE,
1194 .label = "GPIOF",
1195 .ngpio = 8,
1196 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
1197 },
1198 }, {
1199 .irq_base = IRQ_EINT8,
1200 .chip = {
1201 .base = S3C2410_GPG(0),
1202 .owner = THIS_MODULE,
1203 .label = "GPIOG",
1204 .ngpio = 16,
1205 .to_irq = samsung_gpiolib_to_irq,
1206 },
1207 }, {
1208 .chip = {
1209 .base = S3C2410_GPH(0),
1210 .owner = THIS_MODULE,
1211 .label = "GPIOH",
1212 .ngpio = 11,
1213 },
1214 },
1215 /* GPIOS for the S3C2443 and later devices. */
1216 {
1217 .base = S3C2440_GPJCON,
1218 .chip = {
1219 .base = S3C2410_GPJ(0),
1220 .owner = THIS_MODULE,
1221 .label = "GPIOJ",
1222 .ngpio = 16,
1223 },
1224 }, {
1225 .base = S3C2443_GPKCON,
1226 .chip = {
1227 .base = S3C2410_GPK(0),
1228 .owner = THIS_MODULE,
1229 .label = "GPIOK",
1230 .ngpio = 16,
1231 },
1232 }, {
1233 .base = S3C2443_GPLCON,
1234 .chip = {
1235 .base = S3C2410_GPL(0),
1236 .owner = THIS_MODULE,
1237 .label = "GPIOL",
1238 .ngpio = 15,
1239 },
1240 }, {
1241 .base = S3C2443_GPMCON,
1242 .chip = {
1243 .base = S3C2410_GPM(0),
1244 .owner = THIS_MODULE,
1245 .label = "GPIOM",
1246 .ngpio = 2,
1247 },
1248 },
1249#endif
1250};
1251
1252/*
1253 * GPIO bank summary:
1254 *
1255 * Bank GPIOs Style SlpCon ExtInt Group
1256 * A 8 4Bit Yes 1
1257 * B 7 4Bit Yes 1
1258 * C 8 4Bit Yes 2
1259 * D 5 4Bit Yes 3
1260 * E 5 4Bit Yes None
1261 * F 16 2Bit Yes 4 [1]
1262 * G 7 4Bit Yes 5
1263 * H 10 4Bit[2] Yes 6
1264 * I 16 2Bit Yes None
1265 * J 12 2Bit Yes None
1266 * K 16 4Bit[2] No None
1267 * L 15 4Bit[2] No None
1268 * M 6 4Bit No IRQ_EINT
1269 * N 16 2Bit No IRQ_EINT
1270 * O 16 2Bit Yes 7
1271 * P 15 2Bit Yes 8
1272 * Q 9 2Bit Yes 9
1273 *
1274 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1275 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1276 */
1277
1278static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1279#ifdef CONFIG_PLAT_S3C64XX
1280 {
1281 .chip = {
1282 .base = S3C64XX_GPA(0),
1283 .ngpio = S3C64XX_GPIO_A_NR,
1284 .label = "GPA",
1285 },
1286 }, {
1287 .chip = {
1288 .base = S3C64XX_GPB(0),
1289 .ngpio = S3C64XX_GPIO_B_NR,
1290 .label = "GPB",
1291 },
1292 }, {
1293 .chip = {
1294 .base = S3C64XX_GPC(0),
1295 .ngpio = S3C64XX_GPIO_C_NR,
1296 .label = "GPC",
1297 },
1298 }, {
1299 .chip = {
1300 .base = S3C64XX_GPD(0),
1301 .ngpio = S3C64XX_GPIO_D_NR,
1302 .label = "GPD",
1303 },
1304 }, {
1305 .config = &samsung_gpio_cfgs[0],
1306 .chip = {
1307 .base = S3C64XX_GPE(0),
1308 .ngpio = S3C64XX_GPIO_E_NR,
1309 .label = "GPE",
1310 },
1311 }, {
1312 .base = S3C64XX_GPG_BASE,
1313 .chip = {
1314 .base = S3C64XX_GPG(0),
1315 .ngpio = S3C64XX_GPIO_G_NR,
1316 .label = "GPG",
1317 },
1318 }, {
1319 .base = S3C64XX_GPM_BASE,
1320 .config = &samsung_gpio_cfgs[1],
1321 .chip = {
1322 .base = S3C64XX_GPM(0),
1323 .ngpio = S3C64XX_GPIO_M_NR,
1324 .label = "GPM",
1325 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1326 },
1327 },
1328#endif
1329};
1330
1331static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1332#ifdef CONFIG_PLAT_S3C64XX
1333 {
1334 .base = S3C64XX_GPH_BASE + 0x4,
1335 .chip = {
1336 .base = S3C64XX_GPH(0),
1337 .ngpio = S3C64XX_GPIO_H_NR,
1338 .label = "GPH",
1339 },
1340 }, {
1341 .base = S3C64XX_GPK_BASE + 0x4,
1342 .config = &samsung_gpio_cfgs[0],
1343 .chip = {
1344 .base = S3C64XX_GPK(0),
1345 .ngpio = S3C64XX_GPIO_K_NR,
1346 .label = "GPK",
1347 },
1348 }, {
1349 .base = S3C64XX_GPL_BASE + 0x4,
1350 .config = &samsung_gpio_cfgs[1],
1351 .chip = {
1352 .base = S3C64XX_GPL(0),
1353 .ngpio = S3C64XX_GPIO_L_NR,
1354 .label = "GPL",
1355 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1356 },
1357 },
1358#endif
1359};
1360
1361static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1362#ifdef CONFIG_PLAT_S3C64XX
1363 {
1364 .base = S3C64XX_GPF_BASE,
1365 .config = &samsung_gpio_cfgs[6],
1366 .chip = {
1367 .base = S3C64XX_GPF(0),
1368 .ngpio = S3C64XX_GPIO_F_NR,
1369 .label = "GPF",
1370 },
1371 }, {
1372 .config = &samsung_gpio_cfgs[7],
1373 .chip = {
1374 .base = S3C64XX_GPI(0),
1375 .ngpio = S3C64XX_GPIO_I_NR,
1376 .label = "GPI",
1377 },
1378 }, {
1379 .config = &samsung_gpio_cfgs[7],
1380 .chip = {
1381 .base = S3C64XX_GPJ(0),
1382 .ngpio = S3C64XX_GPIO_J_NR,
1383 .label = "GPJ",
1384 },
1385 }, {
1386 .config = &samsung_gpio_cfgs[6],
1387 .chip = {
1388 .base = S3C64XX_GPO(0),
1389 .ngpio = S3C64XX_GPIO_O_NR,
1390 .label = "GPO",
1391 },
1392 }, {
1393 .config = &samsung_gpio_cfgs[6],
1394 .chip = {
1395 .base = S3C64XX_GPP(0),
1396 .ngpio = S3C64XX_GPIO_P_NR,
1397 .label = "GPP",
1398 },
1399 }, {
1400 .config = &samsung_gpio_cfgs[6],
1401 .chip = {
1402 .base = S3C64XX_GPQ(0),
1403 .ngpio = S3C64XX_GPIO_Q_NR,
1404 .label = "GPQ",
1405 },
1406 }, {
1407 .base = S3C64XX_GPN_BASE,
1408 .irq_base = IRQ_EINT(0),
1409 .config = &samsung_gpio_cfgs[5],
1410 .chip = {
1411 .base = S3C64XX_GPN(0),
1412 .ngpio = S3C64XX_GPIO_N_NR,
1413 .label = "GPN",
1414 .to_irq = samsung_gpiolib_to_irq,
1415 },
1416 },
1417#endif
1418};
1419
1420/*
1421 * S5P6440 GPIO bank summary:
1422 *
1423 * Bank GPIOs Style SlpCon ExtInt Group
1424 * A 6 4Bit Yes 1
1425 * B 7 4Bit Yes 1
1426 * C 8 4Bit Yes 2
1427 * F 2 2Bit Yes 4 [1]
1428 * G 7 4Bit Yes 5
1429 * H 10 4Bit[2] Yes 6
1430 * I 16 2Bit Yes None
1431 * J 12 2Bit Yes None
1432 * N 16 2Bit No IRQ_EINT
1433 * P 8 2Bit Yes 8
1434 * R 15 4Bit[2] Yes 8
1435 */
1436
1437static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1438#ifdef CONFIG_CPU_S5P6440
1439 {
1440 .chip = {
1441 .base = S5P6440_GPA(0),
1442 .ngpio = S5P6440_GPIO_A_NR,
1443 .label = "GPA",
1444 },
1445 }, {
1446 .chip = {
1447 .base = S5P6440_GPB(0),
1448 .ngpio = S5P6440_GPIO_B_NR,
1449 .label = "GPB",
1450 },
1451 }, {
1452 .chip = {
1453 .base = S5P6440_GPC(0),
1454 .ngpio = S5P6440_GPIO_C_NR,
1455 .label = "GPC",
1456 },
1457 }, {
1458 .base = S5P64X0_GPG_BASE,
1459 .chip = {
1460 .base = S5P6440_GPG(0),
1461 .ngpio = S5P6440_GPIO_G_NR,
1462 .label = "GPG",
1463 },
1464 },
1465#endif
1466};
1467
1468static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1469#ifdef CONFIG_CPU_S5P6440
1470 {
1471 .base = S5P64X0_GPH_BASE + 0x4,
1472 .chip = {
1473 .base = S5P6440_GPH(0),
1474 .ngpio = S5P6440_GPIO_H_NR,
1475 .label = "GPH",
1476 },
1477 },
1478#endif
1479};
1480
1481static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1482#ifdef CONFIG_CPU_S5P6440
1483 {
1484 .base = S5P64X0_GPR_BASE + 0x4,
1485 .config = &s5p64x0_gpio_cfg_rbank,
1486 .chip = {
1487 .base = S5P6440_GPR(0),
1488 .ngpio = S5P6440_GPIO_R_NR,
1489 .label = "GPR",
1490 },
1491 },
1492#endif
1493};
1494
1495static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1496#ifdef CONFIG_CPU_S5P6440
1497 {
1498 .base = S5P64X0_GPF_BASE,
1499 .config = &samsung_gpio_cfgs[6],
1500 .chip = {
1501 .base = S5P6440_GPF(0),
1502 .ngpio = S5P6440_GPIO_F_NR,
1503 .label = "GPF",
1504 },
1505 }, {
1506 .base = S5P64X0_GPI_BASE,
1507 .config = &samsung_gpio_cfgs[4],
1508 .chip = {
1509 .base = S5P6440_GPI(0),
1510 .ngpio = S5P6440_GPIO_I_NR,
1511 .label = "GPI",
1512 },
1513 }, {
1514 .base = S5P64X0_GPJ_BASE,
1515 .config = &samsung_gpio_cfgs[4],
1516 .chip = {
1517 .base = S5P6440_GPJ(0),
1518 .ngpio = S5P6440_GPIO_J_NR,
1519 .label = "GPJ",
1520 },
1521 }, {
1522 .base = S5P64X0_GPN_BASE,
1523 .config = &samsung_gpio_cfgs[5],
1524 .chip = {
1525 .base = S5P6440_GPN(0),
1526 .ngpio = S5P6440_GPIO_N_NR,
1527 .label = "GPN",
1528 },
1529 }, {
1530 .base = S5P64X0_GPP_BASE,
1531 .config = &samsung_gpio_cfgs[6],
1532 .chip = {
1533 .base = S5P6440_GPP(0),
1534 .ngpio = S5P6440_GPIO_P_NR,
1535 .label = "GPP",
1536 },
1537 },
1538#endif
1539};
1540
1541/*
1542 * S5P6450 GPIO bank summary:
1543 *
1544 * Bank GPIOs Style SlpCon ExtInt Group
1545 * A 6 4Bit Yes 1
1546 * B 7 4Bit Yes 1
1547 * C 8 4Bit Yes 2
1548 * D 8 4Bit Yes None
1549 * F 2 2Bit Yes None
1550 * G 14 4Bit[2] Yes 5
1551 * H 10 4Bit[2] Yes 6
1552 * I 16 2Bit Yes None
1553 * J 12 2Bit Yes None
1554 * K 5 4Bit Yes None
1555 * N 16 2Bit No IRQ_EINT
1556 * P 11 2Bit Yes 8
1557 * Q 14 2Bit Yes None
1558 * R 15 4Bit[2] Yes None
1559 * S 8 2Bit Yes None
1560 *
1561 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1562 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1563 */
1564
1565static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1566#ifdef CONFIG_CPU_S5P6450
1567 {
1568 .chip = {
1569 .base = S5P6450_GPA(0),
1570 .ngpio = S5P6450_GPIO_A_NR,
1571 .label = "GPA",
1572 },
1573 }, {
1574 .chip = {
1575 .base = S5P6450_GPB(0),
1576 .ngpio = S5P6450_GPIO_B_NR,
1577 .label = "GPB",
1578 },
1579 }, {
1580 .chip = {
1581 .base = S5P6450_GPC(0),
1582 .ngpio = S5P6450_GPIO_C_NR,
1583 .label = "GPC",
1584 },
1585 }, {
1586 .chip = {
1587 .base = S5P6450_GPD(0),
1588 .ngpio = S5P6450_GPIO_D_NR,
1589 .label = "GPD",
1590 },
1591 }, {
1592 .base = S5P6450_GPK_BASE,
1593 .chip = {
1594 .base = S5P6450_GPK(0),
1595 .ngpio = S5P6450_GPIO_K_NR,
1596 .label = "GPK",
1597 },
1598 },
1599#endif
1600};
1601
1602static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1603#ifdef CONFIG_CPU_S5P6450
1604 {
1605 .base = S5P64X0_GPG_BASE + 0x4,
1606 .chip = {
1607 .base = S5P6450_GPG(0),
1608 .ngpio = S5P6450_GPIO_G_NR,
1609 .label = "GPG",
1610 },
1611 }, {
1612 .base = S5P64X0_GPH_BASE + 0x4,
1613 .chip = {
1614 .base = S5P6450_GPH(0),
1615 .ngpio = S5P6450_GPIO_H_NR,
1616 .label = "GPH",
1617 },
1618 },
1619#endif
1620};
1621
1622static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1623#ifdef CONFIG_CPU_S5P6450
1624 {
1625 .base = S5P64X0_GPR_BASE + 0x4,
1626 .config = &s5p64x0_gpio_cfg_rbank,
1627 .chip = {
1628 .base = S5P6450_GPR(0),
1629 .ngpio = S5P6450_GPIO_R_NR,
1630 .label = "GPR",
1631 },
1632 },
1633#endif
1634};
1635
1636static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1637#ifdef CONFIG_CPU_S5P6450
1638 {
1639 .base = S5P64X0_GPF_BASE,
1640 .config = &samsung_gpio_cfgs[6],
1641 .chip = {
1642 .base = S5P6450_GPF(0),
1643 .ngpio = S5P6450_GPIO_F_NR,
1644 .label = "GPF",
1645 },
1646 }, {
1647 .base = S5P64X0_GPI_BASE,
1648 .config = &samsung_gpio_cfgs[4],
1649 .chip = {
1650 .base = S5P6450_GPI(0),
1651 .ngpio = S5P6450_GPIO_I_NR,
1652 .label = "GPI",
1653 },
1654 }, {
1655 .base = S5P64X0_GPJ_BASE,
1656 .config = &samsung_gpio_cfgs[4],
1657 .chip = {
1658 .base = S5P6450_GPJ(0),
1659 .ngpio = S5P6450_GPIO_J_NR,
1660 .label = "GPJ",
1661 },
1662 }, {
1663 .base = S5P64X0_GPN_BASE,
1664 .config = &samsung_gpio_cfgs[5],
1665 .chip = {
1666 .base = S5P6450_GPN(0),
1667 .ngpio = S5P6450_GPIO_N_NR,
1668 .label = "GPN",
1669 },
1670 }, {
1671 .base = S5P64X0_GPP_BASE,
1672 .config = &samsung_gpio_cfgs[6],
1673 .chip = {
1674 .base = S5P6450_GPP(0),
1675 .ngpio = S5P6450_GPIO_P_NR,
1676 .label = "GPP",
1677 },
1678 }, {
1679 .base = S5P6450_GPQ_BASE,
1680 .config = &samsung_gpio_cfgs[5],
1681 .chip = {
1682 .base = S5P6450_GPQ(0),
1683 .ngpio = S5P6450_GPIO_Q_NR,
1684 .label = "GPQ",
1685 },
1686 }, {
1687 .base = S5P6450_GPS_BASE,
1688 .config = &samsung_gpio_cfgs[6],
1689 .chip = {
1690 .base = S5P6450_GPS(0),
1691 .ngpio = S5P6450_GPIO_S_NR,
1692 .label = "GPS",
1693 },
1694 },
1695#endif
1696};
1697
1698/*
1699 * S5PC100 GPIO bank summary:
1700 *
1701 * Bank GPIOs Style INT Type
1702 * A0 8 4Bit GPIO_INT0
1703 * A1 5 4Bit GPIO_INT1
1704 * B 8 4Bit GPIO_INT2
1705 * C 5 4Bit GPIO_INT3
1706 * D 7 4Bit GPIO_INT4
1707 * E0 8 4Bit GPIO_INT5
1708 * E1 6 4Bit GPIO_INT6
1709 * F0 8 4Bit GPIO_INT7
1710 * F1 8 4Bit GPIO_INT8
1711 * F2 8 4Bit GPIO_INT9
1712 * F3 4 4Bit GPIO_INT10
1713 * G0 8 4Bit GPIO_INT11
1714 * G1 3 4Bit GPIO_INT12
1715 * G2 7 4Bit GPIO_INT13
1716 * G3 7 4Bit GPIO_INT14
1717 * H0 8 4Bit WKUP_INT
1718 * H1 8 4Bit WKUP_INT
1719 * H2 8 4Bit WKUP_INT
1720 * H3 8 4Bit WKUP_INT
1721 * I 8 4Bit GPIO_INT15
1722 * J0 8 4Bit GPIO_INT16
1723 * J1 5 4Bit GPIO_INT17
1724 * J2 8 4Bit GPIO_INT18
1725 * J3 8 4Bit GPIO_INT19
1726 * J4 4 4Bit GPIO_INT20
1727 * K0 8 4Bit None
1728 * K1 6 4Bit None
1729 * K2 8 4Bit None
1730 * K3 8 4Bit None
1731 * L0 8 4Bit None
1732 * L1 8 4Bit None
1733 * L2 8 4Bit None
1734 * L3 8 4Bit None
1735 */
1736
1737static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1738#ifdef CONFIG_CPU_S5PC100
1739 {
1740 .chip = {
1741 .base = S5PC100_GPA0(0),
1742 .ngpio = S5PC100_GPIO_A0_NR,
1743 .label = "GPA0",
1744 },
1745 }, {
1746 .chip = {
1747 .base = S5PC100_GPA1(0),
1748 .ngpio = S5PC100_GPIO_A1_NR,
1749 .label = "GPA1",
1750 },
1751 }, {
1752 .chip = {
1753 .base = S5PC100_GPB(0),
1754 .ngpio = S5PC100_GPIO_B_NR,
1755 .label = "GPB",
1756 },
1757 }, {
1758 .chip = {
1759 .base = S5PC100_GPC(0),
1760 .ngpio = S5PC100_GPIO_C_NR,
1761 .label = "GPC",
1762 },
1763 }, {
1764 .chip = {
1765 .base = S5PC100_GPD(0),
1766 .ngpio = S5PC100_GPIO_D_NR,
1767 .label = "GPD",
1768 },
1769 }, {
1770 .chip = {
1771 .base = S5PC100_GPE0(0),
1772 .ngpio = S5PC100_GPIO_E0_NR,
1773 .label = "GPE0",
1774 },
1775 }, {
1776 .chip = {
1777 .base = S5PC100_GPE1(0),
1778 .ngpio = S5PC100_GPIO_E1_NR,
1779 .label = "GPE1",
1780 },
1781 }, {
1782 .chip = {
1783 .base = S5PC100_GPF0(0),
1784 .ngpio = S5PC100_GPIO_F0_NR,
1785 .label = "GPF0",
1786 },
1787 }, {
1788 .chip = {
1789 .base = S5PC100_GPF1(0),
1790 .ngpio = S5PC100_GPIO_F1_NR,
1791 .label = "GPF1",
1792 },
1793 }, {
1794 .chip = {
1795 .base = S5PC100_GPF2(0),
1796 .ngpio = S5PC100_GPIO_F2_NR,
1797 .label = "GPF2",
1798 },
1799 }, {
1800 .chip = {
1801 .base = S5PC100_GPF3(0),
1802 .ngpio = S5PC100_GPIO_F3_NR,
1803 .label = "GPF3",
1804 },
1805 }, {
1806 .chip = {
1807 .base = S5PC100_GPG0(0),
1808 .ngpio = S5PC100_GPIO_G0_NR,
1809 .label = "GPG0",
1810 },
1811 }, {
1812 .chip = {
1813 .base = S5PC100_GPG1(0),
1814 .ngpio = S5PC100_GPIO_G1_NR,
1815 .label = "GPG1",
1816 },
1817 }, {
1818 .chip = {
1819 .base = S5PC100_GPG2(0),
1820 .ngpio = S5PC100_GPIO_G2_NR,
1821 .label = "GPG2",
1822 },
1823 }, {
1824 .chip = {
1825 .base = S5PC100_GPG3(0),
1826 .ngpio = S5PC100_GPIO_G3_NR,
1827 .label = "GPG3",
1828 },
1829 }, {
1830 .chip = {
1831 .base = S5PC100_GPI(0),
1832 .ngpio = S5PC100_GPIO_I_NR,
1833 .label = "GPI",
1834 },
1835 }, {
1836 .chip = {
1837 .base = S5PC100_GPJ0(0),
1838 .ngpio = S5PC100_GPIO_J0_NR,
1839 .label = "GPJ0",
1840 },
1841 }, {
1842 .chip = {
1843 .base = S5PC100_GPJ1(0),
1844 .ngpio = S5PC100_GPIO_J1_NR,
1845 .label = "GPJ1",
1846 },
1847 }, {
1848 .chip = {
1849 .base = S5PC100_GPJ2(0),
1850 .ngpio = S5PC100_GPIO_J2_NR,
1851 .label = "GPJ2",
1852 },
1853 }, {
1854 .chip = {
1855 .base = S5PC100_GPJ3(0),
1856 .ngpio = S5PC100_GPIO_J3_NR,
1857 .label = "GPJ3",
1858 },
1859 }, {
1860 .chip = {
1861 .base = S5PC100_GPJ4(0),
1862 .ngpio = S5PC100_GPIO_J4_NR,
1863 .label = "GPJ4",
1864 },
1865 }, {
1866 .chip = {
1867 .base = S5PC100_GPK0(0),
1868 .ngpio = S5PC100_GPIO_K0_NR,
1869 .label = "GPK0",
1870 },
1871 }, {
1872 .chip = {
1873 .base = S5PC100_GPK1(0),
1874 .ngpio = S5PC100_GPIO_K1_NR,
1875 .label = "GPK1",
1876 },
1877 }, {
1878 .chip = {
1879 .base = S5PC100_GPK2(0),
1880 .ngpio = S5PC100_GPIO_K2_NR,
1881 .label = "GPK2",
1882 },
1883 }, {
1884 .chip = {
1885 .base = S5PC100_GPK3(0),
1886 .ngpio = S5PC100_GPIO_K3_NR,
1887 .label = "GPK3",
1888 },
1889 }, {
1890 .chip = {
1891 .base = S5PC100_GPL0(0),
1892 .ngpio = S5PC100_GPIO_L0_NR,
1893 .label = "GPL0",
1894 },
1895 }, {
1896 .chip = {
1897 .base = S5PC100_GPL1(0),
1898 .ngpio = S5PC100_GPIO_L1_NR,
1899 .label = "GPL1",
1900 },
1901 }, {
1902 .chip = {
1903 .base = S5PC100_GPL2(0),
1904 .ngpio = S5PC100_GPIO_L2_NR,
1905 .label = "GPL2",
1906 },
1907 }, {
1908 .chip = {
1909 .base = S5PC100_GPL3(0),
1910 .ngpio = S5PC100_GPIO_L3_NR,
1911 .label = "GPL3",
1912 },
1913 }, {
1914 .chip = {
1915 .base = S5PC100_GPL4(0),
1916 .ngpio = S5PC100_GPIO_L4_NR,
1917 .label = "GPL4",
1918 },
1919 }, {
1920 .base = (S5P_VA_GPIO + 0xC00),
1921 .irq_base = IRQ_EINT(0),
1922 .chip = {
1923 .base = S5PC100_GPH0(0),
1924 .ngpio = S5PC100_GPIO_H0_NR,
1925 .label = "GPH0",
1926 .to_irq = samsung_gpiolib_to_irq,
1927 },
1928 }, {
1929 .base = (S5P_VA_GPIO + 0xC20),
1930 .irq_base = IRQ_EINT(8),
1931 .chip = {
1932 .base = S5PC100_GPH1(0),
1933 .ngpio = S5PC100_GPIO_H1_NR,
1934 .label = "GPH1",
1935 .to_irq = samsung_gpiolib_to_irq,
1936 },
1937 }, {
1938 .base = (S5P_VA_GPIO + 0xC40),
1939 .irq_base = IRQ_EINT(16),
1940 .chip = {
1941 .base = S5PC100_GPH2(0),
1942 .ngpio = S5PC100_GPIO_H2_NR,
1943 .label = "GPH2",
1944 .to_irq = samsung_gpiolib_to_irq,
1945 },
1946 }, {
1947 .base = (S5P_VA_GPIO + 0xC60),
1948 .irq_base = IRQ_EINT(24),
1949 .chip = {
1950 .base = S5PC100_GPH3(0),
1951 .ngpio = S5PC100_GPIO_H3_NR,
1952 .label = "GPH3",
1953 .to_irq = samsung_gpiolib_to_irq,
1954 },
1955 },
1956#endif
1957};
1958
1959/*
1960 * Followings are the gpio banks in S5PV210/S5PC110
1961 *
1962 * The 'config' member when left to NULL, is initialized to the default
b391f8cf 1963 * structure samsung_gpio_cfgs[3] in the init function below.
1b39d5f2
KK		 1964 *
1965 * The 'base' member is also initialized in the init function below.
1966 * Note: The initialization of 'base' member of samsung_gpio_chip structure
1967 * uses the above macro and depends on the banks being listed in order here.
1968 */
1969
1970static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
1971#ifdef CONFIG_CPU_S5PV210
1972 {
1973 .chip = {
1974 .base = S5PV210_GPA0(0),
1975 .ngpio = S5PV210_GPIO_A0_NR,
1976 .label = "GPA0",
1977 },
1978 }, {
1979 .chip = {
1980 .base = S5PV210_GPA1(0),
1981 .ngpio = S5PV210_GPIO_A1_NR,
1982 .label = "GPA1",
1983 },
1984 }, {
1985 .chip = {
1986 .base = S5PV210_GPB(0),
1987 .ngpio = S5PV210_GPIO_B_NR,
1988 .label = "GPB",
1989 },
1990 }, {
1991 .chip = {
1992 .base = S5PV210_GPC0(0),
1993 .ngpio = S5PV210_GPIO_C0_NR,
1994 .label = "GPC0",
1995 },
1996 }, {
1997 .chip = {
1998 .base = S5PV210_GPC1(0),
1999 .ngpio = S5PV210_GPIO_C1_NR,
2000 .label = "GPC1",
2001 },
2002 }, {
2003 .chip = {
2004 .base = S5PV210_GPD0(0),
2005 .ngpio = S5PV210_GPIO_D0_NR,
2006 .label = "GPD0",
2007 },
2008 }, {
2009 .chip = {
2010 .base = S5PV210_GPD1(0),
2011 .ngpio = S5PV210_GPIO_D1_NR,
2012 .label = "GPD1",
2013 },
2014 }, {
2015 .chip = {
2016 .base = S5PV210_GPE0(0),
2017 .ngpio = S5PV210_GPIO_E0_NR,
2018 .label = "GPE0",
2019 },
2020 }, {
2021 .chip = {
2022 .base = S5PV210_GPE1(0),
2023 .ngpio = S5PV210_GPIO_E1_NR,
2024 .label = "GPE1",
2025 },
2026 }, {
2027 .chip = {
2028 .base = S5PV210_GPF0(0),
2029 .ngpio = S5PV210_GPIO_F0_NR,
2030 .label = "GPF0",
2031 },
2032 }, {
2033 .chip = {
2034 .base = S5PV210_GPF1(0),
2035 .ngpio = S5PV210_GPIO_F1_NR,
2036 .label = "GPF1",
2037 },
2038 }, {
2039 .chip = {
2040 .base = S5PV210_GPF2(0),
2041 .ngpio = S5PV210_GPIO_F2_NR,
2042 .label = "GPF2",
2043 },
2044 }, {
2045 .chip = {
2046 .base = S5PV210_GPF3(0),
2047 .ngpio = S5PV210_GPIO_F3_NR,
2048 .label = "GPF3",
2049 },
2050 }, {
2051 .chip = {
2052 .base = S5PV210_GPG0(0),
2053 .ngpio = S5PV210_GPIO_G0_NR,
2054 .label = "GPG0",
2055 },
2056 }, {
2057 .chip = {
2058 .base = S5PV210_GPG1(0),
2059 .ngpio = S5PV210_GPIO_G1_NR,
2060 .label = "GPG1",
2061 },
2062 }, {
2063 .chip = {
2064 .base = S5PV210_GPG2(0),
2065 .ngpio = S5PV210_GPIO_G2_NR,
2066 .label = "GPG2",
2067 },
2068 }, {
2069 .chip = {
2070 .base = S5PV210_GPG3(0),
2071 .ngpio = S5PV210_GPIO_G3_NR,
2072 .label = "GPG3",
2073 },
2074 }, {
2075 .chip = {
2076 .base = S5PV210_GPI(0),
2077 .ngpio = S5PV210_GPIO_I_NR,
2078 .label = "GPI",
2079 },
2080 }, {
2081 .chip = {
2082 .base = S5PV210_GPJ0(0),
2083 .ngpio = S5PV210_GPIO_J0_NR,
2084 .label = "GPJ0",
2085 },
2086 }, {
2087 .chip = {
2088 .base = S5PV210_GPJ1(0),
2089 .ngpio = S5PV210_GPIO_J1_NR,
2090 .label = "GPJ1",
2091 },
2092 }, {
2093 .chip = {
2094 .base = S5PV210_GPJ2(0),
2095 .ngpio = S5PV210_GPIO_J2_NR,
2096 .label = "GPJ2",
2097 },
2098 }, {
2099 .chip = {
2100 .base = S5PV210_GPJ3(0),
2101 .ngpio = S5PV210_GPIO_J3_NR,
2102 .label = "GPJ3",
2103 },
2104 }, {
2105 .chip = {
2106 .base = S5PV210_GPJ4(0),
2107 .ngpio = S5PV210_GPIO_J4_NR,
2108 .label = "GPJ4",
2109 },
2110 }, {
2111 .chip = {
2112 .base = S5PV210_MP01(0),
2113 .ngpio = S5PV210_GPIO_MP01_NR,
2114 .label = "MP01",
2115 },
2116 }, {
2117 .chip = {
2118 .base = S5PV210_MP02(0),
2119 .ngpio = S5PV210_GPIO_MP02_NR,
2120 .label = "MP02",
2121 },
2122 }, {
2123 .chip = {
2124 .base = S5PV210_MP03(0),
2125 .ngpio = S5PV210_GPIO_MP03_NR,
2126 .label = "MP03",
2127 },
2128 }, {
2129 .chip = {
2130 .base = S5PV210_MP04(0),
2131 .ngpio = S5PV210_GPIO_MP04_NR,
2132 .label = "MP04",
2133 },
2134 }, {
2135 .chip = {
2136 .base = S5PV210_MP05(0),
2137 .ngpio = S5PV210_GPIO_MP05_NR,
2138 .label = "MP05",
2139 },
2140 }, {
2141 .base = (S5P_VA_GPIO + 0xC00),
2142 .irq_base = IRQ_EINT(0),
2143 .chip = {
2144 .base = S5PV210_GPH0(0),
2145 .ngpio = S5PV210_GPIO_H0_NR,
2146 .label = "GPH0",
2147 .to_irq = samsung_gpiolib_to_irq,
2148 },
2149 }, {
2150 .base = (S5P_VA_GPIO + 0xC20),
2151 .irq_base = IRQ_EINT(8),
2152 .chip = {
2153 .base = S5PV210_GPH1(0),
2154 .ngpio = S5PV210_GPIO_H1_NR,
2155 .label = "GPH1",
2156 .to_irq = samsung_gpiolib_to_irq,
2157 },
2158 }, {
2159 .base = (S5P_VA_GPIO + 0xC40),
2160 .irq_base = IRQ_EINT(16),
2161 .chip = {
2162 .base = S5PV210_GPH2(0),
2163 .ngpio = S5PV210_GPIO_H2_NR,
2164 .label = "GPH2",
2165 .to_irq = samsung_gpiolib_to_irq,
2166 },
2167 }, {
2168 .base = (S5P_VA_GPIO + 0xC60),
2169 .irq_base = IRQ_EINT(24),
2170 .chip = {
2171 .base = S5PV210_GPH3(0),
2172 .ngpio = S5PV210_GPIO_H3_NR,
2173 .label = "GPH3",
2174 .to_irq = samsung_gpiolib_to_irq,
2175 },
2176 },
2177#endif
2178};
2179
2180/*
a9696d84 2181 * Followings are the gpio banks in EXYNOS SoCs
1b39d5f2
KK		 2182 *
2183 * The 'config' member when left to NULL, is initialized to the default
a9696d84 2184 * structure exynos_gpio_cfg in the init function below.
1b39d5f2
KK		 2185 *
2186 * The 'base' member is also initialized in the init function below.
2187 * Note: The initialization of 'base' member of samsung_gpio_chip structure
2188 * uses the above macro and depends on the banks being listed in order here.
2189 */
2190
1b39d5f2 2191#ifdef CONFIG_ARCH_EXYNOS4
2760f7ad 2192static struct samsung_gpio_chip exynos4_gpios_1[] = {
1b39d5f2
KK		 2193 {
2194 .chip = {
2195 .base = EXYNOS4_GPA0(0),
2196 .ngpio = EXYNOS4_GPIO_A0_NR,
2197 .label = "GPA0",
2198 },
2199 }, {
2200 .chip = {
2201 .base = EXYNOS4_GPA1(0),
2202 .ngpio = EXYNOS4_GPIO_A1_NR,
2203 .label = "GPA1",
2204 },
2205 }, {
2206 .chip = {
2207 .base = EXYNOS4_GPB(0),
2208 .ngpio = EXYNOS4_GPIO_B_NR,
2209 .label = "GPB",
2210 },
2211 }, {
2212 .chip = {
2213 .base = EXYNOS4_GPC0(0),
2214 .ngpio = EXYNOS4_GPIO_C0_NR,
2215 .label = "GPC0",
2216 },
2217 }, {
2218 .chip = {
2219 .base = EXYNOS4_GPC1(0),
2220 .ngpio = EXYNOS4_GPIO_C1_NR,
2221 .label = "GPC1",
2222 },
2223 }, {
2224 .chip = {
2225 .base = EXYNOS4_GPD0(0),
2226 .ngpio = EXYNOS4_GPIO_D0_NR,
2227 .label = "GPD0",
2228 },
2229 }, {
2230 .chip = {
2231 .base = EXYNOS4_GPD1(0),
2232 .ngpio = EXYNOS4_GPIO_D1_NR,
2233 .label = "GPD1",
2234 },
2235 }, {
2236 .chip = {
2237 .base = EXYNOS4_GPE0(0),
2238 .ngpio = EXYNOS4_GPIO_E0_NR,
2239 .label = "GPE0",
2240 },
2241 }, {
2242 .chip = {
2243 .base = EXYNOS4_GPE1(0),
2244 .ngpio = EXYNOS4_GPIO_E1_NR,
2245 .label = "GPE1",
2246 },
2247 }, {
2248 .chip = {
2249 .base = EXYNOS4_GPE2(0),
2250 .ngpio = EXYNOS4_GPIO_E2_NR,
2251 .label = "GPE2",
2252 },
2253 }, {
2254 .chip = {
2255 .base = EXYNOS4_GPE3(0),
2256 .ngpio = EXYNOS4_GPIO_E3_NR,
2257 .label = "GPE3",
2258 },
2259 }, {
2260 .chip = {
2261 .base = EXYNOS4_GPE4(0),
2262 .ngpio = EXYNOS4_GPIO_E4_NR,
2263 .label = "GPE4",
2264 },
2265 }, {
2266 .chip = {
2267 .base = EXYNOS4_GPF0(0),
2268 .ngpio = EXYNOS4_GPIO_F0_NR,
2269 .label = "GPF0",
2270 },
2271 }, {
2272 .chip = {
2273 .base = EXYNOS4_GPF1(0),
2274 .ngpio = EXYNOS4_GPIO_F1_NR,
2275 .label = "GPF1",
2276 },
2277 }, {
2278 .chip = {
2279 .base = EXYNOS4_GPF2(0),
2280 .ngpio = EXYNOS4_GPIO_F2_NR,
2281 .label = "GPF2",
2282 },
2283 }, {
2284 .chip = {
2285 .base = EXYNOS4_GPF3(0),
2286 .ngpio = EXYNOS4_GPIO_F3_NR,
2287 .label = "GPF3",
2288 },
2289 },
1b39d5f2 2290};
2760f7ad 2291#endif
1b39d5f2 2292
1b39d5f2 2293#ifdef CONFIG_ARCH_EXYNOS4
2760f7ad 2294static struct samsung_gpio_chip exynos4_gpios_2[] = {
1b39d5f2
KK		 2295 {
2296 .chip = {
2297 .base = EXYNOS4_GPJ0(0),
2298 .ngpio = EXYNOS4_GPIO_J0_NR,
2299 .label = "GPJ0",
2300 },
2301 }, {
2302 .chip = {
2303 .base = EXYNOS4_GPJ1(0),
2304 .ngpio = EXYNOS4_GPIO_J1_NR,
2305 .label = "GPJ1",
2306 },
2307 }, {
2308 .chip = {
2309 .base = EXYNOS4_GPK0(0),
2310 .ngpio = EXYNOS4_GPIO_K0_NR,
2311 .label = "GPK0",
2312 },
2313 }, {
2314 .chip = {
2315 .base = EXYNOS4_GPK1(0),
2316 .ngpio = EXYNOS4_GPIO_K1_NR,
2317 .label = "GPK1",
2318 },
2319 }, {
2320 .chip = {
2321 .base = EXYNOS4_GPK2(0),
2322 .ngpio = EXYNOS4_GPIO_K2_NR,
2323 .label = "GPK2",
2324 },
2325 }, {
2326 .chip = {
2327 .base = EXYNOS4_GPK3(0),
2328 .ngpio = EXYNOS4_GPIO_K3_NR,
2329 .label = "GPK3",
2330 },
2331 }, {
2332 .chip = {
2333 .base = EXYNOS4_GPL0(0),
2334 .ngpio = EXYNOS4_GPIO_L0_NR,
2335 .label = "GPL0",
2336 },
2337 }, {
2338 .chip = {
2339 .base = EXYNOS4_GPL1(0),
2340 .ngpio = EXYNOS4_GPIO_L1_NR,
2341 .label = "GPL1",
2342 },
2343 }, {
2344 .chip = {
2345 .base = EXYNOS4_GPL2(0),
2346 .ngpio = EXYNOS4_GPIO_L2_NR,
2347 .label = "GPL2",
2348 },
2349 }, {
b82cee24 2350 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2351 .chip = {
2352 .base = EXYNOS4_GPY0(0),
2353 .ngpio = EXYNOS4_GPIO_Y0_NR,
2354 .label = "GPY0",
2355 },
2356 }, {
b82cee24 2357 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2358 .chip = {
2359 .base = EXYNOS4_GPY1(0),
2360 .ngpio = EXYNOS4_GPIO_Y1_NR,
2361 .label = "GPY1",
2362 },
2363 }, {
b82cee24 2364 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2365 .chip = {
2366 .base = EXYNOS4_GPY2(0),
2367 .ngpio = EXYNOS4_GPIO_Y2_NR,
2368 .label = "GPY2",
2369 },
2370 }, {
b82cee24 2371 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2372 .chip = {
2373 .base = EXYNOS4_GPY3(0),
2374 .ngpio = EXYNOS4_GPIO_Y3_NR,
2375 .label = "GPY3",
2376 },
2377 }, {
b82cee24 2378 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2379 .chip = {
2380 .base = EXYNOS4_GPY4(0),
2381 .ngpio = EXYNOS4_GPIO_Y4_NR,
2382 .label = "GPY4",
2383 },
2384 }, {
b82cee24 2385 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2386 .chip = {
2387 .base = EXYNOS4_GPY5(0),
2388 .ngpio = EXYNOS4_GPIO_Y5_NR,
2389 .label = "GPY5",
2390 },
2391 }, {
b82cee24 2392 .config = &samsung_gpio_cfgs[8],
1b39d5f2
KK		 2393 .chip = {
2394 .base = EXYNOS4_GPY6(0),
2395 .ngpio = EXYNOS4_GPIO_Y6_NR,
2396 .label = "GPY6",
2397 },
2398 }, {
b82cee24 2399 .config = &samsung_gpio_cfgs[9],
1b39d5f2
KK		 2400 .irq_base = IRQ_EINT(0),
2401 .chip = {
2402 .base = EXYNOS4_GPX0(0),
2403 .ngpio = EXYNOS4_GPIO_X0_NR,
2404 .label = "GPX0",
2405 .to_irq = samsung_gpiolib_to_irq,
2406 },
2407 }, {
b82cee24 2408 .config = &samsung_gpio_cfgs[9],
1b39d5f2
KK		 2409 .irq_base = IRQ_EINT(8),
2410 .chip = {
2411 .base = EXYNOS4_GPX1(0),
2412 .ngpio = EXYNOS4_GPIO_X1_NR,
2413 .label = "GPX1",
2414 .to_irq = samsung_gpiolib_to_irq,
2415 },
2416 }, {
b82cee24 2417 .config = &samsung_gpio_cfgs[9],
1b39d5f2
KK		 2418 .irq_base = IRQ_EINT(16),
2419 .chip = {
2420 .base = EXYNOS4_GPX2(0),
2421 .ngpio = EXYNOS4_GPIO_X2_NR,
2422 .label = "GPX2",
2423 .to_irq = samsung_gpiolib_to_irq,
2424 },
2425 }, {
b82cee24 2426 .config = &samsung_gpio_cfgs[9],
1b39d5f2
KK		 2427 .irq_base = IRQ_EINT(24),
2428 .chip = {
2429 .base = EXYNOS4_GPX3(0),
2430 .ngpio = EXYNOS4_GPIO_X3_NR,
2431 .label = "GPX3",
2432 .to_irq = samsung_gpiolib_to_irq,
2433 },
2434 },
1b39d5f2 2435};
2760f7ad 2436#endif
1b39d5f2 2437
1b39d5f2 2438#ifdef CONFIG_ARCH_EXYNOS4
2760f7ad 2439static struct samsung_gpio_chip exynos4_gpios_3[] = {
1b39d5f2
KK		 2440 {
2441 .chip = {
2442 .base = EXYNOS4_GPZ(0),
2443 .ngpio = EXYNOS4_GPIO_Z_NR,
2444 .label = "GPZ",
2445 },
2446 },
1b39d5f2 2447};
2760f7ad 2448#endif
1b39d5f2 2449
dcb9c349 2450#ifdef CONFIG_SOC_EXYNOS5250
9a5c7d6e 2451static struct samsung_gpio_chip exynos5_gpios_1[] = {
a9696d84
SP		 2452 {
2453 .chip = {
2454 .base = EXYNOS5_GPA0(0),
2455 .ngpio = EXYNOS5_GPIO_A0_NR,
2456 .label = "GPA0",
2457 },
2458 }, {
2459 .chip = {
2460 .base = EXYNOS5_GPA1(0),
2461 .ngpio = EXYNOS5_GPIO_A1_NR,
2462 .label = "GPA1",
2463 },
2464 }, {
2465 .chip = {
2466 .base = EXYNOS5_GPA2(0),
2467 .ngpio = EXYNOS5_GPIO_A2_NR,
2468 .label = "GPA2",
2469 },
2470 }, {
2471 .chip = {
2472 .base = EXYNOS5_GPB0(0),
2473 .ngpio = EXYNOS5_GPIO_B0_NR,
2474 .label = "GPB0",
2475 },
2476 }, {
2477 .chip = {
2478 .base = EXYNOS5_GPB1(0),
2479 .ngpio = EXYNOS5_GPIO_B1_NR,
2480 .label = "GPB1",
2481 },
2482 }, {
2483 .chip = {
2484 .base = EXYNOS5_GPB2(0),
2485 .ngpio = EXYNOS5_GPIO_B2_NR,
2486 .label = "GPB2",
2487 },
2488 }, {
2489 .chip = {
2490 .base = EXYNOS5_GPB3(0),
2491 .ngpio = EXYNOS5_GPIO_B3_NR,
2492 .label = "GPB3",
2493 },
2494 }, {
2495 .chip = {
2496 .base = EXYNOS5_GPC0(0),
2497 .ngpio = EXYNOS5_GPIO_C0_NR,
2498 .label = "GPC0",
2499 },
2500 }, {
2501 .chip = {
2502 .base = EXYNOS5_GPC1(0),
2503 .ngpio = EXYNOS5_GPIO_C1_NR,
2504 .label = "GPC1",
2505 },
2506 }, {
2507 .chip = {
2508 .base = EXYNOS5_GPC2(0),
2509 .ngpio = EXYNOS5_GPIO_C2_NR,
2510 .label = "GPC2",
2511 },
2512 }, {
2513 .chip = {
2514 .base = EXYNOS5_GPC3(0),
2515 .ngpio = EXYNOS5_GPIO_C3_NR,
2516 .label = "GPC3",
2517 },
2518 }, {
2519 .chip = {
2520 .base = EXYNOS5_GPD0(0),
2521 .ngpio = EXYNOS5_GPIO_D0_NR,
2522 .label = "GPD0",
2523 },
2524 }, {
2525 .chip = {
2526 .base = EXYNOS5_GPD1(0),
2527 .ngpio = EXYNOS5_GPIO_D1_NR,
2528 .label = "GPD1",
2529 },
2530 }, {
2531 .chip = {
2532 .base = EXYNOS5_GPY0(0),
2533 .ngpio = EXYNOS5_GPIO_Y0_NR,
2534 .label = "GPY0",
2535 },
2536 }, {
2537 .chip = {
2538 .base = EXYNOS5_GPY1(0),
2539 .ngpio = EXYNOS5_GPIO_Y1_NR,
2540 .label = "GPY1",
2541 },
2542 }, {
2543 .chip = {
2544 .base = EXYNOS5_GPY2(0),
2545 .ngpio = EXYNOS5_GPIO_Y2_NR,
2546 .label = "GPY2",
2547 },
2548 }, {
2549 .chip = {
2550 .base = EXYNOS5_GPY3(0),
2551 .ngpio = EXYNOS5_GPIO_Y3_NR,
2552 .label = "GPY3",
2553 },
2554 }, {
2555 .chip = {
2556 .base = EXYNOS5_GPY4(0),
2557 .ngpio = EXYNOS5_GPIO_Y4_NR,
2558 .label = "GPY4",
2559 },
2560 }, {
2561 .chip = {
2562 .base = EXYNOS5_GPY5(0),
2563 .ngpio = EXYNOS5_GPIO_Y5_NR,
2564 .label = "GPY5",
2565 },
2566 }, {
2567 .chip = {
2568 .base = EXYNOS5_GPY6(0),
2569 .ngpio = EXYNOS5_GPIO_Y6_NR,
2570 .label = "GPY6",
2571 },
f7093f3e
SP		 2572 }, {
2573 .chip = {
2574 .base = EXYNOS5_GPC4(0),
2575 .ngpio = EXYNOS5_GPIO_C4_NR,
2576 .label = "GPC4",
2577 },
a9696d84
SP		 2578 }, {
2579 .config = &samsung_gpio_cfgs[9],
2580 .irq_base = IRQ_EINT(0),
2581 .chip = {
2582 .base = EXYNOS5_GPX0(0),
2583 .ngpio = EXYNOS5_GPIO_X0_NR,
2584 .label = "GPX0",
2585 .to_irq = samsung_gpiolib_to_irq,
2586 },
2587 }, {
2588 .config = &samsung_gpio_cfgs[9],
2589 .irq_base = IRQ_EINT(8),
2590 .chip = {
2591 .base = EXYNOS5_GPX1(0),
2592 .ngpio = EXYNOS5_GPIO_X1_NR,
2593 .label = "GPX1",
2594 .to_irq = samsung_gpiolib_to_irq,
2595 },
2596 }, {
2597 .config = &samsung_gpio_cfgs[9],
2598 .irq_base = IRQ_EINT(16),
2599 .chip = {
2600 .base = EXYNOS5_GPX2(0),
2601 .ngpio = EXYNOS5_GPIO_X2_NR,
2602 .label = "GPX2",
2603 .to_irq = samsung_gpiolib_to_irq,
2604 },
2605 }, {
2606 .config = &samsung_gpio_cfgs[9],
2607 .irq_base = IRQ_EINT(24),
2608 .chip = {
2609 .base = EXYNOS5_GPX3(0),
2610 .ngpio = EXYNOS5_GPIO_X3_NR,
2611 .label = "GPX3",
2612 .to_irq = samsung_gpiolib_to_irq,
2613 },
2614 },
a9696d84 2615};
9a5c7d6e 2616#endif
a9696d84 2617
dcb9c349 2618#ifdef CONFIG_SOC_EXYNOS5250
9a5c7d6e 2619static struct samsung_gpio_chip exynos5_gpios_2[] = {
a9696d84
SP		 2620 {
2621 .chip = {
2622 .base = EXYNOS5_GPE0(0),
2623 .ngpio = EXYNOS5_GPIO_E0_NR,
2624 .label = "GPE0",
2625 },
2626 }, {
2627 .chip = {
2628 .base = EXYNOS5_GPE1(0),
2629 .ngpio = EXYNOS5_GPIO_E1_NR,
2630 .label = "GPE1",
2631 },
2632 }, {
2633 .chip = {
2634 .base = EXYNOS5_GPF0(0),
2635 .ngpio = EXYNOS5_GPIO_F0_NR,
2636 .label = "GPF0",
2637 },
2638 }, {
2639 .chip = {
2640 .base = EXYNOS5_GPF1(0),
2641 .ngpio = EXYNOS5_GPIO_F1_NR,
2642 .label = "GPF1",
2643 },
2644 }, {
2645 .chip = {
2646 .base = EXYNOS5_GPG0(0),
2647 .ngpio = EXYNOS5_GPIO_G0_NR,
2648 .label = "GPG0",
2649 },
2650 }, {
2651 .chip = {
2652 .base = EXYNOS5_GPG1(0),
2653 .ngpio = EXYNOS5_GPIO_G1_NR,
2654 .label = "GPG1",
2655 },
2656 }, {
2657 .chip = {
2658 .base = EXYNOS5_GPG2(0),
2659 .ngpio = EXYNOS5_GPIO_G2_NR,
2660 .label = "GPG2",
2661 },
2662 }, {
2663 .chip = {
2664 .base = EXYNOS5_GPH0(0),
2665 .ngpio = EXYNOS5_GPIO_H0_NR,
2666 .label = "GPH0",
2667 },
2668 }, {
2669 .chip = {
2670 .base = EXYNOS5_GPH1(0),
2671 .ngpio = EXYNOS5_GPIO_H1_NR,
2672 .label = "GPH1",
2673
2674 },
2675 },
a9696d84 2676};
9a5c7d6e 2677#endif
a9696d84 2678
dcb9c349 2679#ifdef CONFIG_SOC_EXYNOS5250
9a5c7d6e 2680static struct samsung_gpio_chip exynos5_gpios_3[] = {
a9696d84
SP		 2681 {
2682 .chip = {
2683 .base = EXYNOS5_GPV0(0),
2684 .ngpio = EXYNOS5_GPIO_V0_NR,
2685 .label = "GPV0",
2686 },
2687 }, {
2688 .chip = {
2689 .base = EXYNOS5_GPV1(0),
2690 .ngpio = EXYNOS5_GPIO_V1_NR,
2691 .label = "GPV1",
2692 },
2693 }, {
2694 .chip = {
2695 .base = EXYNOS5_GPV2(0),
2696 .ngpio = EXYNOS5_GPIO_V2_NR,
2697 .label = "GPV2",
2698 },
2699 }, {
2700 .chip = {
2701 .base = EXYNOS5_GPV3(0),
2702 .ngpio = EXYNOS5_GPIO_V3_NR,
2703 .label = "GPV3",
2704 },
2705 }, {
2706 .chip = {
2707 .base = EXYNOS5_GPV4(0),
2708 .ngpio = EXYNOS5_GPIO_V4_NR,
2709 .label = "GPV4",
2710 },
2711 },
a9696d84 2712};
9a5c7d6e 2713#endif
a9696d84 2714
dcb9c349 2715#ifdef CONFIG_SOC_EXYNOS5250
9a5c7d6e 2716static struct samsung_gpio_chip exynos5_gpios_4[] = {
a9696d84
SP		 2717 {
2718 .chip = {
2719 .base = EXYNOS5_GPZ(0),
2720 .ngpio = EXYNOS5_GPIO_Z_NR,
2721 .label = "GPZ",
2722 },
2723 },
a9696d84 2724};
9a5c7d6e 2725#endif
a9696d84
SP		 2726
2727
2728#if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
2729static int exynos_gpio_xlate(struct gpio_chip *gc,
876cf5e7 2730 const struct of_phandle_args *gpiospec, u32 *flags)
659d73ad 2731{
876cf5e7 2732 unsigned int pin;
659d73ad
TA		 2733
2734 if (WARN_ON(gc->of_gpio_n_cells < 4))
2735 return -EINVAL;
2736
876cf5e7 2737 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
659d73ad
TA		 2738 return -EINVAL;
2739
876cf5e7
TA		 2740 if (gpiospec->args[0] > gc->ngpio)
2741 return -EINVAL;
2742
2743 pin = gc->base + gpiospec->args[0];
2744
2745 if (s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(gpiospec->args[1])))
659d73ad 2746 pr_warn("gpio_xlate: failed to set pin function\n");
f447ed8b 2747 if (s3c_gpio_setpull(pin, gpiospec->args[2] & 0xffff))
659d73ad 2748 pr_warn("gpio_xlate: failed to set pin pull up/down\n");
876cf5e7 2749 if (s5p_gpio_set_drvstr(pin, gpiospec->args[3]))
659d73ad
TA		 2750 pr_warn("gpio_xlate: failed to set pin drive strength\n");
2751
f447ed8b
OJ		 2752 if (flags)
2753 *flags = gpiospec->args[2] >> 16;
2754
876cf5e7 2755 return gpiospec->args[0];
659d73ad
TA		 2756}
2757
a9696d84 2758static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
659d73ad
TA		 2759 { .compatible = "samsung,exynos4-gpio", },
2760 {}
2761};
2762
a9696d84
SP		 2763static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2764 u64 base, u64 offset)
659d73ad
TA		 2765{
2766 struct gpio_chip *gc = &chip->chip;
2767 u64 address;
2768
2769 if (!of_have_populated_dt())
2770 return;
2771
2772 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2773 gc->of_node = of_find_matching_node_by_address(NULL,
a9696d84 2774 exynos_gpio_dt_match, address);
659d73ad
TA		 2775 if (!gc->of_node) {
2776 pr_info("gpio: device tree node not found for gpio controller"
2777 " with base address %08llx\n", address);
2778 return;
2779 }
2780 gc->of_gpio_n_cells = 4;
a9696d84 2781 gc->of_xlate = exynos_gpio_xlate;
659d73ad 2782}
a9696d84
SP		 2783#elif defined(CONFIG_ARCH_EXYNOS)
2784static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2785 u64 base, u64 offset)
659d73ad
TA		 2786{
2787 return;
2788}
a9696d84 2789#endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
659d73ad 2790
fd454997
OJ		 2791static __init void exynos4_gpiolib_init(void)
2792{
2793#ifdef CONFIG_CPU_EXYNOS4210
2794 struct samsung_gpio_chip *chip;
2795 int i, nr_chips;
2796 void __iomem *gpio_base1, *gpio_base2, *gpio_base3;
2797 int group = 0;
2798 void __iomem *gpx_base;
2799
2800 /* gpio part1 */
2801 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2802 if (gpio_base1 == NULL) {
2803 pr_err("unable to ioremap for gpio_base1\n");
2804 goto err_ioremap1;
2805 }
2806
2807 chip = exynos4_gpios_1;
2808 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2809
2810 for (i = 0; i < nr_chips; i++, chip++) {
2811 if (!chip->config) {
2812 chip->config = &exynos_gpio_cfg;
2813 chip->group = group++;
2814 }
2815 exynos_gpiolib_attach_ofnode(chip,
2816 EXYNOS4_PA_GPIO1, i * 0x20);
2817 }
2818 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2819 nr_chips, gpio_base1);
2820
2821 /* gpio part2 */
2822 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2823 if (gpio_base2 == NULL) {
2824 pr_err("unable to ioremap for gpio_base2\n");
2825 goto err_ioremap2;
2826 }
2827
2828 /* need to set base address for gpx */
2829 chip = &exynos4_gpios_2[16];
2830 gpx_base = gpio_base2 + 0xC00;
2831 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2832 chip->base = gpx_base;
2833
2834 chip = exynos4_gpios_2;
2835 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2836
2837 for (i = 0; i < nr_chips; i++, chip++) {
2838 if (!chip->config) {
2839 chip->config = &exynos_gpio_cfg;
2840 chip->group = group++;
2841 }
2842 exynos_gpiolib_attach_ofnode(chip,
2843 EXYNOS4_PA_GPIO2, i * 0x20);
2844 }
2845 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2846 nr_chips, gpio_base2);
2847
2848 /* gpio part3 */
2849 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2850 if (gpio_base3 == NULL) {
2851 pr_err("unable to ioremap for gpio_base3\n");
2852 goto err_ioremap3;
2853 }
2854
2855 chip = exynos4_gpios_3;
2856 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2857
2858 for (i = 0; i < nr_chips; i++, chip++) {
2859 if (!chip->config) {
2860 chip->config = &exynos_gpio_cfg;
2861 chip->group = group++;
2862 }
2863 exynos_gpiolib_attach_ofnode(chip,
2864 EXYNOS4_PA_GPIO3, i * 0x20);
2865 }
2866 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2867 nr_chips, gpio_base3);
2868
2869#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2870 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2871 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2872#endif
2873
2874 return;
2875
2876err_ioremap3:
2877 iounmap(gpio_base2);
2878err_ioremap2:
2879 iounmap(gpio_base1);
2880err_ioremap1:
2881 return;
2882#endif /* CONFIG_CPU_EXYNOS4210 */
2883}
2884
2885static __init void exynos5_gpiolib_init(void)
2886{
2887#ifdef CONFIG_SOC_EXYNOS5250
2888 struct samsung_gpio_chip *chip;
2889 int i, nr_chips;
2890 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2891 int group = 0;
2892 void __iomem *gpx_base;
2893
2894 /* gpio part1 */
2895 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2896 if (gpio_base1 == NULL) {
2897 pr_err("unable to ioremap for gpio_base1\n");
2898 goto err_ioremap1;
2899 }
2900
30b84288 2901 /* need to set base address for gpc4 */
f7093f3e 2902 exynos5_gpios_1[20].base = gpio_base1 + 0x2E0;
30b84288 2903
fd454997 2904 /* need to set base address for gpx */
30b84288 2905 chip = &exynos5_gpios_1[21];
fd454997
OJ		 2906 gpx_base = gpio_base1 + 0xC00;
2907 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2908 chip->base = gpx_base;
2909
2910 chip = exynos5_gpios_1;
2911 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2912
2913 for (i = 0; i < nr_chips; i++, chip++) {
2914 if (!chip->config) {
2915 chip->config = &exynos_gpio_cfg;
2916 chip->group = group++;
2917 }
2918 exynos_gpiolib_attach_ofnode(chip,
2919 EXYNOS5_PA_GPIO1, i * 0x20);
2920 }
2921 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2922 nr_chips, gpio_base1);
2923
2924 /* gpio part2 */
2925 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2926 if (gpio_base2 == NULL) {
2927 pr_err("unable to ioremap for gpio_base2\n");
2928 goto err_ioremap2;
2929 }
2930
2931 chip = exynos5_gpios_2;
2932 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2933
2934 for (i = 0; i < nr_chips; i++, chip++) {
2935 if (!chip->config) {
2936 chip->config = &exynos_gpio_cfg;
2937 chip->group = group++;
2938 }
2939 exynos_gpiolib_attach_ofnode(chip,
2940 EXYNOS5_PA_GPIO2, i * 0x20);
2941 }
2942 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2943 nr_chips, gpio_base2);
2944
2945 /* gpio part3 */
2946 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2947 if (gpio_base3 == NULL) {
2948 pr_err("unable to ioremap for gpio_base3\n");
2949 goto err_ioremap3;
2950 }
2951
2952 /* need to set base address for gpv */
2953 exynos5_gpios_3[0].base = gpio_base3;
2954 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2955 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2956 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2957 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2958
2959 chip = exynos5_gpios_3;
2960 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2961
2962 for (i = 0; i < nr_chips; i++, chip++) {
2963 if (!chip->config) {
2964 chip->config = &exynos_gpio_cfg;
2965 chip->group = group++;
2966 }
2967 exynos_gpiolib_attach_ofnode(chip,
2968 EXYNOS5_PA_GPIO3, i * 0x20);
2969 }
2970 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2971 nr_chips, gpio_base3);
2972
2973 /* gpio part4 */
2974 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
2975 if (gpio_base4 == NULL) {
2976 pr_err("unable to ioremap for gpio_base4\n");
2977 goto err_ioremap4;
2978 }
2979
2980 chip = exynos5_gpios_4;
2981 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
2982
2983 for (i = 0; i < nr_chips; i++, chip++) {
2984 if (!chip->config) {
2985 chip->config = &exynos_gpio_cfg;
2986 chip->group = group++;
2987 }
2988 exynos_gpiolib_attach_ofnode(chip,
2989 EXYNOS5_PA_GPIO4, i * 0x20);
2990 }
2991 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
2992 nr_chips, gpio_base4);
2993 return;
2994
2995err_ioremap4:
2996 iounmap(gpio_base3);
2997err_ioremap3:
2998 iounmap(gpio_base2);
2999err_ioremap2:
3000 iounmap(gpio_base1);
3001err_ioremap1:
3002 return;
3003
3004#endif /* CONFIG_SOC_EXYNOS5250 */
3005}
3006
1b39d5f2
KK		 3007/* TODO: cleanup soc_is_* */
3008static __init int samsung_gpiolib_init(void)
3009{
3010 struct samsung_gpio_chip *chip;
3011 int i, nr_chips;
3012 int group = 0;
3013
e4a5da51 3014#if defined(CONFIG_PINCTRL_EXYNOS) || defined(CONFIG_PINCTRL_EXYNOS5440)
ba51bdd3
TF		 3015 /*
3016 * This gpio driver includes support for device tree support and there
3017 * are platforms using it. In order to maintain compatibility with those
3018 * platforms, and to allow non-dt Exynos4210 platforms to use this
3019 * gpiolib support, a check is added to find out if there is a active
3020 * pin-controller driver support available. If it is available, this
3021 * gpiolib support is ignored and the gpiolib support available in
3022 * pin-controller driver is used. This is a temporary check and will go
3023 * away when all of the Exynos4210 platforms have switched to using
3024 * device tree and the pin-ctrl driver.
3025 */
3026 struct device_node *pctrl_np;
3027 static const struct of_device_id exynos_pinctrl_ids[] = {
b533c868
KK		 3028 { .compatible = "samsung,exynos4210-pinctrl", },
3029 { .compatible = "samsung,exynos4x12-pinctrl", },
f6925432 3030 { .compatible = "samsung,exynos5440-pinctrl", },
ba51bdd3
TF		 3031 };
3032 for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
3033 if (pctrl_np && of_device_is_available(pctrl_np))
3034 return -ENODEV;
3035#endif
3036
1b39d5f2
KK		 3037 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
3038
3039 if (soc_is_s3c24xx()) {
3040 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
3041 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
3042 } else if (soc_is_s3c64xx()) {
3043 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
3044 ARRAY_SIZE(s3c64xx_gpios_2bit),
3045 S3C64XX_VA_GPIO + 0xE0, 0x20);
3046 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
3047 ARRAY_SIZE(s3c64xx_gpios_4bit),
3048 S3C64XX_VA_GPIO);
3049 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
3050 ARRAY_SIZE(s3c64xx_gpios_4bit2));
3051 } else if (soc_is_s5p6440()) {
3052 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
3053 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
3054 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
3055 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
3056 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
3057 ARRAY_SIZE(s5p6440_gpios_4bit2));
3058 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
3059 ARRAY_SIZE(s5p6440_gpios_rbank));
3060 } else if (soc_is_s5p6450()) {
3061 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
3062 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
3063 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
3064 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
3065 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
3066 ARRAY_SIZE(s5p6450_gpios_4bit2));
3067 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
3068 ARRAY_SIZE(s5p6450_gpios_rbank));
3069 } else if (soc_is_s5pc100()) {
3070 group = 0;
3071 chip = s5pc100_gpios_4bit;
3072 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
3073
3074 for (i = 0; i < nr_chips; i++, chip++) {
3075 if (!chip->config) {
b391f8cf 3076 chip->config = &samsung_gpio_cfgs[3];
1b39d5f2
KK		 3077 chip->group = group++;
3078 }
3079 }
3080 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
3081#if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
3082 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3083#endif
3084 } else if (soc_is_s5pv210()) {
3085 group = 0;
3086 chip = s5pv210_gpios_4bit;
3087 nr_chips = ARRAY_SIZE(s5pv210_gpios_4bit);
3088
3089 for (i = 0; i < nr_chips; i++, chip++) {
3090 if (!chip->config) {
b391f8cf 3091 chip->config = &samsung_gpio_cfgs[3];
1b39d5f2
KK		 3092 chip->group = group++;
3093 }
3094 }
3095 samsung_gpiolib_add_4bit_chips(s5pv210_gpios_4bit, nr_chips, S5P_VA_GPIO);
3096#if defined(CONFIG_CPU_S5PV210) && defined(CONFIG_S5P_GPIO_INT)
3097 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
3098#endif
3099 } else if (soc_is_exynos4210()) {
fd454997 3100 exynos4_gpiolib_init();
a9696d84 3101 } else if (soc_is_exynos5250()) {
fd454997 3102 exynos5_gpiolib_init();
fbe92fcc
MB		 3103 } else {
3104 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
3105 return -ENODEV;
1b39d5f2
KK		 3106 }
3107
3108 return 0;
3109}
3110core_initcall(samsung_gpiolib_init);
3111
3112int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
3113{
3114 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3115 unsigned long flags;
3116 int offset;
3117 int ret;
3118
3119 if (!chip)
3120 return -EINVAL;
3121
3122 offset = pin - chip->chip.base;
3123
3124 samsung_gpio_lock(chip, flags);
3125 ret = samsung_gpio_do_setcfg(chip, offset, config);
3126 samsung_gpio_unlock(chip, flags);
3127
3128 return ret;
3129}
3130EXPORT_SYMBOL(s3c_gpio_cfgpin);
3131
3132int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
3133 unsigned int cfg)
3134{
3135 int ret;
3136
3137 for (; nr > 0; nr--, start++) {
3138 ret = s3c_gpio_cfgpin(start, cfg);
3139 if (ret != 0)
3140 return ret;
3141 }
3142
3143 return 0;
3144}
3145EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
3146
3147int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
3148 unsigned int cfg, samsung_gpio_pull_t pull)
3149{
3150 int ret;
3151
3152 for (; nr > 0; nr--, start++) {
3153 s3c_gpio_setpull(start, pull);
3154 ret = s3c_gpio_cfgpin(start, cfg);
3155 if (ret != 0)
3156 return ret;
3157 }
3158
3159 return 0;
3160}
3161EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
3162
3163unsigned s3c_gpio_getcfg(unsigned int pin)
3164{
3165 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3166 unsigned long flags;
3167 unsigned ret = 0;
3168 int offset;
3169
3170 if (chip) {
3171 offset = pin - chip->chip.base;
3172
3173 samsung_gpio_lock(chip, flags);
3174 ret = samsung_gpio_do_getcfg(chip, offset);
3175 samsung_gpio_unlock(chip, flags);
3176 }
3177
3178 return ret;
3179}
3180EXPORT_SYMBOL(s3c_gpio_getcfg);
3181
3182int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
3183{
3184 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3185 unsigned long flags;
3186 int offset, ret;
3187
3188 if (!chip)
3189 return -EINVAL;
3190
3191 offset = pin - chip->chip.base;
3192
3193 samsung_gpio_lock(chip, flags);
3194 ret = samsung_gpio_do_setpull(chip, offset, pull);
3195 samsung_gpio_unlock(chip, flags);
3196
3197 return ret;
3198}
3199EXPORT_SYMBOL(s3c_gpio_setpull);
3200
3201samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
3202{
3203 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3204 unsigned long flags;
3205 int offset;
3206 u32 pup = 0;
3207
3208 if (chip) {
3209 offset = pin - chip->chip.base;
3210
3211 samsung_gpio_lock(chip, flags);
3212 pup = samsung_gpio_do_getpull(chip, offset);
3213 samsung_gpio_unlock(chip, flags);
3214 }
3215
3216 return (__force samsung_gpio_pull_t)pup;
3217}
3218EXPORT_SYMBOL(s3c_gpio_getpull);
3219
1b39d5f2
KK		 3220#ifdef CONFIG_S5P_GPIO_DRVSTR
3221s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
3222{
3223 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3224 unsigned int off;
3225 void __iomem *reg;
3226 int shift;
3227 u32 drvstr;
3228
3229 if (!chip)
3230 return -EINVAL;
3231
3232 off = pin - chip->chip.base;
3233 shift = off * 2;
3234 reg = chip->base + 0x0C;
3235
3236 drvstr = __raw_readl(reg);
3237 drvstr = drvstr >> shift;
3238 drvstr &= 0x3;
3239
3240 return (__force s5p_gpio_drvstr_t)drvstr;
3241}
3242EXPORT_SYMBOL(s5p_gpio_get_drvstr);
3243
3244int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
3245{
3246 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3247 unsigned int off;
3248 void __iomem *reg;
3249 int shift;
3250 u32 tmp;
3251
3252 if (!chip)
3253 return -EINVAL;
3254
3255 off = pin - chip->chip.base;
3256 shift = off * 2;
3257 reg = chip->base + 0x0C;
3258
3259 tmp = __raw_readl(reg);
3260 tmp &= ~(0x3 << shift);
3261 tmp |= drvstr << shift;
3262
3263 __raw_writel(tmp, reg);
3264
3265 return 0;
3266}
3267EXPORT_SYMBOL(s5p_gpio_set_drvstr);
3268#endif /* CONFIG_S5P_GPIO_DRVSTR */
3269
3270#ifdef CONFIG_PLAT_S3C24XX
3271unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
3272{
3273 unsigned long flags;
3274 unsigned long misccr;
3275
3276 local_irq_save(flags);
3277 misccr = __raw_readl(S3C24XX_MISCCR);
3278 misccr &= ~clear;
3279 misccr ^= change;
3280 __raw_writel(misccr, S3C24XX_MISCCR);
3281 local_irq_restore(flags);
3282
3283 return misccr;
3284}
3285EXPORT_SYMBOL(s3c2410_modify_misccr);
3286#endif
Linux 6.x block layer and io_uring tree(s)