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pinctrl: ocelot: add clock monitor option for LAN966x
[linux-block.git] / drivers / gpio / gpio-rockchip.c
CommitLineData
936ee267
JX		 1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
5 *
6 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
7 */
8
9#include <linux/bitops.h>
10#include <linux/clk.h>
11#include <linux/device.h>
12#include <linux/err.h>
13#include <linux/gpio/driver.h>
14#include <linux/init.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_device.h>
21#include <linux/of_irq.h>
22#include <linux/regmap.h>
23
24#include "../pinctrl/core.h"
25#include "../pinctrl/pinctrl-rockchip.h"
26
ff96a8c2 27#define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
3bcbd1a8 28#define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
ff96a8c2
JX		 29
30static const struct rockchip_gpio_regs gpio_regs_v1 = {
31 .port_dr = 0x00,
32 .port_ddr = 0x04,
33 .int_en = 0x30,
34 .int_mask = 0x34,
35 .int_type = 0x38,
36 .int_polarity = 0x3c,
37 .int_status = 0x40,
38 .int_rawstatus = 0x44,
39 .debounce = 0x48,
40 .port_eoi = 0x4c,
41 .ext_port = 0x50,
42};
936ee267 43
3bcbd1a8
JX		 44static const struct rockchip_gpio_regs gpio_regs_v2 = {
45 .port_dr = 0x00,
46 .port_ddr = 0x08,
47 .int_en = 0x10,
48 .int_mask = 0x18,
49 .int_type = 0x20,
50 .int_polarity = 0x28,
51 .int_bothedge = 0x30,
52 .int_status = 0x50,
53 .int_rawstatus = 0x58,
54 .debounce = 0x38,
55 .dbclk_div_en = 0x40,
56 .dbclk_div_con = 0x48,
57 .port_eoi = 0x60,
58 .ext_port = 0x70,
59 .version_id = 0x78,
60};
61
62static inline void gpio_writel_v2(u32 val, void __iomem *reg)
63{
64 writel((val & 0xffff) | 0xffff0000, reg);
65 writel((val >> 16) | 0xffff0000, reg + 0x4);
66}
67
68static inline u32 gpio_readl_v2(void __iomem *reg)
69{
70 return readl(reg + 0x4) << 16 | readl(reg);
71}
72
73static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank,
74 u32 value, unsigned int offset)
75{
76 void __iomem *reg = bank->reg_base + offset;
77
78 if (bank->gpio_type == GPIO_TYPE_V2)
79 gpio_writel_v2(value, reg);
80 else
81 writel(value, reg);
82}
83
84static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank,
85 unsigned int offset)
86{
87 void __iomem *reg = bank->reg_base + offset;
88 u32 value;
89
90 if (bank->gpio_type == GPIO_TYPE_V2)
91 value = gpio_readl_v2(reg);
92 else
93 value = readl(reg);
94
95 return value;
96}
97
98static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank,
99 u32 bit, u32 value,
100 unsigned int offset)
101{
102 void __iomem *reg = bank->reg_base + offset;
103 u32 data;
104
105 if (bank->gpio_type == GPIO_TYPE_V2) {
106 if (value)
107 data = BIT(bit % 16) | BIT(bit % 16 + 16);
108 else
109 data = BIT(bit % 16 + 16);
110 writel(data, bit >= 16 ? reg + 0x4 : reg);
111 } else {
112 data = readl(reg);
113 data &= ~BIT(bit);
114 if (value)
115 data |= BIT(bit);
116 writel(data, reg);
117 }
118}
119
120static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank,
121 u32 bit, unsigned int offset)
122{
123 void __iomem *reg = bank->reg_base + offset;
124 u32 data;
125
126 if (bank->gpio_type == GPIO_TYPE_V2) {
127 data = readl(bit >= 16 ? reg + 0x4 : reg);
128 data >>= bit % 16;
129 } else {
130 data = readl(reg);
131 data >>= bit;
132 }
133
134 return data & (0x1);
135}
136
936ee267
JX		 137static int rockchip_gpio_get_direction(struct gpio_chip *chip,
138 unsigned int offset)
139{
140 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
141 u32 data;
142
3bcbd1a8 143 data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr);
b22a4705 144 if (data)
936ee267
JX		 145 return GPIO_LINE_DIRECTION_OUT;
146
147 return GPIO_LINE_DIRECTION_IN;
148}
149
150static int rockchip_gpio_set_direction(struct gpio_chip *chip,
151 unsigned int offset, bool input)
152{
153 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
154 unsigned long flags;
3bcbd1a8 155 u32 data = input ? 0 : 1;
936ee267
JX		 156
157 raw_spin_lock_irqsave(&bank->slock, flags);
3bcbd1a8 158 rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr);
936ee267
JX		 159 raw_spin_unlock_irqrestore(&bank->slock, flags);
160
161 return 0;
162}
163
164static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset,
165 int value)
166{
167 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
936ee267 168 unsigned long flags;
936ee267
JX		 169
170 raw_spin_lock_irqsave(&bank->slock, flags);
3bcbd1a8 171 rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr);
936ee267
JX		 172 raw_spin_unlock_irqrestore(&bank->slock, flags);
173}
174
175static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset)
176{
177 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
178 u32 data;
179
ff96a8c2 180 data = readl(bank->reg_base + bank->gpio_regs->ext_port);
936ee267
JX		 181 data >>= offset;
182 data &= 1;
ff96a8c2 183
936ee267
JX		 184 return data;
185}
186
3bcbd1a8
JX		 187static int rockchip_gpio_set_debounce(struct gpio_chip *gc,
188 unsigned int offset,
189 unsigned int debounce)
936ee267
JX		 190{
191 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
3bcbd1a8
JX		 192 const struct rockchip_gpio_regs *reg = bank->gpio_regs;
193 unsigned long flags, div_reg, freq, max_debounce;
194 bool div_debounce_support;
195 unsigned int cur_div_reg;
196 u64 div;
197
0f562b7d 198 if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) {
3bcbd1a8
JX		 199 div_debounce_support = true;
200 freq = clk_get_rate(bank->db_clk);
201 max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq;
202 if (debounce > max_debounce)
203 return -EINVAL;
204
205 div = debounce * freq;
206 div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1;
207 } else {
208 div_debounce_support = false;
209 }
936ee267
JX		 210
211 raw_spin_lock_irqsave(&bank->slock, flags);
212
3bcbd1a8
JX		 213 /* Only the v1 needs to configure div_en and div_con for dbclk */
214 if (debounce) {
215 if (div_debounce_support) {
216 /* Configure the max debounce from consumers */
217 cur_div_reg = readl(bank->reg_base +
218 reg->dbclk_div_con);
219 if (cur_div_reg < div_reg)
220 writel(div_reg, bank->reg_base +
221 reg->dbclk_div_con);
222 rockchip_gpio_writel_bit(bank, offset, 1,
223 reg->dbclk_div_en);
224 }
225
226 rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce);
227 } else {
228 if (div_debounce_support)
229 rockchip_gpio_writel_bit(bank, offset, 0,
230 reg->dbclk_div_en);
231
232 rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce);
233 }
936ee267
JX		 234
235 raw_spin_unlock_irqrestore(&bank->slock, flags);
3bcbd1a8
JX		 236
237 /* Enable or disable dbclk at last */
238 if (div_debounce_support) {
239 if (debounce)
240 clk_prepare_enable(bank->db_clk);
241 else
242 clk_disable_unprepare(bank->db_clk);
243 }
244
245 return 0;
936ee267
JX		 246}
247
248static int rockchip_gpio_direction_input(struct gpio_chip *gc,
249 unsigned int offset)
250{
251 return rockchip_gpio_set_direction(gc, offset, true);
252}
253
254static int rockchip_gpio_direction_output(struct gpio_chip *gc,
255 unsigned int offset, int value)
256{
257 rockchip_gpio_set(gc, offset, value);
258
259 return rockchip_gpio_set_direction(gc, offset, false);
260}
261
262/*
263 * gpiolib set_config callback function. The setting of the pin
264 * mux function as 'gpio output' will be handled by the pinctrl subsystem
265 * interface.
266 */
267static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
268 unsigned long config)
269{
270 enum pin_config_param param = pinconf_to_config_param(config);
271
272 switch (param) {
273 case PIN_CONFIG_INPUT_DEBOUNCE:
274 rockchip_gpio_set_debounce(gc, offset, true);
275 /*
276 * Rockchip's gpio could only support up to one period
277 * of the debounce clock(pclk), which is far away from
278 * satisftying the requirement, as pclk is usually near
279 * 100MHz shared by all peripherals. So the fact is it
280 * has crippled debounce capability could only be useful
281 * to prevent any spurious glitches from waking up the system
282 * if the gpio is conguired as wakeup interrupt source. Let's
283 * still return -ENOTSUPP as before, to make sure the caller
284 * of gpiod_set_debounce won't change its behaviour.
285 */
286 return -ENOTSUPP;
287 default:
288 return -ENOTSUPP;
289 }
290}
291
292/*
293 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
294 * and a virtual IRQ, if not already present.
295 */
296static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
297{
298 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
299 unsigned int virq;
300
301 if (!bank->domain)
302 return -ENXIO;
303
304 virq = irq_create_mapping(bank->domain, offset);
305
306 return (virq) ? : -ENXIO;
307}
308
309static const struct gpio_chip rockchip_gpiolib_chip = {
310 .request = gpiochip_generic_request,
311 .free = gpiochip_generic_free,
312 .set = rockchip_gpio_set,
313 .get = rockchip_gpio_get,
314 .get_direction = rockchip_gpio_get_direction,
315 .direction_input = rockchip_gpio_direction_input,
316 .direction_output = rockchip_gpio_direction_output,
317 .set_config = rockchip_gpio_set_config,
318 .to_irq = rockchip_gpio_to_irq,
319 .owner = THIS_MODULE,
320};
321
322static void rockchip_irq_demux(struct irq_desc *desc)
323{
324 struct irq_chip *chip = irq_desc_get_chip(desc);
325 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
326 u32 pend;
327
328 dev_dbg(bank->dev, "got irq for bank %s\n", bank->name);
329
330 chained_irq_enter(chip, desc);
331
ff96a8c2 332 pend = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status);
936ee267
JX		 333
334 while (pend) {
335 unsigned int irq, virq;
336
337 irq = __ffs(pend);
338 pend &= ~BIT(irq);
339 virq = irq_find_mapping(bank->domain, irq);
340
341 if (!virq) {
342 dev_err(bank->dev, "unmapped irq %d\n", irq);
343 continue;
344 }
345
346 dev_dbg(bank->dev, "handling irq %d\n", irq);
347
348 /*
349 * Triggering IRQ on both rising and falling edge
350 * needs manual intervention.
351 */
352 if (bank->toggle_edge_mode & BIT(irq)) {
353 u32 data, data_old, polarity;
354 unsigned long flags;
355
ff96a8c2
JX		 356 data = readl_relaxed(bank->reg_base +
357 bank->gpio_regs->ext_port);
936ee267
JX		 358 do {
359 raw_spin_lock_irqsave(&bank->slock, flags);
360
361 polarity = readl_relaxed(bank->reg_base +
ff96a8c2 362 bank->gpio_regs->int_polarity);
936ee267
JX		 363 if (data & BIT(irq))
364 polarity &= ~BIT(irq);
365 else
366 polarity |= BIT(irq);
367 writel(polarity,
ff96a8c2
JX		 368 bank->reg_base +
369 bank->gpio_regs->int_polarity);
936ee267
JX		 370
371 raw_spin_unlock_irqrestore(&bank->slock, flags);
372
373 data_old = data;
374 data = readl_relaxed(bank->reg_base +
ff96a8c2 375 bank->gpio_regs->ext_port);
936ee267
JX		 376 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
377 }
378
379 generic_handle_irq(virq);
380 }
381
382 chained_irq_exit(chip, desc);
383}
384
385static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
386{
387 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
388 struct rockchip_pin_bank *bank = gc->private;
389 u32 mask = BIT(d->hwirq);
390 u32 polarity;
391 u32 level;
392 u32 data;
393 unsigned long flags;
3bcbd1a8 394 int ret = 0;
936ee267
JX		 395
396 raw_spin_lock_irqsave(&bank->slock, flags);
397
3bcbd1a8
JX		 398 rockchip_gpio_writel_bit(bank, d->hwirq, 0,
399 bank->gpio_regs->port_ddr);
936ee267
JX		 400
401 raw_spin_unlock_irqrestore(&bank->slock, flags);
402
403 if (type & IRQ_TYPE_EDGE_BOTH)
404 irq_set_handler_locked(d, handle_edge_irq);
405 else
406 irq_set_handler_locked(d, handle_level_irq);
407
408 raw_spin_lock_irqsave(&bank->slock, flags);
936ee267 409
3bcbd1a8
JX		 410 level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type);
411 polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity);
936ee267 412
7920af5c 413 if (type == IRQ_TYPE_EDGE_BOTH) {
3bcbd1a8 414 if (bank->gpio_type == GPIO_TYPE_V2) {
3bcbd1a8
JX		 415 rockchip_gpio_writel_bit(bank, d->hwirq, 1,
416 bank->gpio_regs->int_bothedge);
417 goto out;
418 } else {
419 bank->toggle_edge_mode |= mask;
420 level |= mask;
421
422 /*
423 * Determine gpio state. If 1 next interrupt should be
424 * falling otherwise rising.
425 */
426 data = readl(bank->reg_base + bank->gpio_regs->ext_port);
427 if (data & mask)
428 polarity &= ~mask;
429 else
430 polarity |= mask;
431 }
7920af5c
SH		 432 } else {
433 if (bank->gpio_type == GPIO_TYPE_V2) {
434 rockchip_gpio_writel_bit(bank, d->hwirq, 0,
435 bank->gpio_regs->int_bothedge);
436 } else {
437 bank->toggle_edge_mode &= ~mask;
438 }
439 switch (type) {
440 case IRQ_TYPE_EDGE_RISING:
441 level |= mask;
442 polarity |= mask;
443 break;
444 case IRQ_TYPE_EDGE_FALLING:
445 level |= mask;
446 polarity &= ~mask;
447 break;
448 case IRQ_TYPE_LEVEL_HIGH:
449 level &= ~mask;
450 polarity |= mask;
451 break;
452 case IRQ_TYPE_LEVEL_LOW:
453 level &= ~mask;
454 polarity &= ~mask;
455 break;
456 default:
457 ret = -EINVAL;
458 goto out;
459 }
936ee267
JX		 460 }
461
3bcbd1a8
JX		 462 rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type);
463 rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity);
464out:
936ee267
JX		 465 raw_spin_unlock_irqrestore(&bank->slock, flags);
466
3bcbd1a8 467 return ret;
936ee267
JX		 468}
469
adc8b4bf
JK		 470static int rockchip_irq_reqres(struct irq_data *d)
471{
472 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
473 struct rockchip_pin_bank *bank = gc->private;
474
475 return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq);
476}
477
478static void rockchip_irq_relres(struct irq_data *d)
479{
480 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
481 struct rockchip_pin_bank *bank = gc->private;
482
483 gpiochip_relres_irq(&bank->gpio_chip, d->hwirq);
484}
485
936ee267
JX		 486static void rockchip_irq_suspend(struct irq_data *d)
487{
488 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
489 struct rockchip_pin_bank *bank = gc->private;
490
ff96a8c2
JX		 491 bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask);
492 irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask);
936ee267
JX		 493}
494
495static void rockchip_irq_resume(struct irq_data *d)
496{
497 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
498 struct rockchip_pin_bank *bank = gc->private;
499
ff96a8c2 500 irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask);
936ee267
JX		 501}
502
503static void rockchip_irq_enable(struct irq_data *d)
504{
936ee267
JX		 505 irq_gc_mask_clr_bit(d);
506}
507
508static void rockchip_irq_disable(struct irq_data *d)
509{
936ee267 510 irq_gc_mask_set_bit(d);
936ee267
JX		 511}
512
513static int rockchip_interrupts_register(struct rockchip_pin_bank *bank)
514{
515 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
516 struct irq_chip_generic *gc;
517 int ret;
518
519 bank->domain = irq_domain_add_linear(bank->of_node, 32,
520 &irq_generic_chip_ops, NULL);
521 if (!bank->domain) {
522 dev_warn(bank->dev, "could not init irq domain for bank %s\n",
523 bank->name);
524 return -EINVAL;
525 }
526
527 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
528 "rockchip_gpio_irq",
529 handle_level_irq,
530 clr, 0, 0);
531 if (ret) {
532 dev_err(bank->dev, "could not alloc generic chips for bank %s\n",
533 bank->name);
534 irq_domain_remove(bank->domain);
535 return -EINVAL;
536 }
537
538 gc = irq_get_domain_generic_chip(bank->domain, 0);
3bcbd1a8
JX		 539 if (bank->gpio_type == GPIO_TYPE_V2) {
540 gc->reg_writel = gpio_writel_v2;
541 gc->reg_readl = gpio_readl_v2;
542 }
543
936ee267
JX		 544 gc->reg_base = bank->reg_base;
545 gc->private = bank;
ff96a8c2
JX		 546 gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask;
547 gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi;
936ee267
JX		 548 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
549 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
550 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
551 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
552 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
553 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
554 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
555 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
556 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
adc8b4bf
JK		 557 gc->chip_types[0].chip.irq_request_resources = rockchip_irq_reqres;
558 gc->chip_types[0].chip.irq_release_resources = rockchip_irq_relres;
936ee267
JX		 559 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
560
561 /*
562 * Linux assumes that all interrupts start out disabled/masked.
563 * Our driver only uses the concept of masked and always keeps
564 * things enabled, so for us that's all masked and all enabled.
565 */
3bcbd1a8
JX		 566 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask);
567 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi);
568 rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en);
936ee267
JX		 569 gc->mask_cache = 0xffffffff;
570
571 irq_set_chained_handler_and_data(bank->irq,
572 rockchip_irq_demux, bank);
573
574 return 0;
575}
576
577static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank)
578{
579 struct gpio_chip *gc;
580 int ret;
581
582 bank->gpio_chip = rockchip_gpiolib_chip;
583
584 gc = &bank->gpio_chip;
585 gc->base = bank->pin_base;
586 gc->ngpio = bank->nr_pins;
587 gc->label = bank->name;
588 gc->parent = bank->dev;
936ee267
JX		 589
590 ret = gpiochip_add_data(gc, bank);
591 if (ret) {
592 dev_err(bank->dev, "failed to add gpiochip %s, %d\n",
593 gc->label, ret);
594 return ret;
595 }
596
597 /*
598 * For DeviceTree-supported systems, the gpio core checks the
599 * pinctrl's device node for the "gpio-ranges" property.
600 * If it is present, it takes care of adding the pin ranges
601 * for the driver. In this case the driver can skip ahead.
602 *
603 * In order to remain compatible with older, existing DeviceTree
604 * files which don't set the "gpio-ranges" property or systems that
605 * utilize ACPI the driver has to call gpiochip_add_pin_range().
606 */
607 if (!of_property_read_bool(bank->of_node, "gpio-ranges")) {
608 struct device_node *pctlnp = of_get_parent(bank->of_node);
609 struct pinctrl_dev *pctldev = NULL;
610
611 if (!pctlnp)
612 return -ENODATA;
613
614 pctldev = of_pinctrl_get(pctlnp);
615 if (!pctldev)
616 return -ENODEV;
617
618 ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0,
619 gc->base, gc->ngpio);
620 if (ret) {
621 dev_err(bank->dev, "Failed to add pin range\n");
622 goto fail;
623 }
624 }
625
626 ret = rockchip_interrupts_register(bank);
627 if (ret) {
628 dev_err(bank->dev, "failed to register interrupt, %d\n", ret);
629 goto fail;
630 }
631
632 return 0;
633
634fail:
635 gpiochip_remove(&bank->gpio_chip);
636
637 return ret;
638}
639
640static int rockchip_get_bank_data(struct rockchip_pin_bank *bank)
641{
642 struct resource res;
3bcbd1a8 643 int id = 0;
936ee267
JX		 644
645 if (of_address_to_resource(bank->of_node, 0, &res)) {
646 dev_err(bank->dev, "cannot find IO resource for bank\n");
647 return -ENOENT;
648 }
649
650 bank->reg_base = devm_ioremap_resource(bank->dev, &res);
651 if (IS_ERR(bank->reg_base))
652 return PTR_ERR(bank->reg_base);
653
654 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
3bcbd1a8
JX		 655 if (!bank->irq)
656 return -EINVAL;
ff96a8c2 657
936ee267 658 bank->clk = of_clk_get(bank->of_node, 0);
3bcbd1a8
JX		 659 if (IS_ERR(bank->clk))
660 return PTR_ERR(bank->clk);
661
662 clk_prepare_enable(bank->clk);
663 id = readl(bank->reg_base + gpio_regs_v2.version_id);
664
665 /* If not gpio v2, that is default to v1. */
666 if (id == GPIO_TYPE_V2) {
667 bank->gpio_regs = &gpio_regs_v2;
668 bank->gpio_type = GPIO_TYPE_V2;
669 bank->db_clk = of_clk_get(bank->of_node, 1);
670 if (IS_ERR(bank->db_clk)) {
671 dev_err(bank->dev, "cannot find debounce clk\n");
672 clk_disable_unprepare(bank->clk);
673 return -EINVAL;
674 }
675 } else {
676 bank->gpio_regs = &gpio_regs_v1;
677 bank->gpio_type = GPIO_TYPE_V1;
678 }
936ee267 679
936ee267
JX		 680 return 0;
681}
682
683static struct rockchip_pin_bank *
684rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id)
685{
686 struct rockchip_pinctrl *info;
687 struct rockchip_pin_bank *bank;
688 int i, found = 0;
689
690 info = pinctrl_dev_get_drvdata(pctldev);
691 bank = info->ctrl->pin_banks;
692 for (i = 0; i < info->ctrl->nr_banks; i++, bank++) {
693 if (bank->bank_num == id) {
694 found = 1;
695 break;
696 }
697 }
698
699 return found ? bank : NULL;
700}
701
702static int rockchip_gpio_probe(struct platform_device *pdev)
703{
704 struct device *dev = &pdev->dev;
705 struct device_node *np = dev->of_node;
706 struct device_node *pctlnp = of_get_parent(np);
707 struct pinctrl_dev *pctldev = NULL;
708 struct rockchip_pin_bank *bank = NULL;
59dd178e 709 struct rockchip_pin_output_deferred *cfg;
936ee267
JX		 710 static int gpio;
711 int id, ret;
712
713 if (!np || !pctlnp)
714 return -ENODEV;
715
716 pctldev = of_pinctrl_get(pctlnp);
717 if (!pctldev)
718 return -EPROBE_DEFER;
719
720 id = of_alias_get_id(np, "gpio");
721 if (id < 0)
722 id = gpio++;
723
724 bank = rockchip_gpio_find_bank(pctldev, id);
725 if (!bank)
726 return -EINVAL;
727
728 bank->dev = dev;
729 bank->of_node = np;
730
731 raw_spin_lock_init(&bank->slock);
732
733 ret = rockchip_get_bank_data(bank);
734 if (ret)
735 return ret;
736
59dd178e
HS		 737 /*
738 * Prevent clashes with a deferred output setting
739 * being added right at this moment.
740 */
741 mutex_lock(&bank->deferred_lock);
742
936ee267
JX		 743 ret = rockchip_gpiolib_register(bank);
744 if (ret) {
745 clk_disable_unprepare(bank->clk);
59dd178e 746 mutex_unlock(&bank->deferred_lock);
936ee267
JX		 747 return ret;
748 }
749
59dd178e
HS		 750 while (!list_empty(&bank->deferred_output)) {
751 cfg = list_first_entry(&bank->deferred_output,
752 struct rockchip_pin_output_deferred, head);
753 list_del(&cfg->head);
754
755 ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg);
756 if (ret)
757 dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin, cfg->arg);
758
759 kfree(cfg);
760 }
761
762 mutex_unlock(&bank->deferred_lock);
763
936ee267
JX		 764 platform_set_drvdata(pdev, bank);
765 dev_info(dev, "probed %pOF\n", np);
766
767 return 0;
768}
769
770static int rockchip_gpio_remove(struct platform_device *pdev)
771{
772 struct rockchip_pin_bank *bank = platform_get_drvdata(pdev);
773
774 clk_disable_unprepare(bank->clk);
775 gpiochip_remove(&bank->gpio_chip);
776
777 return 0;
778}
779
780static const struct of_device_id rockchip_gpio_match[] = {
781 { .compatible = "rockchip,gpio-bank", },
782 { .compatible = "rockchip,rk3188-gpio-bank0" },
783 { },
784};
785
786static struct platform_driver rockchip_gpio_driver = {
787 .probe = rockchip_gpio_probe,
788 .remove = rockchip_gpio_remove,
789 .driver = {
790 .name = "rockchip-gpio",
791 .of_match_table = rockchip_gpio_match,
792 },
793};
794
795static int __init rockchip_gpio_init(void)
796{
797 return platform_driver_register(&rockchip_gpio_driver);
798}
799postcore_initcall(rockchip_gpio_init);
800
801static void __exit rockchip_gpio_exit(void)
802{
803 platform_driver_unregister(&rockchip_gpio_driver);
804}
805module_exit(rockchip_gpio_exit);
806
807MODULE_DESCRIPTION("Rockchip gpio driver");
808MODULE_ALIAS("platform:rockchip-gpio");
809MODULE_LICENSE("GPL v2");
810MODULE_DEVICE_TABLE(of, rockchip_gpio_match);
Linux 6.x block layer and io_uring tree(s)