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936ee267 JX |
1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* | |
3 | * Copyright (c) 2013 MundoReader S.L. | |
4 | * Author: Heiko Stuebner <heiko@sntech.de> | |
5 | * | |
6 | * Copyright (c) 2021 Rockchip Electronics Co. Ltd. | |
7 | */ | |
8 | ||
9 | #include <linux/bitops.h> | |
10 | #include <linux/clk.h> | |
11 | #include <linux/device.h> | |
12 | #include <linux/err.h> | |
13 | #include <linux/gpio/driver.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/io.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/of.h> | |
19 | #include <linux/of_address.h> | |
936ee267 | 20 | #include <linux/of_irq.h> |
8ea8af6c | 21 | #include <linux/pinctrl/consumer.h> |
8ce5ef64 | 22 | #include <linux/pinctrl/pinconf-generic.h> |
e91d0f05 | 23 | #include <linux/platform_device.h> |
936ee267 JX |
24 | #include <linux/regmap.h> |
25 | ||
26 | #include "../pinctrl/core.h" | |
27 | #include "../pinctrl/pinctrl-rockchip.h" | |
28 | ||
ff96a8c2 | 29 | #define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */ |
3bcbd1a8 | 30 | #define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */ |
cc165ba4 | 31 | #define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */ |
ff96a8c2 JX |
32 | |
33 | static const struct rockchip_gpio_regs gpio_regs_v1 = { | |
34 | .port_dr = 0x00, | |
35 | .port_ddr = 0x04, | |
36 | .int_en = 0x30, | |
37 | .int_mask = 0x34, | |
38 | .int_type = 0x38, | |
39 | .int_polarity = 0x3c, | |
40 | .int_status = 0x40, | |
41 | .int_rawstatus = 0x44, | |
42 | .debounce = 0x48, | |
43 | .port_eoi = 0x4c, | |
44 | .ext_port = 0x50, | |
45 | }; | |
936ee267 | 46 | |
3bcbd1a8 JX |
47 | static const struct rockchip_gpio_regs gpio_regs_v2 = { |
48 | .port_dr = 0x00, | |
49 | .port_ddr = 0x08, | |
50 | .int_en = 0x10, | |
51 | .int_mask = 0x18, | |
52 | .int_type = 0x20, | |
53 | .int_polarity = 0x28, | |
54 | .int_bothedge = 0x30, | |
55 | .int_status = 0x50, | |
56 | .int_rawstatus = 0x58, | |
57 | .debounce = 0x38, | |
58 | .dbclk_div_en = 0x40, | |
59 | .dbclk_div_con = 0x48, | |
60 | .port_eoi = 0x60, | |
61 | .ext_port = 0x70, | |
62 | .version_id = 0x78, | |
63 | }; | |
64 | ||
65 | static inline void gpio_writel_v2(u32 val, void __iomem *reg) | |
66 | { | |
67 | writel((val & 0xffff) | 0xffff0000, reg); | |
68 | writel((val >> 16) | 0xffff0000, reg + 0x4); | |
69 | } | |
70 | ||
71 | static inline u32 gpio_readl_v2(void __iomem *reg) | |
72 | { | |
73 | return readl(reg + 0x4) << 16 | readl(reg); | |
74 | } | |
75 | ||
76 | static inline void rockchip_gpio_writel(struct rockchip_pin_bank *bank, | |
77 | u32 value, unsigned int offset) | |
78 | { | |
79 | void __iomem *reg = bank->reg_base + offset; | |
80 | ||
81 | if (bank->gpio_type == GPIO_TYPE_V2) | |
82 | gpio_writel_v2(value, reg); | |
83 | else | |
84 | writel(value, reg); | |
85 | } | |
86 | ||
87 | static inline u32 rockchip_gpio_readl(struct rockchip_pin_bank *bank, | |
88 | unsigned int offset) | |
89 | { | |
90 | void __iomem *reg = bank->reg_base + offset; | |
91 | u32 value; | |
92 | ||
93 | if (bank->gpio_type == GPIO_TYPE_V2) | |
94 | value = gpio_readl_v2(reg); | |
95 | else | |
96 | value = readl(reg); | |
97 | ||
98 | return value; | |
99 | } | |
100 | ||
101 | static inline void rockchip_gpio_writel_bit(struct rockchip_pin_bank *bank, | |
102 | u32 bit, u32 value, | |
103 | unsigned int offset) | |
104 | { | |
105 | void __iomem *reg = bank->reg_base + offset; | |
106 | u32 data; | |
107 | ||
108 | if (bank->gpio_type == GPIO_TYPE_V2) { | |
109 | if (value) | |
110 | data = BIT(bit % 16) | BIT(bit % 16 + 16); | |
111 | else | |
112 | data = BIT(bit % 16 + 16); | |
113 | writel(data, bit >= 16 ? reg + 0x4 : reg); | |
114 | } else { | |
115 | data = readl(reg); | |
116 | data &= ~BIT(bit); | |
117 | if (value) | |
118 | data |= BIT(bit); | |
119 | writel(data, reg); | |
120 | } | |
121 | } | |
122 | ||
123 | static inline u32 rockchip_gpio_readl_bit(struct rockchip_pin_bank *bank, | |
124 | u32 bit, unsigned int offset) | |
125 | { | |
126 | void __iomem *reg = bank->reg_base + offset; | |
127 | u32 data; | |
128 | ||
129 | if (bank->gpio_type == GPIO_TYPE_V2) { | |
130 | data = readl(bit >= 16 ? reg + 0x4 : reg); | |
131 | data >>= bit % 16; | |
132 | } else { | |
133 | data = readl(reg); | |
134 | data >>= bit; | |
135 | } | |
136 | ||
137 | return data & (0x1); | |
138 | } | |
139 | ||
936ee267 JX |
140 | static int rockchip_gpio_get_direction(struct gpio_chip *chip, |
141 | unsigned int offset) | |
142 | { | |
143 | struct rockchip_pin_bank *bank = gpiochip_get_data(chip); | |
144 | u32 data; | |
145 | ||
3bcbd1a8 | 146 | data = rockchip_gpio_readl_bit(bank, offset, bank->gpio_regs->port_ddr); |
b22a4705 | 147 | if (data) |
936ee267 JX |
148 | return GPIO_LINE_DIRECTION_OUT; |
149 | ||
150 | return GPIO_LINE_DIRECTION_IN; | |
151 | } | |
152 | ||
153 | static int rockchip_gpio_set_direction(struct gpio_chip *chip, | |
154 | unsigned int offset, bool input) | |
155 | { | |
156 | struct rockchip_pin_bank *bank = gpiochip_get_data(chip); | |
157 | unsigned long flags; | |
3bcbd1a8 | 158 | u32 data = input ? 0 : 1; |
936ee267 | 159 | |
8ea8af6c QS |
160 | |
161 | if (input) | |
315c46f9 | 162 | pinctrl_gpio_direction_input(chip, offset); |
8ea8af6c | 163 | else |
b679d6c0 | 164 | pinctrl_gpio_direction_output(chip, offset); |
8ea8af6c | 165 | |
936ee267 | 166 | raw_spin_lock_irqsave(&bank->slock, flags); |
3bcbd1a8 | 167 | rockchip_gpio_writel_bit(bank, offset, data, bank->gpio_regs->port_ddr); |
936ee267 JX |
168 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
169 | ||
170 | return 0; | |
171 | } | |
172 | ||
173 | static void rockchip_gpio_set(struct gpio_chip *gc, unsigned int offset, | |
174 | int value) | |
175 | { | |
176 | struct rockchip_pin_bank *bank = gpiochip_get_data(gc); | |
936ee267 | 177 | unsigned long flags; |
936ee267 JX |
178 | |
179 | raw_spin_lock_irqsave(&bank->slock, flags); | |
3bcbd1a8 | 180 | rockchip_gpio_writel_bit(bank, offset, value, bank->gpio_regs->port_dr); |
936ee267 JX |
181 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
182 | } | |
183 | ||
184 | static int rockchip_gpio_get(struct gpio_chip *gc, unsigned int offset) | |
185 | { | |
186 | struct rockchip_pin_bank *bank = gpiochip_get_data(gc); | |
187 | u32 data; | |
188 | ||
ff96a8c2 | 189 | data = readl(bank->reg_base + bank->gpio_regs->ext_port); |
936ee267 JX |
190 | data >>= offset; |
191 | data &= 1; | |
ff96a8c2 | 192 | |
936ee267 JX |
193 | return data; |
194 | } | |
195 | ||
3bcbd1a8 JX |
196 | static int rockchip_gpio_set_debounce(struct gpio_chip *gc, |
197 | unsigned int offset, | |
198 | unsigned int debounce) | |
936ee267 JX |
199 | { |
200 | struct rockchip_pin_bank *bank = gpiochip_get_data(gc); | |
3bcbd1a8 JX |
201 | const struct rockchip_gpio_regs *reg = bank->gpio_regs; |
202 | unsigned long flags, div_reg, freq, max_debounce; | |
203 | bool div_debounce_support; | |
204 | unsigned int cur_div_reg; | |
205 | u64 div; | |
206 | ||
0f562b7d | 207 | if (bank->gpio_type == GPIO_TYPE_V2 && !IS_ERR(bank->db_clk)) { |
3bcbd1a8 JX |
208 | div_debounce_support = true; |
209 | freq = clk_get_rate(bank->db_clk); | |
210 | max_debounce = (GENMASK(23, 0) + 1) * 2 * 1000000 / freq; | |
211 | if (debounce > max_debounce) | |
212 | return -EINVAL; | |
213 | ||
214 | div = debounce * freq; | |
215 | div_reg = DIV_ROUND_CLOSEST_ULL(div, 2 * USEC_PER_SEC) - 1; | |
216 | } else { | |
217 | div_debounce_support = false; | |
218 | } | |
936ee267 JX |
219 | |
220 | raw_spin_lock_irqsave(&bank->slock, flags); | |
221 | ||
3bcbd1a8 JX |
222 | /* Only the v1 needs to configure div_en and div_con for dbclk */ |
223 | if (debounce) { | |
224 | if (div_debounce_support) { | |
225 | /* Configure the max debounce from consumers */ | |
226 | cur_div_reg = readl(bank->reg_base + | |
227 | reg->dbclk_div_con); | |
228 | if (cur_div_reg < div_reg) | |
229 | writel(div_reg, bank->reg_base + | |
230 | reg->dbclk_div_con); | |
231 | rockchip_gpio_writel_bit(bank, offset, 1, | |
232 | reg->dbclk_div_en); | |
233 | } | |
234 | ||
235 | rockchip_gpio_writel_bit(bank, offset, 1, reg->debounce); | |
236 | } else { | |
237 | if (div_debounce_support) | |
238 | rockchip_gpio_writel_bit(bank, offset, 0, | |
239 | reg->dbclk_div_en); | |
240 | ||
241 | rockchip_gpio_writel_bit(bank, offset, 0, reg->debounce); | |
242 | } | |
936ee267 JX |
243 | |
244 | raw_spin_unlock_irqrestore(&bank->slock, flags); | |
3bcbd1a8 JX |
245 | |
246 | /* Enable or disable dbclk at last */ | |
247 | if (div_debounce_support) { | |
248 | if (debounce) | |
249 | clk_prepare_enable(bank->db_clk); | |
250 | else | |
251 | clk_disable_unprepare(bank->db_clk); | |
252 | } | |
253 | ||
254 | return 0; | |
936ee267 JX |
255 | } |
256 | ||
257 | static int rockchip_gpio_direction_input(struct gpio_chip *gc, | |
258 | unsigned int offset) | |
259 | { | |
260 | return rockchip_gpio_set_direction(gc, offset, true); | |
261 | } | |
262 | ||
263 | static int rockchip_gpio_direction_output(struct gpio_chip *gc, | |
264 | unsigned int offset, int value) | |
265 | { | |
266 | rockchip_gpio_set(gc, offset, value); | |
267 | ||
268 | return rockchip_gpio_set_direction(gc, offset, false); | |
269 | } | |
270 | ||
271 | /* | |
272 | * gpiolib set_config callback function. The setting of the pin | |
273 | * mux function as 'gpio output' will be handled by the pinctrl subsystem | |
274 | * interface. | |
275 | */ | |
276 | static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, | |
277 | unsigned long config) | |
278 | { | |
279 | enum pin_config_param param = pinconf_to_config_param(config); | |
280 | ||
281 | switch (param) { | |
282 | case PIN_CONFIG_INPUT_DEBOUNCE: | |
283 | rockchip_gpio_set_debounce(gc, offset, true); | |
284 | /* | |
285 | * Rockchip's gpio could only support up to one period | |
286 | * of the debounce clock(pclk), which is far away from | |
287 | * satisftying the requirement, as pclk is usually near | |
288 | * 100MHz shared by all peripherals. So the fact is it | |
289 | * has crippled debounce capability could only be useful | |
290 | * to prevent any spurious glitches from waking up the system | |
291 | * if the gpio is conguired as wakeup interrupt source. Let's | |
292 | * still return -ENOTSUPP as before, to make sure the caller | |
293 | * of gpiod_set_debounce won't change its behaviour. | |
294 | */ | |
295 | return -ENOTSUPP; | |
296 | default: | |
297 | return -ENOTSUPP; | |
298 | } | |
299 | } | |
300 | ||
301 | /* | |
b0047b90 | 302 | * gpiod_to_irq() callback function. Creates a mapping between a GPIO pin |
936ee267 JX |
303 | * and a virtual IRQ, if not already present. |
304 | */ | |
305 | static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) | |
306 | { | |
307 | struct rockchip_pin_bank *bank = gpiochip_get_data(gc); | |
308 | unsigned int virq; | |
309 | ||
310 | if (!bank->domain) | |
311 | return -ENXIO; | |
312 | ||
313 | virq = irq_create_mapping(bank->domain, offset); | |
314 | ||
315 | return (virq) ? : -ENXIO; | |
316 | } | |
317 | ||
318 | static const struct gpio_chip rockchip_gpiolib_chip = { | |
319 | .request = gpiochip_generic_request, | |
320 | .free = gpiochip_generic_free, | |
321 | .set = rockchip_gpio_set, | |
322 | .get = rockchip_gpio_get, | |
323 | .get_direction = rockchip_gpio_get_direction, | |
324 | .direction_input = rockchip_gpio_direction_input, | |
325 | .direction_output = rockchip_gpio_direction_output, | |
326 | .set_config = rockchip_gpio_set_config, | |
327 | .to_irq = rockchip_gpio_to_irq, | |
328 | .owner = THIS_MODULE, | |
329 | }; | |
330 | ||
331 | static void rockchip_irq_demux(struct irq_desc *desc) | |
332 | { | |
333 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
334 | struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc); | |
b98dbd82 JC |
335 | unsigned long pending; |
336 | unsigned int irq; | |
936ee267 JX |
337 | |
338 | dev_dbg(bank->dev, "got irq for bank %s\n", bank->name); | |
339 | ||
340 | chained_irq_enter(chip, desc); | |
341 | ||
b98dbd82 JC |
342 | pending = readl_relaxed(bank->reg_base + bank->gpio_regs->int_status); |
343 | for_each_set_bit(irq, &pending, 32) { | |
936ee267 JX |
344 | dev_dbg(bank->dev, "handling irq %d\n", irq); |
345 | ||
346 | /* | |
347 | * Triggering IRQ on both rising and falling edge | |
348 | * needs manual intervention. | |
349 | */ | |
350 | if (bank->toggle_edge_mode & BIT(irq)) { | |
351 | u32 data, data_old, polarity; | |
352 | unsigned long flags; | |
353 | ||
ff96a8c2 JX |
354 | data = readl_relaxed(bank->reg_base + |
355 | bank->gpio_regs->ext_port); | |
936ee267 JX |
356 | do { |
357 | raw_spin_lock_irqsave(&bank->slock, flags); | |
358 | ||
359 | polarity = readl_relaxed(bank->reg_base + | |
ff96a8c2 | 360 | bank->gpio_regs->int_polarity); |
936ee267 JX |
361 | if (data & BIT(irq)) |
362 | polarity &= ~BIT(irq); | |
363 | else | |
364 | polarity |= BIT(irq); | |
365 | writel(polarity, | |
ff96a8c2 JX |
366 | bank->reg_base + |
367 | bank->gpio_regs->int_polarity); | |
936ee267 JX |
368 | |
369 | raw_spin_unlock_irqrestore(&bank->slock, flags); | |
370 | ||
371 | data_old = data; | |
372 | data = readl_relaxed(bank->reg_base + | |
ff96a8c2 | 373 | bank->gpio_regs->ext_port); |
936ee267 JX |
374 | } while ((data & BIT(irq)) != (data_old & BIT(irq))); |
375 | } | |
376 | ||
b98dbd82 | 377 | generic_handle_domain_irq(bank->domain, irq); |
936ee267 JX |
378 | } |
379 | ||
380 | chained_irq_exit(chip, desc); | |
381 | } | |
382 | ||
383 | static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) | |
384 | { | |
385 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
386 | struct rockchip_pin_bank *bank = gc->private; | |
387 | u32 mask = BIT(d->hwirq); | |
388 | u32 polarity; | |
389 | u32 level; | |
390 | u32 data; | |
391 | unsigned long flags; | |
3bcbd1a8 | 392 | int ret = 0; |
936ee267 JX |
393 | |
394 | raw_spin_lock_irqsave(&bank->slock, flags); | |
395 | ||
3bcbd1a8 JX |
396 | rockchip_gpio_writel_bit(bank, d->hwirq, 0, |
397 | bank->gpio_regs->port_ddr); | |
936ee267 JX |
398 | |
399 | raw_spin_unlock_irqrestore(&bank->slock, flags); | |
400 | ||
401 | if (type & IRQ_TYPE_EDGE_BOTH) | |
402 | irq_set_handler_locked(d, handle_edge_irq); | |
403 | else | |
404 | irq_set_handler_locked(d, handle_level_irq); | |
405 | ||
406 | raw_spin_lock_irqsave(&bank->slock, flags); | |
936ee267 | 407 | |
3bcbd1a8 JX |
408 | level = rockchip_gpio_readl(bank, bank->gpio_regs->int_type); |
409 | polarity = rockchip_gpio_readl(bank, bank->gpio_regs->int_polarity); | |
936ee267 | 410 | |
7920af5c | 411 | if (type == IRQ_TYPE_EDGE_BOTH) { |
3bcbd1a8 | 412 | if (bank->gpio_type == GPIO_TYPE_V2) { |
3bcbd1a8 JX |
413 | rockchip_gpio_writel_bit(bank, d->hwirq, 1, |
414 | bank->gpio_regs->int_bothedge); | |
415 | goto out; | |
416 | } else { | |
417 | bank->toggle_edge_mode |= mask; | |
b871656a | 418 | level &= ~mask; |
3bcbd1a8 JX |
419 | |
420 | /* | |
421 | * Determine gpio state. If 1 next interrupt should be | |
b871656a | 422 | * low otherwise high. |
3bcbd1a8 JX |
423 | */ |
424 | data = readl(bank->reg_base + bank->gpio_regs->ext_port); | |
425 | if (data & mask) | |
426 | polarity &= ~mask; | |
427 | else | |
428 | polarity |= mask; | |
429 | } | |
7920af5c SH |
430 | } else { |
431 | if (bank->gpio_type == GPIO_TYPE_V2) { | |
432 | rockchip_gpio_writel_bit(bank, d->hwirq, 0, | |
433 | bank->gpio_regs->int_bothedge); | |
434 | } else { | |
435 | bank->toggle_edge_mode &= ~mask; | |
436 | } | |
437 | switch (type) { | |
438 | case IRQ_TYPE_EDGE_RISING: | |
439 | level |= mask; | |
440 | polarity |= mask; | |
441 | break; | |
442 | case IRQ_TYPE_EDGE_FALLING: | |
443 | level |= mask; | |
444 | polarity &= ~mask; | |
445 | break; | |
446 | case IRQ_TYPE_LEVEL_HIGH: | |
447 | level &= ~mask; | |
448 | polarity |= mask; | |
449 | break; | |
450 | case IRQ_TYPE_LEVEL_LOW: | |
451 | level &= ~mask; | |
452 | polarity &= ~mask; | |
453 | break; | |
454 | default: | |
455 | ret = -EINVAL; | |
456 | goto out; | |
457 | } | |
936ee267 JX |
458 | } |
459 | ||
3bcbd1a8 JX |
460 | rockchip_gpio_writel(bank, level, bank->gpio_regs->int_type); |
461 | rockchip_gpio_writel(bank, polarity, bank->gpio_regs->int_polarity); | |
462 | out: | |
936ee267 JX |
463 | raw_spin_unlock_irqrestore(&bank->slock, flags); |
464 | ||
3bcbd1a8 | 465 | return ret; |
936ee267 JX |
466 | } |
467 | ||
adc8b4bf JK |
468 | static int rockchip_irq_reqres(struct irq_data *d) |
469 | { | |
470 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
471 | struct rockchip_pin_bank *bank = gc->private; | |
472 | ||
473 | return gpiochip_reqres_irq(&bank->gpio_chip, d->hwirq); | |
474 | } | |
475 | ||
476 | static void rockchip_irq_relres(struct irq_data *d) | |
477 | { | |
478 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
479 | struct rockchip_pin_bank *bank = gc->private; | |
480 | ||
481 | gpiochip_relres_irq(&bank->gpio_chip, d->hwirq); | |
482 | } | |
483 | ||
936ee267 JX |
484 | static void rockchip_irq_suspend(struct irq_data *d) |
485 | { | |
486 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
487 | struct rockchip_pin_bank *bank = gc->private; | |
488 | ||
ff96a8c2 JX |
489 | bank->saved_masks = irq_reg_readl(gc, bank->gpio_regs->int_mask); |
490 | irq_reg_writel(gc, ~gc->wake_active, bank->gpio_regs->int_mask); | |
936ee267 JX |
491 | } |
492 | ||
493 | static void rockchip_irq_resume(struct irq_data *d) | |
494 | { | |
495 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
496 | struct rockchip_pin_bank *bank = gc->private; | |
497 | ||
ff96a8c2 | 498 | irq_reg_writel(gc, bank->saved_masks, bank->gpio_regs->int_mask); |
936ee267 JX |
499 | } |
500 | ||
501 | static void rockchip_irq_enable(struct irq_data *d) | |
502 | { | |
936ee267 JX |
503 | irq_gc_mask_clr_bit(d); |
504 | } | |
505 | ||
506 | static void rockchip_irq_disable(struct irq_data *d) | |
507 | { | |
936ee267 | 508 | irq_gc_mask_set_bit(d); |
936ee267 JX |
509 | } |
510 | ||
511 | static int rockchip_interrupts_register(struct rockchip_pin_bank *bank) | |
512 | { | |
513 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | |
514 | struct irq_chip_generic *gc; | |
515 | int ret; | |
516 | ||
517 | bank->domain = irq_domain_add_linear(bank->of_node, 32, | |
518 | &irq_generic_chip_ops, NULL); | |
519 | if (!bank->domain) { | |
520 | dev_warn(bank->dev, "could not init irq domain for bank %s\n", | |
521 | bank->name); | |
522 | return -EINVAL; | |
523 | } | |
524 | ||
525 | ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, | |
526 | "rockchip_gpio_irq", | |
527 | handle_level_irq, | |
528 | clr, 0, 0); | |
529 | if (ret) { | |
530 | dev_err(bank->dev, "could not alloc generic chips for bank %s\n", | |
531 | bank->name); | |
532 | irq_domain_remove(bank->domain); | |
533 | return -EINVAL; | |
534 | } | |
535 | ||
536 | gc = irq_get_domain_generic_chip(bank->domain, 0); | |
3bcbd1a8 JX |
537 | if (bank->gpio_type == GPIO_TYPE_V2) { |
538 | gc->reg_writel = gpio_writel_v2; | |
539 | gc->reg_readl = gpio_readl_v2; | |
540 | } | |
541 | ||
936ee267 JX |
542 | gc->reg_base = bank->reg_base; |
543 | gc->private = bank; | |
ff96a8c2 JX |
544 | gc->chip_types[0].regs.mask = bank->gpio_regs->int_mask; |
545 | gc->chip_types[0].regs.ack = bank->gpio_regs->port_eoi; | |
936ee267 JX |
546 | gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; |
547 | gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit; | |
548 | gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit; | |
549 | gc->chip_types[0].chip.irq_enable = rockchip_irq_enable; | |
550 | gc->chip_types[0].chip.irq_disable = rockchip_irq_disable; | |
551 | gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; | |
552 | gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend; | |
553 | gc->chip_types[0].chip.irq_resume = rockchip_irq_resume; | |
554 | gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; | |
adc8b4bf JK |
555 | gc->chip_types[0].chip.irq_request_resources = rockchip_irq_reqres; |
556 | gc->chip_types[0].chip.irq_release_resources = rockchip_irq_relres; | |
936ee267 JX |
557 | gc->wake_enabled = IRQ_MSK(bank->nr_pins); |
558 | ||
559 | /* | |
560 | * Linux assumes that all interrupts start out disabled/masked. | |
561 | * Our driver only uses the concept of masked and always keeps | |
562 | * things enabled, so for us that's all masked and all enabled. | |
563 | */ | |
3bcbd1a8 JX |
564 | rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_mask); |
565 | rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->port_eoi); | |
566 | rockchip_gpio_writel(bank, 0xffffffff, bank->gpio_regs->int_en); | |
936ee267 JX |
567 | gc->mask_cache = 0xffffffff; |
568 | ||
569 | irq_set_chained_handler_and_data(bank->irq, | |
570 | rockchip_irq_demux, bank); | |
571 | ||
572 | return 0; | |
573 | } | |
574 | ||
575 | static int rockchip_gpiolib_register(struct rockchip_pin_bank *bank) | |
576 | { | |
577 | struct gpio_chip *gc; | |
578 | int ret; | |
579 | ||
580 | bank->gpio_chip = rockchip_gpiolib_chip; | |
581 | ||
582 | gc = &bank->gpio_chip; | |
583 | gc->base = bank->pin_base; | |
584 | gc->ngpio = bank->nr_pins; | |
585 | gc->label = bank->name; | |
586 | gc->parent = bank->dev; | |
936ee267 JX |
587 | |
588 | ret = gpiochip_add_data(gc, bank); | |
589 | if (ret) { | |
590 | dev_err(bank->dev, "failed to add gpiochip %s, %d\n", | |
591 | gc->label, ret); | |
592 | return ret; | |
593 | } | |
594 | ||
595 | /* | |
596 | * For DeviceTree-supported systems, the gpio core checks the | |
597 | * pinctrl's device node for the "gpio-ranges" property. | |
598 | * If it is present, it takes care of adding the pin ranges | |
599 | * for the driver. In this case the driver can skip ahead. | |
600 | * | |
601 | * In order to remain compatible with older, existing DeviceTree | |
602 | * files which don't set the "gpio-ranges" property or systems that | |
603 | * utilize ACPI the driver has to call gpiochip_add_pin_range(). | |
604 | */ | |
605 | if (!of_property_read_bool(bank->of_node, "gpio-ranges")) { | |
606 | struct device_node *pctlnp = of_get_parent(bank->of_node); | |
607 | struct pinctrl_dev *pctldev = NULL; | |
608 | ||
609 | if (!pctlnp) | |
610 | return -ENODATA; | |
611 | ||
612 | pctldev = of_pinctrl_get(pctlnp); | |
63ff545a | 613 | of_node_put(pctlnp); |
936ee267 JX |
614 | if (!pctldev) |
615 | return -ENODEV; | |
616 | ||
617 | ret = gpiochip_add_pin_range(gc, dev_name(pctldev->dev), 0, | |
618 | gc->base, gc->ngpio); | |
619 | if (ret) { | |
620 | dev_err(bank->dev, "Failed to add pin range\n"); | |
621 | goto fail; | |
622 | } | |
623 | } | |
624 | ||
625 | ret = rockchip_interrupts_register(bank); | |
626 | if (ret) { | |
627 | dev_err(bank->dev, "failed to register interrupt, %d\n", ret); | |
628 | goto fail; | |
629 | } | |
630 | ||
631 | return 0; | |
632 | ||
633 | fail: | |
634 | gpiochip_remove(&bank->gpio_chip); | |
635 | ||
636 | return ret; | |
637 | } | |
638 | ||
639 | static int rockchip_get_bank_data(struct rockchip_pin_bank *bank) | |
640 | { | |
641 | struct resource res; | |
3bcbd1a8 | 642 | int id = 0; |
936ee267 JX |
643 | |
644 | if (of_address_to_resource(bank->of_node, 0, &res)) { | |
645 | dev_err(bank->dev, "cannot find IO resource for bank\n"); | |
646 | return -ENOENT; | |
647 | } | |
648 | ||
649 | bank->reg_base = devm_ioremap_resource(bank->dev, &res); | |
650 | if (IS_ERR(bank->reg_base)) | |
651 | return PTR_ERR(bank->reg_base); | |
652 | ||
653 | bank->irq = irq_of_parse_and_map(bank->of_node, 0); | |
3bcbd1a8 JX |
654 | if (!bank->irq) |
655 | return -EINVAL; | |
ff96a8c2 | 656 | |
936ee267 | 657 | bank->clk = of_clk_get(bank->of_node, 0); |
3bcbd1a8 JX |
658 | if (IS_ERR(bank->clk)) |
659 | return PTR_ERR(bank->clk); | |
660 | ||
661 | clk_prepare_enable(bank->clk); | |
662 | id = readl(bank->reg_base + gpio_regs_v2.version_id); | |
663 | ||
664 | /* If not gpio v2, that is default to v1. */ | |
cc165ba4 | 665 | if (id == GPIO_TYPE_V2 || id == GPIO_TYPE_V2_1) { |
3bcbd1a8 JX |
666 | bank->gpio_regs = &gpio_regs_v2; |
667 | bank->gpio_type = GPIO_TYPE_V2; | |
668 | bank->db_clk = of_clk_get(bank->of_node, 1); | |
669 | if (IS_ERR(bank->db_clk)) { | |
670 | dev_err(bank->dev, "cannot find debounce clk\n"); | |
671 | clk_disable_unprepare(bank->clk); | |
672 | return -EINVAL; | |
673 | } | |
674 | } else { | |
675 | bank->gpio_regs = &gpio_regs_v1; | |
676 | bank->gpio_type = GPIO_TYPE_V1; | |
677 | } | |
936ee267 | 678 | |
936ee267 JX |
679 | return 0; |
680 | } | |
681 | ||
682 | static struct rockchip_pin_bank * | |
683 | rockchip_gpio_find_bank(struct pinctrl_dev *pctldev, int id) | |
684 | { | |
685 | struct rockchip_pinctrl *info; | |
686 | struct rockchip_pin_bank *bank; | |
687 | int i, found = 0; | |
688 | ||
689 | info = pinctrl_dev_get_drvdata(pctldev); | |
690 | bank = info->ctrl->pin_banks; | |
691 | for (i = 0; i < info->ctrl->nr_banks; i++, bank++) { | |
692 | if (bank->bank_num == id) { | |
693 | found = 1; | |
694 | break; | |
695 | } | |
696 | } | |
697 | ||
698 | return found ? bank : NULL; | |
699 | } | |
700 | ||
701 | static int rockchip_gpio_probe(struct platform_device *pdev) | |
702 | { | |
703 | struct device *dev = &pdev->dev; | |
704 | struct device_node *np = dev->of_node; | |
705 | struct device_node *pctlnp = of_get_parent(np); | |
706 | struct pinctrl_dev *pctldev = NULL; | |
707 | struct rockchip_pin_bank *bank = NULL; | |
8ce5ef64 | 708 | struct rockchip_pin_deferred *cfg; |
936ee267 JX |
709 | static int gpio; |
710 | int id, ret; | |
711 | ||
712 | if (!np || !pctlnp) | |
713 | return -ENODEV; | |
714 | ||
715 | pctldev = of_pinctrl_get(pctlnp); | |
716 | if (!pctldev) | |
717 | return -EPROBE_DEFER; | |
718 | ||
719 | id = of_alias_get_id(np, "gpio"); | |
720 | if (id < 0) | |
721 | id = gpio++; | |
722 | ||
723 | bank = rockchip_gpio_find_bank(pctldev, id); | |
724 | if (!bank) | |
725 | return -EINVAL; | |
726 | ||
727 | bank->dev = dev; | |
728 | bank->of_node = np; | |
729 | ||
730 | raw_spin_lock_init(&bank->slock); | |
731 | ||
732 | ret = rockchip_get_bank_data(bank); | |
733 | if (ret) | |
734 | return ret; | |
735 | ||
59dd178e HS |
736 | /* |
737 | * Prevent clashes with a deferred output setting | |
738 | * being added right at this moment. | |
739 | */ | |
740 | mutex_lock(&bank->deferred_lock); | |
741 | ||
936ee267 JX |
742 | ret = rockchip_gpiolib_register(bank); |
743 | if (ret) { | |
744 | clk_disable_unprepare(bank->clk); | |
59dd178e | 745 | mutex_unlock(&bank->deferred_lock); |
936ee267 JX |
746 | return ret; |
747 | } | |
748 | ||
8ce5ef64 CC |
749 | while (!list_empty(&bank->deferred_pins)) { |
750 | cfg = list_first_entry(&bank->deferred_pins, | |
751 | struct rockchip_pin_deferred, head); | |
59dd178e HS |
752 | list_del(&cfg->head); |
753 | ||
8ce5ef64 CC |
754 | switch (cfg->param) { |
755 | case PIN_CONFIG_OUTPUT: | |
756 | ret = rockchip_gpio_direction_output(&bank->gpio_chip, cfg->pin, cfg->arg); | |
757 | if (ret) | |
758 | dev_warn(dev, "setting output pin %u to %u failed\n", cfg->pin, | |
759 | cfg->arg); | |
760 | break; | |
7ff11357 CC |
761 | case PIN_CONFIG_INPUT_ENABLE: |
762 | ret = rockchip_gpio_direction_input(&bank->gpio_chip, cfg->pin); | |
763 | if (ret) | |
764 | dev_warn(dev, "setting input pin %u failed\n", cfg->pin); | |
765 | break; | |
8ce5ef64 CC |
766 | default: |
767 | dev_warn(dev, "unknown deferred config param %d\n", cfg->param); | |
768 | break; | |
769 | } | |
59dd178e HS |
770 | kfree(cfg); |
771 | } | |
772 | ||
773 | mutex_unlock(&bank->deferred_lock); | |
774 | ||
936ee267 JX |
775 | platform_set_drvdata(pdev, bank); |
776 | dev_info(dev, "probed %pOF\n", np); | |
777 | ||
778 | return 0; | |
779 | } | |
780 | ||
12305969 | 781 | static void rockchip_gpio_remove(struct platform_device *pdev) |
936ee267 JX |
782 | { |
783 | struct rockchip_pin_bank *bank = platform_get_drvdata(pdev); | |
784 | ||
785 | clk_disable_unprepare(bank->clk); | |
786 | gpiochip_remove(&bank->gpio_chip); | |
936ee267 JX |
787 | } |
788 | ||
789 | static const struct of_device_id rockchip_gpio_match[] = { | |
790 | { .compatible = "rockchip,gpio-bank", }, | |
791 | { .compatible = "rockchip,rk3188-gpio-bank0" }, | |
792 | { }, | |
793 | }; | |
794 | ||
795 | static struct platform_driver rockchip_gpio_driver = { | |
796 | .probe = rockchip_gpio_probe, | |
12305969 | 797 | .remove_new = rockchip_gpio_remove, |
936ee267 JX |
798 | .driver = { |
799 | .name = "rockchip-gpio", | |
800 | .of_match_table = rockchip_gpio_match, | |
801 | }, | |
802 | }; | |
803 | ||
804 | static int __init rockchip_gpio_init(void) | |
805 | { | |
806 | return platform_driver_register(&rockchip_gpio_driver); | |
807 | } | |
808 | postcore_initcall(rockchip_gpio_init); | |
809 | ||
810 | static void __exit rockchip_gpio_exit(void) | |
811 | { | |
812 | platform_driver_unregister(&rockchip_gpio_driver); | |
813 | } | |
814 | module_exit(rockchip_gpio_exit); | |
815 | ||
816 | MODULE_DESCRIPTION("Rockchip gpio driver"); | |
817 | MODULE_ALIAS("platform:rockchip-gpio"); | |
818 | MODULE_LICENSE("GPL v2"); | |
819 | MODULE_DEVICE_TABLE(of, rockchip_gpio_match); |