Commit | Line | Data |
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8b37eb74 | 1 | // SPDX-License-Identifier: GPL-2.0 |
119f5e44 MD |
2 | /* |
3 | * Renesas R-Car GPIO Support | |
4 | * | |
1fd2b49d | 5 | * Copyright (C) 2014 Renesas Electronics Corporation |
119f5e44 | 6 | * Copyright (C) 2013 Magnus Damm |
119f5e44 MD |
7 | */ |
8 | ||
9 | #include <linux/err.h> | |
4b1d8007 | 10 | #include <linux/gpio/driver.h> |
119f5e44 MD |
11 | #include <linux/init.h> |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/io.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/irq.h> | |
119f5e44 | 16 | #include <linux/module.h> |
bd0bf468 | 17 | #include <linux/of.h> |
f9f2a6fe | 18 | #include <linux/of_device.h> |
dc3465a9 | 19 | #include <linux/pinctrl/consumer.h> |
119f5e44 | 20 | #include <linux/platform_device.h> |
df0c6c80 | 21 | #include <linux/pm_runtime.h> |
119f5e44 MD |
22 | #include <linux/spinlock.h> |
23 | #include <linux/slab.h> | |
24 | ||
51750fb1 HD |
25 | struct gpio_rcar_bank_info { |
26 | u32 iointsel; | |
27 | u32 inoutsel; | |
28 | u32 outdt; | |
29 | u32 posneg; | |
30 | u32 edglevel; | |
31 | u32 bothedge; | |
32 | u32 intmsk; | |
33 | }; | |
34 | ||
119f5e44 MD |
35 | struct gpio_rcar_priv { |
36 | void __iomem *base; | |
37 | spinlock_t lock; | |
a53f7953 | 38 | struct device *dev; |
119f5e44 MD |
39 | struct gpio_chip gpio_chip; |
40 | struct irq_chip irq_chip; | |
8b092be9 | 41 | unsigned int irq_parent; |
9ac79ba9 | 42 | atomic_t wakeup_path; |
3ae4f3aa | 43 | bool has_outdtsel; |
8b092be9 | 44 | bool has_both_edge_trigger; |
51750fb1 | 45 | struct gpio_rcar_bank_info bank_info; |
119f5e44 MD |
46 | }; |
47 | ||
3dc1e685 GU |
48 | #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ |
49 | #define INOUTSEL 0x04 /* General Input/Output Switching Register */ | |
50 | #define OUTDT 0x08 /* General Output Register */ | |
51 | #define INDT 0x0c /* General Input Register */ | |
52 | #define INTDT 0x10 /* Interrupt Display Register */ | |
53 | #define INTCLR 0x14 /* Interrupt Clear Register */ | |
54 | #define INTMSK 0x18 /* Interrupt Mask Register */ | |
55 | #define MSKCLR 0x1c /* Interrupt Mask Clear Register */ | |
56 | #define POSNEG 0x20 /* Positive/Negative Logic Select Register */ | |
57 | #define EDGLEVEL 0x24 /* Edge/level Select Register */ | |
58 | #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */ | |
3ae4f3aa | 59 | #define OUTDTSEL 0x40 /* Output Data Select Register */ |
3dc1e685 | 60 | #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */ |
119f5e44 | 61 | |
159f8a02 LP |
62 | #define RCAR_MAX_GPIO_PER_BANK 32 |
63 | ||
119f5e44 MD |
64 | static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) |
65 | { | |
66 | return ioread32(p->base + offs); | |
67 | } | |
68 | ||
69 | static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs, | |
70 | u32 value) | |
71 | { | |
72 | iowrite32(value, p->base + offs); | |
73 | } | |
74 | ||
75 | static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs, | |
76 | int bit, bool value) | |
77 | { | |
78 | u32 tmp = gpio_rcar_read(p, offs); | |
79 | ||
80 | if (value) | |
81 | tmp |= BIT(bit); | |
82 | else | |
83 | tmp &= ~BIT(bit); | |
84 | ||
85 | gpio_rcar_write(p, offs, tmp); | |
86 | } | |
87 | ||
88 | static void gpio_rcar_irq_disable(struct irq_data *d) | |
89 | { | |
c7f3c5d3 | 90 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
c7b6f457 | 91 | struct gpio_rcar_priv *p = gpiochip_get_data(gc); |
119f5e44 MD |
92 | |
93 | gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d))); | |
94 | } | |
95 | ||
96 | static void gpio_rcar_irq_enable(struct irq_data *d) | |
97 | { | |
c7f3c5d3 | 98 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
c7b6f457 | 99 | struct gpio_rcar_priv *p = gpiochip_get_data(gc); |
119f5e44 MD |
100 | |
101 | gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); | |
102 | } | |
103 | ||
104 | static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, | |
105 | unsigned int hwirq, | |
106 | bool active_high_rising_edge, | |
7e1092b5 SH |
107 | bool level_trigger, |
108 | bool both) | |
119f5e44 MD |
109 | { |
110 | unsigned long flags; | |
111 | ||
112 | /* follow steps in the GPIO documentation for | |
113 | * "Setting Edge-Sensitive Interrupt Input Mode" and | |
114 | * "Setting Level-Sensitive Interrupt Input Mode" | |
115 | */ | |
116 | ||
117 | spin_lock_irqsave(&p->lock, flags); | |
118 | ||
b36368f6 | 119 | /* Configure positive or negative logic in POSNEG */ |
119f5e44 MD |
120 | gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); |
121 | ||
122 | /* Configure edge or level trigger in EDGLEVEL */ | |
123 | gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); | |
124 | ||
7e1092b5 | 125 | /* Select one edge or both edges in BOTHEDGE */ |
8b092be9 | 126 | if (p->has_both_edge_trigger) |
7e1092b5 SH |
127 | gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both); |
128 | ||
119f5e44 MD |
129 | /* Select "Interrupt Input Mode" in IOINTSEL */ |
130 | gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); | |
131 | ||
132 | /* Write INTCLR in case of edge trigger */ | |
133 | if (!level_trigger) | |
134 | gpio_rcar_write(p, INTCLR, BIT(hwirq)); | |
135 | ||
136 | spin_unlock_irqrestore(&p->lock, flags); | |
137 | } | |
138 | ||
139 | static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) | |
140 | { | |
c7f3c5d3 | 141 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
c7b6f457 | 142 | struct gpio_rcar_priv *p = gpiochip_get_data(gc); |
119f5e44 MD |
143 | unsigned int hwirq = irqd_to_hwirq(d); |
144 | ||
a53f7953 | 145 | dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type); |
119f5e44 MD |
146 | |
147 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
148 | case IRQ_TYPE_LEVEL_HIGH: | |
7e1092b5 SH |
149 | gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true, |
150 | false); | |
119f5e44 MD |
151 | break; |
152 | case IRQ_TYPE_LEVEL_LOW: | |
7e1092b5 SH |
153 | gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true, |
154 | false); | |
119f5e44 MD |
155 | break; |
156 | case IRQ_TYPE_EDGE_RISING: | |
7e1092b5 SH |
157 | gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, |
158 | false); | |
119f5e44 MD |
159 | break; |
160 | case IRQ_TYPE_EDGE_FALLING: | |
7e1092b5 SH |
161 | gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false, |
162 | false); | |
163 | break; | |
164 | case IRQ_TYPE_EDGE_BOTH: | |
8b092be9 | 165 | if (!p->has_both_edge_trigger) |
7e1092b5 SH |
166 | return -EINVAL; |
167 | gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, | |
168 | true); | |
119f5e44 MD |
169 | break; |
170 | default: | |
171 | return -EINVAL; | |
172 | } | |
173 | return 0; | |
174 | } | |
175 | ||
ab82fa7d GU |
176 | static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on) |
177 | { | |
178 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
c7b6f457 | 179 | struct gpio_rcar_priv *p = gpiochip_get_data(gc); |
501ef0f9 GU |
180 | int error; |
181 | ||
182 | if (p->irq_parent) { | |
183 | error = irq_set_irq_wake(p->irq_parent, on); | |
184 | if (error) { | |
a53f7953 | 185 | dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n", |
501ef0f9 GU |
186 | p->irq_parent); |
187 | p->irq_parent = 0; | |
188 | } | |
189 | } | |
ab82fa7d | 190 | |
ab82fa7d | 191 | if (on) |
9ac79ba9 | 192 | atomic_inc(&p->wakeup_path); |
ab82fa7d | 193 | else |
9ac79ba9 | 194 | atomic_dec(&p->wakeup_path); |
ab82fa7d GU |
195 | |
196 | return 0; | |
197 | } | |
198 | ||
119f5e44 MD |
199 | static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) |
200 | { | |
201 | struct gpio_rcar_priv *p = dev_id; | |
202 | u32 pending; | |
203 | unsigned int offset, irqs_handled = 0; | |
204 | ||
8808b64d VB |
205 | while ((pending = gpio_rcar_read(p, INTDT) & |
206 | gpio_rcar_read(p, INTMSK))) { | |
119f5e44 MD |
207 | offset = __ffs(pending); |
208 | gpio_rcar_write(p, INTCLR, BIT(offset)); | |
f0fbe7bc | 209 | generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain, |
c7f3c5d3 | 210 | offset)); |
119f5e44 MD |
211 | irqs_handled++; |
212 | } | |
213 | ||
214 | return irqs_handled ? IRQ_HANDLED : IRQ_NONE; | |
215 | } | |
216 | ||
119f5e44 MD |
217 | static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, |
218 | unsigned int gpio, | |
219 | bool output) | |
220 | { | |
c7b6f457 | 221 | struct gpio_rcar_priv *p = gpiochip_get_data(chip); |
119f5e44 MD |
222 | unsigned long flags; |
223 | ||
224 | /* follow steps in the GPIO documentation for | |
225 | * "Setting General Output Mode" and | |
226 | * "Setting General Input Mode" | |
227 | */ | |
228 | ||
229 | spin_lock_irqsave(&p->lock, flags); | |
230 | ||
b36368f6 | 231 | /* Configure positive logic in POSNEG */ |
119f5e44 MD |
232 | gpio_rcar_modify_bit(p, POSNEG, gpio, false); |
233 | ||
234 | /* Select "General Input/Output Mode" in IOINTSEL */ | |
235 | gpio_rcar_modify_bit(p, IOINTSEL, gpio, false); | |
236 | ||
237 | /* Select Input Mode or Output Mode in INOUTSEL */ | |
238 | gpio_rcar_modify_bit(p, INOUTSEL, gpio, output); | |
239 | ||
3ae4f3aa VZ |
240 | /* Select General Output Register to output data in OUTDTSEL */ |
241 | if (p->has_outdtsel && output) | |
242 | gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false); | |
243 | ||
119f5e44 MD |
244 | spin_unlock_irqrestore(&p->lock, flags); |
245 | } | |
246 | ||
dc3465a9 LP |
247 | static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) |
248 | { | |
2d65472b GU |
249 | struct gpio_rcar_priv *p = gpiochip_get_data(chip); |
250 | int error; | |
251 | ||
a53f7953 | 252 | error = pm_runtime_get_sync(p->dev); |
6f8cd246 DL |
253 | if (error < 0) { |
254 | pm_runtime_put(p->dev); | |
2d65472b | 255 | return error; |
6f8cd246 | 256 | } |
2d65472b | 257 | |
a9a1d2a7 | 258 | error = pinctrl_gpio_request(chip->base + offset); |
2d65472b | 259 | if (error) |
a53f7953 | 260 | pm_runtime_put(p->dev); |
2d65472b GU |
261 | |
262 | return error; | |
dc3465a9 LP |
263 | } |
264 | ||
265 | static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) | |
266 | { | |
2d65472b GU |
267 | struct gpio_rcar_priv *p = gpiochip_get_data(chip); |
268 | ||
a9a1d2a7 | 269 | pinctrl_gpio_free(chip->base + offset); |
dc3465a9 | 270 | |
ce0e2c60 LW |
271 | /* |
272 | * Set the GPIO as an input to ensure that the next GPIO request won't | |
dc3465a9 LP |
273 | * drive the GPIO pin as an output. |
274 | */ | |
275 | gpio_rcar_config_general_input_output_mode(chip, offset, false); | |
2d65472b | 276 | |
a53f7953 | 277 | pm_runtime_put(p->dev); |
dc3465a9 LP |
278 | } |
279 | ||
ad817297 GU |
280 | static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset) |
281 | { | |
282 | struct gpio_rcar_priv *p = gpiochip_get_data(chip); | |
283 | ||
e42615ec MV |
284 | if (gpio_rcar_read(p, INOUTSEL) & BIT(offset)) |
285 | return GPIO_LINE_DIRECTION_OUT; | |
286 | ||
287 | return GPIO_LINE_DIRECTION_IN; | |
ad817297 GU |
288 | } |
289 | ||
119f5e44 MD |
290 | static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) |
291 | { | |
292 | gpio_rcar_config_general_input_output_mode(chip, offset, false); | |
293 | return 0; | |
294 | } | |
295 | ||
296 | static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) | |
297 | { | |
ae9550f6 MD |
298 | u32 bit = BIT(offset); |
299 | ||
300 | /* testing on r8a7790 shows that INDT does not show correct pin state | |
301 | * when configured as output, so use OUTDT in case of output pins */ | |
c7b6f457 LW |
302 | if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit) |
303 | return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit); | |
ae9550f6 | 304 | else |
c7b6f457 | 305 | return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit); |
119f5e44 MD |
306 | } |
307 | ||
308 | static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value) | |
309 | { | |
c7b6f457 | 310 | struct gpio_rcar_priv *p = gpiochip_get_data(chip); |
119f5e44 MD |
311 | unsigned long flags; |
312 | ||
313 | spin_lock_irqsave(&p->lock, flags); | |
314 | gpio_rcar_modify_bit(p, OUTDT, offset, value); | |
315 | spin_unlock_irqrestore(&p->lock, flags); | |
316 | } | |
317 | ||
dbb763b8 GU |
318 | static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask, |
319 | unsigned long *bits) | |
320 | { | |
321 | struct gpio_rcar_priv *p = gpiochip_get_data(chip); | |
322 | unsigned long flags; | |
323 | u32 val, bankmask; | |
324 | ||
325 | bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); | |
496069b8 BD |
326 | if (chip->valid_mask) |
327 | bankmask &= chip->valid_mask[0]; | |
328 | ||
dbb763b8 GU |
329 | if (!bankmask) |
330 | return; | |
331 | ||
332 | spin_lock_irqsave(&p->lock, flags); | |
333 | val = gpio_rcar_read(p, OUTDT); | |
334 | val &= ~bankmask; | |
335 | val |= (bankmask & bits[0]); | |
336 | gpio_rcar_write(p, OUTDT, val); | |
337 | spin_unlock_irqrestore(&p->lock, flags); | |
338 | } | |
339 | ||
119f5e44 MD |
340 | static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset, |
341 | int value) | |
342 | { | |
343 | /* write GPIO value to output before selecting output mode of pin */ | |
344 | gpio_rcar_set(chip, offset, value); | |
345 | gpio_rcar_config_general_input_output_mode(chip, offset, true); | |
346 | return 0; | |
347 | } | |
348 | ||
850dfe17 | 349 | struct gpio_rcar_info { |
3ae4f3aa | 350 | bool has_outdtsel; |
850dfe17 LP |
351 | bool has_both_edge_trigger; |
352 | }; | |
353 | ||
1fd2b49d | 354 | static const struct gpio_rcar_info gpio_rcar_info_gen1 = { |
3ae4f3aa | 355 | .has_outdtsel = false, |
1fd2b49d HN |
356 | .has_both_edge_trigger = false, |
357 | }; | |
358 | ||
359 | static const struct gpio_rcar_info gpio_rcar_info_gen2 = { | |
3ae4f3aa | 360 | .has_outdtsel = true, |
1fd2b49d HN |
361 | .has_both_edge_trigger = true, |
362 | }; | |
363 | ||
850dfe17 LP |
364 | static const struct of_device_id gpio_rcar_of_table[] = { |
365 | { | |
85bb4646 BD |
366 | .compatible = "renesas,gpio-r8a7743", |
367 | /* RZ/G1 GPIO is identical to R-Car Gen2. */ | |
368 | .data = &gpio_rcar_info_gen2, | |
369 | }, { | |
850dfe17 | 370 | .compatible = "renesas,gpio-r8a7790", |
1fd2b49d | 371 | .data = &gpio_rcar_info_gen2, |
850dfe17 LP |
372 | }, { |
373 | .compatible = "renesas,gpio-r8a7791", | |
1fd2b49d | 374 | .data = &gpio_rcar_info_gen2, |
e79c5830 SS |
375 | }, { |
376 | .compatible = "renesas,gpio-r8a7792", | |
377 | .data = &gpio_rcar_info_gen2, | |
1fd2b49d HN |
378 | }, { |
379 | .compatible = "renesas,gpio-r8a7793", | |
380 | .data = &gpio_rcar_info_gen2, | |
381 | }, { | |
382 | .compatible = "renesas,gpio-r8a7794", | |
383 | .data = &gpio_rcar_info_gen2, | |
8cd14702 UH |
384 | }, { |
385 | .compatible = "renesas,gpio-r8a7795", | |
386 | /* Gen3 GPIO is identical to Gen2. */ | |
387 | .data = &gpio_rcar_info_gen2, | |
5d2f1d6e SH |
388 | }, { |
389 | .compatible = "renesas,gpio-r8a7796", | |
390 | /* Gen3 GPIO is identical to Gen2. */ | |
391 | .data = &gpio_rcar_info_gen2, | |
dbd1dad2 SH |
392 | }, { |
393 | .compatible = "renesas,rcar-gen1-gpio", | |
394 | .data = &gpio_rcar_info_gen1, | |
395 | }, { | |
396 | .compatible = "renesas,rcar-gen2-gpio", | |
397 | .data = &gpio_rcar_info_gen2, | |
398 | }, { | |
399 | .compatible = "renesas,rcar-gen3-gpio", | |
400 | /* Gen3 GPIO is identical to Gen2. */ | |
401 | .data = &gpio_rcar_info_gen2, | |
850dfe17 LP |
402 | }, { |
403 | .compatible = "renesas,gpio-rcar", | |
1fd2b49d | 404 | .data = &gpio_rcar_info_gen1, |
850dfe17 LP |
405 | }, { |
406 | /* Terminator */ | |
407 | }, | |
408 | }; | |
409 | ||
410 | MODULE_DEVICE_TABLE(of, gpio_rcar_of_table); | |
411 | ||
8b092be9 | 412 | static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins) |
159f8a02 | 413 | { |
a53f7953 | 414 | struct device_node *np = p->dev->of_node; |
8b092be9 | 415 | const struct gpio_rcar_info *info; |
159f8a02 LP |
416 | struct of_phandle_args args; |
417 | int ret; | |
159f8a02 | 418 | |
a53f7953 | 419 | info = of_device_get_match_data(p->dev); |
3ae4f3aa VZ |
420 | p->has_outdtsel = info->has_outdtsel; |
421 | p->has_both_edge_trigger = info->has_both_edge_trigger; | |
850dfe17 | 422 | |
8b092be9 GU |
423 | ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args); |
424 | *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK; | |
850dfe17 | 425 | |
8b092be9 | 426 | if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) { |
a53f7953 VZ |
427 | dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n", |
428 | *npins, RCAR_MAX_GPIO_PER_BANK); | |
8b092be9 | 429 | *npins = RCAR_MAX_GPIO_PER_BANK; |
159f8a02 | 430 | } |
850dfe17 LP |
431 | |
432 | return 0; | |
159f8a02 LP |
433 | } |
434 | ||
119f5e44 MD |
435 | static int gpio_rcar_probe(struct platform_device *pdev) |
436 | { | |
119f5e44 | 437 | struct gpio_rcar_priv *p; |
ecbf7c2e | 438 | struct resource *irq; |
119f5e44 MD |
439 | struct gpio_chip *gpio_chip; |
440 | struct irq_chip *irq_chip; | |
b22978fc GU |
441 | struct device *dev = &pdev->dev; |
442 | const char *name = dev_name(dev); | |
8b092be9 | 443 | unsigned int npins; |
119f5e44 MD |
444 | int ret; |
445 | ||
b22978fc | 446 | p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); |
7d82bf34 GU |
447 | if (!p) |
448 | return -ENOMEM; | |
119f5e44 | 449 | |
a53f7953 | 450 | p->dev = dev; |
119f5e44 MD |
451 | spin_lock_init(&p->lock); |
452 | ||
8b092be9 GU |
453 | /* Get device configuration from DT node */ |
454 | ret = gpio_rcar_parse_dt(p, &npins); | |
850dfe17 LP |
455 | if (ret < 0) |
456 | return ret; | |
159f8a02 LP |
457 | |
458 | platform_set_drvdata(pdev, p); | |
459 | ||
df0c6c80 | 460 | pm_runtime_enable(dev); |
df0c6c80 | 461 | |
119f5e44 | 462 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
5a24d4b6 SS |
463 | if (!irq) { |
464 | dev_err(dev, "missing IRQ\n"); | |
119f5e44 MD |
465 | ret = -EINVAL; |
466 | goto err0; | |
467 | } | |
468 | ||
ecbf7c2e | 469 | p->base = devm_platform_ioremap_resource(pdev, 0); |
5a24d4b6 SS |
470 | if (IS_ERR(p->base)) { |
471 | ret = PTR_ERR(p->base); | |
119f5e44 MD |
472 | goto err0; |
473 | } | |
474 | ||
475 | gpio_chip = &p->gpio_chip; | |
dc3465a9 LP |
476 | gpio_chip->request = gpio_rcar_request; |
477 | gpio_chip->free = gpio_rcar_free; | |
ad817297 | 478 | gpio_chip->get_direction = gpio_rcar_get_direction; |
119f5e44 MD |
479 | gpio_chip->direction_input = gpio_rcar_direction_input; |
480 | gpio_chip->get = gpio_rcar_get; | |
481 | gpio_chip->direction_output = gpio_rcar_direction_output; | |
482 | gpio_chip->set = gpio_rcar_set; | |
dbb763b8 | 483 | gpio_chip->set_multiple = gpio_rcar_set_multiple; |
119f5e44 | 484 | gpio_chip->label = name; |
58383c78 | 485 | gpio_chip->parent = dev; |
119f5e44 | 486 | gpio_chip->owner = THIS_MODULE; |
8b092be9 GU |
487 | gpio_chip->base = -1; |
488 | gpio_chip->ngpio = npins; | |
119f5e44 MD |
489 | |
490 | irq_chip = &p->irq_chip; | |
f932a686 | 491 | irq_chip->name = "gpio-rcar"; |
47bd38a3 | 492 | irq_chip->parent_device = dev; |
119f5e44 MD |
493 | irq_chip->irq_mask = gpio_rcar_irq_disable; |
494 | irq_chip->irq_unmask = gpio_rcar_irq_enable; | |
119f5e44 | 495 | irq_chip->irq_set_type = gpio_rcar_irq_set_type; |
ab82fa7d | 496 | irq_chip->irq_set_wake = gpio_rcar_irq_set_wake; |
b183cab7 | 497 | irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND; |
119f5e44 | 498 | |
c7b6f457 | 499 | ret = gpiochip_add_data(gpio_chip, p); |
c7f3c5d3 GU |
500 | if (ret) { |
501 | dev_err(dev, "failed to add GPIO controller\n"); | |
0c8aab8e | 502 | goto err0; |
119f5e44 MD |
503 | } |
504 | ||
8b092be9 GU |
505 | ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq, |
506 | IRQ_TYPE_NONE); | |
c7f3c5d3 GU |
507 | if (ret) { |
508 | dev_err(dev, "cannot add irqchip\n"); | |
509 | goto err1; | |
510 | } | |
511 | ||
ab82fa7d | 512 | p->irq_parent = irq->start; |
b22978fc GU |
513 | if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler, |
514 | IRQF_SHARED, name, p)) { | |
515 | dev_err(dev, "failed to request IRQ\n"); | |
119f5e44 MD |
516 | ret = -ENOENT; |
517 | goto err1; | |
518 | } | |
519 | ||
8b092be9 | 520 | dev_info(dev, "driving %d GPIOs\n", npins); |
dc3465a9 | 521 | |
119f5e44 MD |
522 | return 0; |
523 | ||
524 | err1: | |
4d84b9e4 | 525 | gpiochip_remove(gpio_chip); |
119f5e44 | 526 | err0: |
df0c6c80 | 527 | pm_runtime_disable(dev); |
119f5e44 MD |
528 | return ret; |
529 | } | |
530 | ||
531 | static int gpio_rcar_remove(struct platform_device *pdev) | |
532 | { | |
533 | struct gpio_rcar_priv *p = platform_get_drvdata(pdev); | |
119f5e44 | 534 | |
9f5132ae | 535 | gpiochip_remove(&p->gpio_chip); |
119f5e44 | 536 | |
df0c6c80 | 537 | pm_runtime_disable(&pdev->dev); |
119f5e44 MD |
538 | return 0; |
539 | } | |
540 | ||
51750fb1 HD |
541 | #ifdef CONFIG_PM_SLEEP |
542 | static int gpio_rcar_suspend(struct device *dev) | |
543 | { | |
544 | struct gpio_rcar_priv *p = dev_get_drvdata(dev); | |
545 | ||
546 | p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL); | |
547 | p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL); | |
548 | p->bank_info.outdt = gpio_rcar_read(p, OUTDT); | |
549 | p->bank_info.intmsk = gpio_rcar_read(p, INTMSK); | |
550 | p->bank_info.posneg = gpio_rcar_read(p, POSNEG); | |
551 | p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL); | |
552 | if (p->has_both_edge_trigger) | |
553 | p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE); | |
554 | ||
9ac79ba9 GU |
555 | if (atomic_read(&p->wakeup_path)) |
556 | device_set_wakeup_path(dev); | |
557 | ||
51750fb1 HD |
558 | return 0; |
559 | } | |
560 | ||
561 | static int gpio_rcar_resume(struct device *dev) | |
562 | { | |
563 | struct gpio_rcar_priv *p = dev_get_drvdata(dev); | |
564 | unsigned int offset; | |
565 | u32 mask; | |
566 | ||
567 | for (offset = 0; offset < p->gpio_chip.ngpio; offset++) { | |
496069b8 BD |
568 | if (!gpiochip_line_is_valid(&p->gpio_chip, offset)) |
569 | continue; | |
570 | ||
51750fb1 HD |
571 | mask = BIT(offset); |
572 | /* I/O pin */ | |
573 | if (!(p->bank_info.iointsel & mask)) { | |
574 | if (p->bank_info.inoutsel & mask) | |
575 | gpio_rcar_direction_output( | |
576 | &p->gpio_chip, offset, | |
577 | !!(p->bank_info.outdt & mask)); | |
578 | else | |
579 | gpio_rcar_direction_input(&p->gpio_chip, | |
580 | offset); | |
581 | } else { | |
582 | /* Interrupt pin */ | |
583 | gpio_rcar_config_interrupt_input_mode( | |
584 | p, | |
585 | offset, | |
586 | !(p->bank_info.posneg & mask), | |
587 | !(p->bank_info.edglevel & mask), | |
588 | !!(p->bank_info.bothedge & mask)); | |
589 | ||
590 | if (p->bank_info.intmsk & mask) | |
591 | gpio_rcar_write(p, MSKCLR, mask); | |
592 | } | |
593 | } | |
594 | ||
595 | return 0; | |
596 | } | |
597 | #endif /* CONFIG_PM_SLEEP*/ | |
598 | ||
599 | static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume); | |
600 | ||
119f5e44 MD |
601 | static struct platform_driver gpio_rcar_device_driver = { |
602 | .probe = gpio_rcar_probe, | |
603 | .remove = gpio_rcar_remove, | |
604 | .driver = { | |
605 | .name = "gpio_rcar", | |
51750fb1 | 606 | .pm = &gpio_rcar_pm_ops, |
159f8a02 | 607 | .of_match_table = of_match_ptr(gpio_rcar_of_table), |
119f5e44 MD |
608 | } |
609 | }; | |
610 | ||
611 | module_platform_driver(gpio_rcar_device_driver); | |
612 | ||
613 | MODULE_AUTHOR("Magnus Damm"); | |
614 | MODULE_DESCRIPTION("Renesas R-Car GPIO Driver"); | |
615 | MODULE_LICENSE("GPL v2"); |