[linux-2.6-block.git] / drivers / gpio / gpio-rcar.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Renesas R-Car GPIO Support
 *
 *  Copyright (C) 2014 Renesas Electronics Corporation
 *  Copyright (C) 2013 Magnus Damm
 */

#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spinlock.h>
#include <linux/slab.h>

struct gpio_rcar_bank_info {
	u32 iointsel;
	u32 inoutsel;
	u32 outdt;
	u32 posneg;
	u32 edglevel;
	u32 bothedge;
	u32 intmsk;
};

struct gpio_rcar_info {
	bool has_outdtsel;
	bool has_both_edge_trigger;
};

struct gpio_rcar_priv {
	void __iomem *base;
	spinlock_t lock;
	struct device *dev;
	struct gpio_chip gpio_chip;
	struct irq_chip irq_chip;
	unsigned int irq_parent;
	atomic_t wakeup_path;
	struct gpio_rcar_info info;
	struct gpio_rcar_bank_info bank_info;
};

#define IOINTSEL	0x00	/* General IO/Interrupt Switching Register */
#define INOUTSEL	0x04	/* General Input/Output Switching Register */
#define OUTDT		0x08	/* General Output Register */
#define INDT		0x0c	/* General Input Register */
#define INTDT		0x10	/* Interrupt Display Register */
#define INTCLR		0x14	/* Interrupt Clear Register */
#define INTMSK		0x18	/* Interrupt Mask Register */
#define MSKCLR		0x1c	/* Interrupt Mask Clear Register */
#define POSNEG		0x20	/* Positive/Negative Logic Select Register */
#define EDGLEVEL	0x24	/* Edge/level Select Register */
#define FILONOFF	0x28	/* Chattering Prevention On/Off Register */
#define OUTDTSEL	0x40	/* Output Data Select Register */
#define BOTHEDGE	0x4c	/* One Edge/Both Edge Select Register */

#define RCAR_MAX_GPIO_PER_BANK		32

static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
{
	return ioread32(p->base + offs);
}

static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
				   u32 value)
{
	iowrite32(value, p->base + offs);
}

static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
				 int bit, bool value)
{
	u32 tmp = gpio_rcar_read(p, offs);

	if (value)
		tmp |= BIT(bit);
	else
		tmp &= ~BIT(bit);

	gpio_rcar_write(p, offs, tmp);
}

static void gpio_rcar_irq_disable(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);

	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
}

static void gpio_rcar_irq_enable(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);

	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
}

static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
						  unsigned int hwirq,
						  bool active_high_rising_edge,
						  bool level_trigger,
						  bool both)
{
	unsigned long flags;

	/* follow steps in the GPIO documentation for
	 * "Setting Edge-Sensitive Interrupt Input Mode" and
	 * "Setting Level-Sensitive Interrupt Input Mode"
	 */

	spin_lock_irqsave(&p->lock, flags);

	/* Configure positive or negative logic in POSNEG */
	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);

	/* Configure edge or level trigger in EDGLEVEL */
	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);

	/* Select one edge or both edges in BOTHEDGE */
	if (p->info.has_both_edge_trigger)
		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);

	/* Select "Interrupt Input Mode" in IOINTSEL */
	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);

	/* Write INTCLR in case of edge trigger */
	if (!level_trigger)
		gpio_rcar_write(p, INTCLR, BIT(hwirq));

	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
	unsigned int hwirq = irqd_to_hwirq(d);

	dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_LEVEL_HIGH:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
						      false);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
						      false);
		break;
	case IRQ_TYPE_EDGE_RISING:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
						      false);
		break;
	case IRQ_TYPE_EDGE_FALLING:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
						      false);
		break;
	case IRQ_TYPE_EDGE_BOTH:
		if (!p->info.has_both_edge_trigger)
			return -EINVAL;
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
						      true);
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
	int error;

	if (p->irq_parent) {
		error = irq_set_irq_wake(p->irq_parent, on);
		if (error) {
			dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
				p->irq_parent);
			p->irq_parent = 0;
		}
	}

	if (on)
		atomic_inc(&p->wakeup_path);
	else
		atomic_dec(&p->wakeup_path);

	return 0;
}

static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
{
	struct gpio_rcar_priv *p = dev_id;
	u32 pending;
	unsigned int offset, irqs_handled = 0;

	while ((pending = gpio_rcar_read(p, INTDT) &
			  gpio_rcar_read(p, INTMSK))) {
		offset = __ffs(pending);
		gpio_rcar_write(p, INTCLR, BIT(offset));
		generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
						    offset));
		irqs_handled++;
	}

	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
}

static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
						       unsigned int gpio,
						       bool output)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;

	/* follow steps in the GPIO documentation for
	 * "Setting General Output Mode" and
	 * "Setting General Input Mode"
	 */

	spin_lock_irqsave(&p->lock, flags);

	/* Configure positive logic in POSNEG */
	gpio_rcar_modify_bit(p, POSNEG, gpio, false);

	/* Select "General Input/Output Mode" in IOINTSEL */
	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);

	/* Select Input Mode or Output Mode in INOUTSEL */
	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);

	/* Select General Output Register to output data in OUTDTSEL */
	if (p->info.has_outdtsel && output)
		gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);

	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	int error;

	error = pm_runtime_get_sync(p->dev);
	if (error < 0) {
		pm_runtime_put(p->dev);
		return error;
	}

	error = pinctrl_gpio_request(chip->base + offset);
	if (error)
		pm_runtime_put(p->dev);

	return error;
}

static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);

	pinctrl_gpio_free(chip->base + offset);

	/*
	 * Set the GPIO as an input to ensure that the next GPIO request won't
	 * drive the GPIO pin as an output.
	 */
	gpio_rcar_config_general_input_output_mode(chip, offset, false);

	pm_runtime_put(p->dev);
}

static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);

	if (gpio_rcar_read(p, INOUTSEL) & BIT(offset))
		return GPIO_LINE_DIRECTION_OUT;

	return GPIO_LINE_DIRECTION_IN;
}

static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
{
	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	return 0;
}

static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	u32 bit = BIT(offset);

	/* testing on r8a7790 shows that INDT does not show correct pin state
	 * when configured as output, so use OUTDT in case of output pins */
	if (gpio_rcar_read(p, INOUTSEL) & bit)
		return !!(gpio_rcar_read(p, OUTDT) & bit);
	else
		return !!(gpio_rcar_read(p, INDT) & bit);
}

static int gpio_rcar_get_multiple(struct gpio_chip *chip, unsigned long *mask,
				  unsigned long *bits)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	u32 bankmask, outputs, m, val = 0;
	unsigned long flags;

	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
	if (chip->valid_mask)
		bankmask &= chip->valid_mask[0];

	if (!bankmask)
		return 0;

	spin_lock_irqsave(&p->lock, flags);
	outputs = gpio_rcar_read(p, INOUTSEL);
	m = outputs & bankmask;
	if (m)
		val |= gpio_rcar_read(p, OUTDT) & m;

	m = ~outputs & bankmask;
	if (m)
		val |= gpio_rcar_read(p, INDT) & m;
	spin_unlock_irqrestore(&p->lock, flags);

	bits[0] = val;
	return 0;
}

static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;

	spin_lock_irqsave(&p->lock, flags);
	gpio_rcar_modify_bit(p, OUTDT, offset, value);
	spin_unlock_irqrestore(&p->lock, flags);
}

static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
				   unsigned long *bits)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;
	u32 val, bankmask;

	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
	if (chip->valid_mask)
		bankmask &= chip->valid_mask[0];

	if (!bankmask)
		return;

	spin_lock_irqsave(&p->lock, flags);
	val = gpio_rcar_read(p, OUTDT);
	val &= ~bankmask;
	val |= (bankmask & bits[0]);
	gpio_rcar_write(p, OUTDT, val);
	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
				      int value)
{
	/* write GPIO value to output before selecting output mode of pin */
	gpio_rcar_set(chip, offset, value);
	gpio_rcar_config_general_input_output_mode(chip, offset, true);
	return 0;
}

static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
	.has_outdtsel = false,
	.has_both_edge_trigger = false,
};

static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
	.has_outdtsel = true,
	.has_both_edge_trigger = true,
};

static const struct of_device_id gpio_rcar_of_table[] = {
	{
		.compatible = "renesas,gpio-r8a7743",
		/* RZ/G1 GPIO is identical to R-Car Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7790",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7791",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7792",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7793",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7794",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7795",
		/* Gen3 GPIO is identical to Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7796",
		/* Gen3 GPIO is identical to Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,rcar-gen1-gpio",
		.data = &gpio_rcar_info_gen1,
	}, {
		.compatible = "renesas,rcar-gen2-gpio",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,rcar-gen3-gpio",
		/* Gen3 GPIO is identical to Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-rcar",
		.data = &gpio_rcar_info_gen1,
	}, {
		/* Terminator */
	},
};

MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);

static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
{
	struct device_node *np = p->dev->of_node;
	const struct gpio_rcar_info *info;
	struct of_phandle_args args;
	int ret;

	info = of_device_get_match_data(p->dev);
	p->info = *info;

	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;

	if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
		dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
			 *npins, RCAR_MAX_GPIO_PER_BANK);
		*npins = RCAR_MAX_GPIO_PER_BANK;
	}

	return 0;
}

static int gpio_rcar_probe(struct platform_device *pdev)
{
	struct gpio_rcar_priv *p;
	struct resource *irq;
	struct gpio_chip *gpio_chip;
	struct irq_chip *irq_chip;
	struct gpio_irq_chip *girq;
	struct device *dev = &pdev->dev;
	const char *name = dev_name(dev);
	unsigned int npins;
	int ret;

	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
	if (!p)
		return -ENOMEM;

	p->dev = dev;
	spin_lock_init(&p->lock);

	/* Get device configuration from DT node */
	ret = gpio_rcar_parse_dt(p, &npins);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, p);

	pm_runtime_enable(dev);

	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!irq) {
		dev_err(dev, "missing IRQ\n");
		ret = -EINVAL;
		goto err0;
	}

	p->base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(p->base)) {
		ret = PTR_ERR(p->base);
		goto err0;
	}

	gpio_chip = &p->gpio_chip;
	gpio_chip->request = gpio_rcar_request;
	gpio_chip->free = gpio_rcar_free;
	gpio_chip->get_direction = gpio_rcar_get_direction;
	gpio_chip->direction_input = gpio_rcar_direction_input;
	gpio_chip->get = gpio_rcar_get;
	gpio_chip->get_multiple = gpio_rcar_get_multiple;
	gpio_chip->direction_output = gpio_rcar_direction_output;
	gpio_chip->set = gpio_rcar_set;
	gpio_chip->set_multiple = gpio_rcar_set_multiple;
	gpio_chip->label = name;
	gpio_chip->parent = dev;
	gpio_chip->owner = THIS_MODULE;
	gpio_chip->base = -1;
	gpio_chip->ngpio = npins;

	irq_chip = &p->irq_chip;
	irq_chip->name = "gpio-rcar";
	irq_chip->parent_device = dev;
	irq_chip->irq_mask = gpio_rcar_irq_disable;
	irq_chip->irq_unmask = gpio_rcar_irq_enable;
	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
	irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;

	girq = &gpio_chip->irq;
	girq->chip = irq_chip;
	/* This will let us handle the parent IRQ in the driver */
	girq->parent_handler = NULL;
	girq->num_parents = 0;
	girq->parents = NULL;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_level_irq;

	ret = gpiochip_add_data(gpio_chip, p);
	if (ret) {
		dev_err(dev, "failed to add GPIO controller\n");
		goto err0;
	}

	p->irq_parent = irq->start;
	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
			     IRQF_SHARED, name, p)) {
		dev_err(dev, "failed to request IRQ\n");
		ret = -ENOENT;
		goto err1;
	}

	dev_info(dev, "driving %d GPIOs\n", npins);

	return 0;

err1:
	gpiochip_remove(gpio_chip);
err0:
	pm_runtime_disable(dev);
	return ret;
}

static int gpio_rcar_remove(struct platform_device *pdev)
{
	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);

	gpiochip_remove(&p->gpio_chip);

	pm_runtime_disable(&pdev->dev);
	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int gpio_rcar_suspend(struct device *dev)
{
	struct gpio_rcar_priv *p = dev_get_drvdata(dev);

	p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
	p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
	p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
	p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
	p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
	p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
	if (p->info.has_both_edge_trigger)
		p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);

	if (atomic_read(&p->wakeup_path))
		device_set_wakeup_path(dev);

	return 0;
}

static int gpio_rcar_resume(struct device *dev)
{
	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
	unsigned int offset;
	u32 mask;

	for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
		if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
			continue;

		mask = BIT(offset);
		/* I/O pin */
		if (!(p->bank_info.iointsel & mask)) {
			if (p->bank_info.inoutsel & mask)
				gpio_rcar_direction_output(
					&p->gpio_chip, offset,
					!!(p->bank_info.outdt & mask));
			else
				gpio_rcar_direction_input(&p->gpio_chip,
							  offset);
		} else {
			/* Interrupt pin */
			gpio_rcar_config_interrupt_input_mode(
				p,
				offset,
				!(p->bank_info.posneg & mask),
				!(p->bank_info.edglevel & mask),
				!!(p->bank_info.bothedge & mask));

			if (p->bank_info.intmsk & mask)
				gpio_rcar_write(p, MSKCLR, mask);
		}
	}

	return 0;
}
#endif /* CONFIG_PM_SLEEP*/

static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);

static struct platform_driver gpio_rcar_device_driver = {
	.probe		= gpio_rcar_probe,
	.remove		= gpio_rcar_remove,
	.driver		= {
		.name	= "gpio_rcar",
		.pm     = &gpio_rcar_pm_ops,
		.of_match_table = of_match_ptr(gpio_rcar_of_table),
	}
};

module_platform_driver(gpio_rcar_device_driver);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
8b37eb74	1	// SPDX-License-Identifier: GPL-2.0
119f5e44 MD	2	/*
	3	* Renesas R-Car GPIO Support
	4	*
1fd2b49d	5	* Copyright (C) 2014 Renesas Electronics Corporation
119f5e44	6	* Copyright (C) 2013 Magnus Damm
119f5e44 MD	7	*/
	8
	9	#include <linux/err.h>
4b1d8007	10	#include <linux/gpio/driver.h>
119f5e44 MD	11	#include <linux/init.h>
	12	#include <linux/interrupt.h>
	13	#include <linux/io.h>
	14	#include <linux/ioport.h>
	15	#include <linux/irq.h>
119f5e44	16	#include <linux/module.h>
bd0bf468	17	#include <linux/of.h>
f9f2a6fe	18	#include <linux/of_device.h>
dc3465a9	19	#include <linux/pinctrl/consumer.h>
119f5e44	20	#include <linux/platform_device.h>
df0c6c80	21	#include <linux/pm_runtime.h>
119f5e44 MD	22	#include <linux/spinlock.h>
	23	#include <linux/slab.h>
	24
51750fb1 HD	25	struct gpio_rcar_bank_info {
	26	u32 iointsel;
	27	u32 inoutsel;
	28	u32 outdt;
	29	u32 posneg;
	30	u32 edglevel;
	31	u32 bothedge;
	32	u32 intmsk;
	33	};
	34
208c80f1 GU	35	struct gpio_rcar_info {
	36	bool has_outdtsel;
	37	bool has_both_edge_trigger;
	38	};
	39
119f5e44 MD	40	struct gpio_rcar_priv {
	41	void __iomem *base;
	42	spinlock_t lock;
a53f7953	43	struct device *dev;
119f5e44 MD	44	struct gpio_chip gpio_chip;
119f5e44 MD	45	struct irq_chip irq_chip;
8b092be9	46	unsigned int irq_parent;
9ac79ba9	47	atomic_t wakeup_path;
208c80f1	48	struct gpio_rcar_info info;
51750fb1	49	struct gpio_rcar_bank_info bank_info;
119f5e44 MD	50	};
119f5e44 MD	51
677d7d61 GU	52	#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
	53	#define INOUTSEL 0x04 /* General Input/Output Switching Register */
	54	#define OUTDT 0x08 /* General Output Register */
	55	#define INDT 0x0c /* General Input Register */
	56	#define INTDT 0x10 /* Interrupt Display Register */
	57	#define INTCLR 0x14 /* Interrupt Clear Register */
	58	#define INTMSK 0x18 /* Interrupt Mask Register */
	59	#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
	60	#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
	61	#define EDGLEVEL 0x24 /* Edge/level Select Register */
	62	#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
	63	#define OUTDTSEL 0x40 /* Output Data Select Register */
	64	#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
119f5e44	65
159f8a02 LP	66	#define RCAR_MAX_GPIO_PER_BANK 32
159f8a02 LP	67
119f5e44 MD	68	static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
	69	{
	70	return ioread32(p->base + offs);
	71	}
	72
	73	static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
	74	u32 value)
	75	{
	76	iowrite32(value, p->base + offs);
	77	}
	78
	79	static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
	80	int bit, bool value)
	81	{
	82	u32 tmp = gpio_rcar_read(p, offs);
	83
	84	if (value)
	85	tmp \|= BIT(bit);
	86	else
	87	tmp &= ~BIT(bit);
	88
	89	gpio_rcar_write(p, offs, tmp);
	90	}
	91
	92	static void gpio_rcar_irq_disable(struct irq_data *d)
	93	{
c7f3c5d3	94	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	95	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	96
	97	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
	98	}
	99
	100	static void gpio_rcar_irq_enable(struct irq_data *d)
	101	{
c7f3c5d3	102	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	103	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	104
	105	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
	106	}
	107
	108	static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
	109	unsigned int hwirq,
	110	bool active_high_rising_edge,
7e1092b5 SH	111	bool level_trigger,
7e1092b5 SH	112	bool both)
119f5e44 MD	113	{
	114	unsigned long flags;
	115
	116	/* follow steps in the GPIO documentation for
	117	* "Setting Edge-Sensitive Interrupt Input Mode" and
	118	* "Setting Level-Sensitive Interrupt Input Mode"
	119	*/
	120
	121	spin_lock_irqsave(&p->lock, flags);
	122
b36368f6	123	/* Configure positive or negative logic in POSNEG */
119f5e44 MD	124	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
	125
	126	/* Configure edge or level trigger in EDGLEVEL */
	127	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
	128
7e1092b5	129	/* Select one edge or both edges in BOTHEDGE */
208c80f1	130	if (p->info.has_both_edge_trigger)
7e1092b5 SH	131	gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
7e1092b5 SH	132
119f5e44 MD	133	/* Select "Interrupt Input Mode" in IOINTSEL */
	134	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
	135
	136	/* Write INTCLR in case of edge trigger */
	137	if (!level_trigger)
	138	gpio_rcar_write(p, INTCLR, BIT(hwirq));
	139
	140	spin_unlock_irqrestore(&p->lock, flags);
	141	}
	142
	143	static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
	144	{
c7f3c5d3	145	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	146	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	147	unsigned int hwirq = irqd_to_hwirq(d);
119f5e44 MD	148
a53f7953	149	dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
119f5e44 MD	150
	151	switch (type & IRQ_TYPE_SENSE_MASK) {
	152	case IRQ_TYPE_LEVEL_HIGH:
7e1092b5 SH	153	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
7e1092b5 SH	154	false);
119f5e44 MD	155	break;
119f5e44 MD	156	case IRQ_TYPE_LEVEL_LOW:
7e1092b5 SH	157	gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
7e1092b5 SH	158	false);
119f5e44 MD	159	break;
119f5e44 MD	160	case IRQ_TYPE_EDGE_RISING:
7e1092b5 SH	161	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
7e1092b5 SH	162	false);
119f5e44 MD	163	break;
119f5e44 MD	164	case IRQ_TYPE_EDGE_FALLING:
7e1092b5 SH	165	gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
	166	false);
	167	break;
	168	case IRQ_TYPE_EDGE_BOTH:
208c80f1	169	if (!p->info.has_both_edge_trigger)
7e1092b5 SH	170	return -EINVAL;
	171	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
	172	true);
119f5e44 MD	173	break;
	174	default:
	175	return -EINVAL;
	176	}
	177	return 0;
	178	}
	179
ab82fa7d GU	180	static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
	181	{
	182	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	183	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
501ef0f9 GU	184	int error;
	185
	186	if (p->irq_parent) {
	187	error = irq_set_irq_wake(p->irq_parent, on);
	188	if (error) {
a53f7953	189	dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
501ef0f9 GU	190	p->irq_parent);
	191	p->irq_parent = 0;
	192	}
	193	}
ab82fa7d	194
ab82fa7d	195	if (on)
9ac79ba9	196	atomic_inc(&p->wakeup_path);
ab82fa7d	197	else
9ac79ba9	198	atomic_dec(&p->wakeup_path);
ab82fa7d GU	199
	200	return 0;
	201	}
	202
119f5e44 MD	203	static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
	204	{
	205	struct gpio_rcar_priv *p = dev_id;
	206	u32 pending;
	207	unsigned int offset, irqs_handled = 0;
	208
8808b64d VB	209	while ((pending = gpio_rcar_read(p, INTDT) &
8808b64d VB	210	gpio_rcar_read(p, INTMSK))) {
119f5e44 MD	211	offset = __ffs(pending);
119f5e44 MD	212	gpio_rcar_write(p, INTCLR, BIT(offset));
f0fbe7bc	213	generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
c7f3c5d3	214	offset));
119f5e44 MD	215	irqs_handled++;
	216	}
	217
	218	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
	219	}
	220
119f5e44 MD	221	static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
	222	unsigned int gpio,
	223	bool output)
	224	{
c7b6f457	225	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
119f5e44 MD	226	unsigned long flags;
	227
	228	/* follow steps in the GPIO documentation for
	229	* "Setting General Output Mode" and
	230	* "Setting General Input Mode"
	231	*/
	232
	233	spin_lock_irqsave(&p->lock, flags);
	234
b36368f6	235	/* Configure positive logic in POSNEG */
119f5e44 MD	236	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
	237
	238	/* Select "General Input/Output Mode" in IOINTSEL */
	239	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
	240
	241	/* Select Input Mode or Output Mode in INOUTSEL */
	242	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
	243
3ae4f3aa	244	/* Select General Output Register to output data in OUTDTSEL */
208c80f1	245	if (p->info.has_outdtsel && output)
3ae4f3aa VZ	246	gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
3ae4f3aa VZ	247
119f5e44 MD	248	spin_unlock_irqrestore(&p->lock, flags);
	249	}
	250
dc3465a9 LP	251	static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
dc3465a9 LP	252	{
2d65472b GU	253	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	254	int error;
	255
a53f7953	256	error = pm_runtime_get_sync(p->dev);
6f8cd246 DL	257	if (error < 0) {
6f8cd246 DL	258	pm_runtime_put(p->dev);
2d65472b	259	return error;
6f8cd246	260	}
2d65472b	261
a9a1d2a7	262	error = pinctrl_gpio_request(chip->base + offset);
2d65472b	263	if (error)
a53f7953	264	pm_runtime_put(p->dev);
2d65472b GU	265
2d65472b GU	266	return error;
dc3465a9 LP	267	}
	268
	269	static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
	270	{
2d65472b GU	271	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
2d65472b GU	272
a9a1d2a7	273	pinctrl_gpio_free(chip->base + offset);
dc3465a9	274
ce0e2c60 LW	275	/*
ce0e2c60 LW	276	* Set the GPIO as an input to ensure that the next GPIO request won't
dc3465a9 LP	277	* drive the GPIO pin as an output.
	278	*/
	279	gpio_rcar_config_general_input_output_mode(chip, offset, false);
2d65472b	280
a53f7953	281	pm_runtime_put(p->dev);
dc3465a9 LP	282	}
dc3465a9 LP	283
ad817297 GU	284	static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
	285	{
	286	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	287
e42615ec MV	288	if (gpio_rcar_read(p, INOUTSEL) & BIT(offset))
	289	return GPIO_LINE_DIRECTION_OUT;
	290
	291	return GPIO_LINE_DIRECTION_IN;
ad817297 GU	292	}
ad817297 GU	293
119f5e44 MD	294	static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
	295	{
	296	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	297	return 0;
	298	}
	299
	300	static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
	301	{
714d3a29	302	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
ae9550f6 MD	303	u32 bit = BIT(offset);
	304
	305	/* testing on r8a7790 shows that INDT does not show correct pin state
	306	* when configured as output, so use OUTDT in case of output pins */
714d3a29 GU	307	if (gpio_rcar_read(p, INOUTSEL) & bit)
714d3a29 GU	308	return !!(gpio_rcar_read(p, OUTDT) & bit);
ae9550f6	309	else
714d3a29	310	return !!(gpio_rcar_read(p, INDT) & bit);
119f5e44 MD	311	}
119f5e44 MD	312
183245c4 GU	313	static int gpio_rcar_get_multiple(struct gpio_chip chip, unsigned long mask,
	314	unsigned long *bits)
	315	{
	316	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	317	u32 bankmask, outputs, m, val = 0;
	318	unsigned long flags;
	319
	320	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
	321	if (chip->valid_mask)
	322	bankmask &= chip->valid_mask[0];
	323
	324	if (!bankmask)
	325	return 0;
	326
	327	spin_lock_irqsave(&p->lock, flags);
	328	outputs = gpio_rcar_read(p, INOUTSEL);
	329	m = outputs & bankmask;
	330	if (m)
	331	val \|= gpio_rcar_read(p, OUTDT) & m;
	332
	333	m = ~outputs & bankmask;
	334	if (m)
	335	val \|= gpio_rcar_read(p, INDT) & m;
	336	spin_unlock_irqrestore(&p->lock, flags);
	337
	338	bits[0] = val;
	339	return 0;
	340	}
	341
119f5e44 MD	342	static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
119f5e44 MD	343	{
c7b6f457	344	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
119f5e44 MD	345	unsigned long flags;
	346
	347	spin_lock_irqsave(&p->lock, flags);
	348	gpio_rcar_modify_bit(p, OUTDT, offset, value);
	349	spin_unlock_irqrestore(&p->lock, flags);
	350	}
	351
dbb763b8 GU	352	static void gpio_rcar_set_multiple(struct gpio_chip chip, unsigned long mask,
	353	unsigned long *bits)
	354	{
	355	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	356	unsigned long flags;
	357	u32 val, bankmask;
	358
	359	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
496069b8 BD	360	if (chip->valid_mask)
	361	bankmask &= chip->valid_mask[0];
	362
dbb763b8 GU	363	if (!bankmask)
	364	return;
	365
	366	spin_lock_irqsave(&p->lock, flags);
	367	val = gpio_rcar_read(p, OUTDT);
	368	val &= ~bankmask;
	369	val \|= (bankmask & bits[0]);
	370	gpio_rcar_write(p, OUTDT, val);
	371	spin_unlock_irqrestore(&p->lock, flags);
	372	}
	373
119f5e44 MD	374	static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
	375	int value)
	376	{
	377	/* write GPIO value to output before selecting output mode of pin */
	378	gpio_rcar_set(chip, offset, value);
	379	gpio_rcar_config_general_input_output_mode(chip, offset, true);
	380	return 0;
	381	}
	382
1fd2b49d	383	static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
3ae4f3aa	384	.has_outdtsel = false,
1fd2b49d HN	385	.has_both_edge_trigger = false,
	386	};
	387
	388	static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
3ae4f3aa	389	.has_outdtsel = true,
1fd2b49d HN	390	.has_both_edge_trigger = true,
	391	};
	392
850dfe17 LP	393	static const struct of_device_id gpio_rcar_of_table[] = {
850dfe17 LP	394	{
85bb4646 BD	395	.compatible = "renesas,gpio-r8a7743",
	396	/* RZ/G1 GPIO is identical to R-Car Gen2. */
	397	.data = &gpio_rcar_info_gen2,
	398	}, {
850dfe17	399	.compatible = "renesas,gpio-r8a7790",
1fd2b49d	400	.data = &gpio_rcar_info_gen2,
850dfe17 LP	401	}, {
850dfe17 LP	402	.compatible = "renesas,gpio-r8a7791",
1fd2b49d	403	.data = &gpio_rcar_info_gen2,
e79c5830 SS	404	}, {
	405	.compatible = "renesas,gpio-r8a7792",
	406	.data = &gpio_rcar_info_gen2,
1fd2b49d HN	407	}, {
	408	.compatible = "renesas,gpio-r8a7793",
	409	.data = &gpio_rcar_info_gen2,
	410	}, {
	411	.compatible = "renesas,gpio-r8a7794",
	412	.data = &gpio_rcar_info_gen2,
8cd14702 UH	413	}, {
	414	.compatible = "renesas,gpio-r8a7795",
	415	/* Gen3 GPIO is identical to Gen2. */
	416	.data = &gpio_rcar_info_gen2,
5d2f1d6e SH	417	}, {
	418	.compatible = "renesas,gpio-r8a7796",
	419	/* Gen3 GPIO is identical to Gen2. */
	420	.data = &gpio_rcar_info_gen2,
dbd1dad2 SH	421	}, {
	422	.compatible = "renesas,rcar-gen1-gpio",
	423	.data = &gpio_rcar_info_gen1,
	424	}, {
	425	.compatible = "renesas,rcar-gen2-gpio",
	426	.data = &gpio_rcar_info_gen2,
	427	}, {
	428	.compatible = "renesas,rcar-gen3-gpio",
	429	/* Gen3 GPIO is identical to Gen2. */
	430	.data = &gpio_rcar_info_gen2,
850dfe17 LP	431	}, {
850dfe17 LP	432	.compatible = "renesas,gpio-rcar",
1fd2b49d	433	.data = &gpio_rcar_info_gen1,
850dfe17 LP	434	}, {
	435	/* Terminator */
	436	},
	437	};
	438
	439	MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
	440
8b092be9	441	static int gpio_rcar_parse_dt(struct gpio_rcar_priv p, unsigned int npins)
159f8a02	442	{
a53f7953	443	struct device_node *np = p->dev->of_node;
8b092be9	444	const struct gpio_rcar_info *info;
159f8a02 LP	445	struct of_phandle_args args;
159f8a02 LP	446	int ret;
159f8a02	447
a53f7953	448	info = of_device_get_match_data(p->dev);
208c80f1	449	p->info = *info;
850dfe17	450
8b092be9 GU	451	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
8b092be9 GU	452	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
850dfe17	453
8b092be9	454	if (npins == 0 \|\| npins > RCAR_MAX_GPIO_PER_BANK) {
a53f7953 VZ	455	dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
a53f7953 VZ	456	*npins, RCAR_MAX_GPIO_PER_BANK);
8b092be9	457	*npins = RCAR_MAX_GPIO_PER_BANK;
159f8a02	458	}
850dfe17 LP	459
850dfe17 LP	460	return 0;
159f8a02 LP	461	}
159f8a02 LP	462
119f5e44 MD	463	static int gpio_rcar_probe(struct platform_device *pdev)
119f5e44 MD	464	{
119f5e44	465	struct gpio_rcar_priv *p;
ecbf7c2e	466	struct resource *irq;
119f5e44 MD	467	struct gpio_chip *gpio_chip;
119f5e44 MD	468	struct irq_chip *irq_chip;
b470cef1	469	struct gpio_irq_chip *girq;
b22978fc GU	470	struct device *dev = &pdev->dev;
b22978fc GU	471	const char *name = dev_name(dev);
8b092be9	472	unsigned int npins;
119f5e44 MD	473	int ret;
119f5e44 MD	474
b22978fc	475	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
7d82bf34 GU	476	if (!p)
7d82bf34 GU	477	return -ENOMEM;
119f5e44	478
a53f7953	479	p->dev = dev;
119f5e44 MD	480	spin_lock_init(&p->lock);
119f5e44 MD	481
8b092be9 GU	482	/* Get device configuration from DT node */
8b092be9 GU	483	ret = gpio_rcar_parse_dt(p, &npins);
850dfe17 LP	484	if (ret < 0)
850dfe17 LP	485	return ret;
159f8a02 LP	486
	487	platform_set_drvdata(pdev, p);
	488
df0c6c80	489	pm_runtime_enable(dev);
df0c6c80	490
119f5e44	491	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
5a24d4b6 SS	492	if (!irq) {
5a24d4b6 SS	493	dev_err(dev, "missing IRQ\n");
119f5e44 MD	494	ret = -EINVAL;
	495	goto err0;
	496	}
	497
ecbf7c2e	498	p->base = devm_platform_ioremap_resource(pdev, 0);
5a24d4b6 SS	499	if (IS_ERR(p->base)) {
5a24d4b6 SS	500	ret = PTR_ERR(p->base);
119f5e44 MD	501	goto err0;
	502	}
	503
	504	gpio_chip = &p->gpio_chip;
dc3465a9 LP	505	gpio_chip->request = gpio_rcar_request;
dc3465a9 LP	506	gpio_chip->free = gpio_rcar_free;
ad817297	507	gpio_chip->get_direction = gpio_rcar_get_direction;
119f5e44 MD	508	gpio_chip->direction_input = gpio_rcar_direction_input;
119f5e44 MD	509	gpio_chip->get = gpio_rcar_get;
183245c4	510	gpio_chip->get_multiple = gpio_rcar_get_multiple;
119f5e44 MD	511	gpio_chip->direction_output = gpio_rcar_direction_output;
119f5e44 MD	512	gpio_chip->set = gpio_rcar_set;
dbb763b8	513	gpio_chip->set_multiple = gpio_rcar_set_multiple;
119f5e44	514	gpio_chip->label = name;
58383c78	515	gpio_chip->parent = dev;
119f5e44	516	gpio_chip->owner = THIS_MODULE;
8b092be9 GU	517	gpio_chip->base = -1;
8b092be9 GU	518	gpio_chip->ngpio = npins;
119f5e44 MD	519
119f5e44 MD	520	irq_chip = &p->irq_chip;
f932a686	521	irq_chip->name = "gpio-rcar";
47bd38a3	522	irq_chip->parent_device = dev;
119f5e44 MD	523	irq_chip->irq_mask = gpio_rcar_irq_disable;
119f5e44 MD	524	irq_chip->irq_unmask = gpio_rcar_irq_enable;
119f5e44	525	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
ab82fa7d	526	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
b183cab7	527	irq_chip->flags = IRQCHIP_SET_TYPE_MASKED \| IRQCHIP_MASK_ON_SUSPEND;
119f5e44	528
b470cef1 LW	529	girq = &gpio_chip->irq;
	530	girq->chip = irq_chip;
	531	/* This will let us handle the parent IRQ in the driver */
	532	girq->parent_handler = NULL;
	533	girq->num_parents = 0;
	534	girq->parents = NULL;
	535	girq->default_type = IRQ_TYPE_NONE;
	536	girq->handler = handle_level_irq;
	537
c7b6f457	538	ret = gpiochip_add_data(gpio_chip, p);
c7f3c5d3 GU	539	if (ret) {
c7f3c5d3 GU	540	dev_err(dev, "failed to add GPIO controller\n");
0c8aab8e	541	goto err0;
119f5e44 MD	542	}
119f5e44 MD	543
ab82fa7d	544	p->irq_parent = irq->start;
b22978fc GU	545	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
	546	IRQF_SHARED, name, p)) {
	547	dev_err(dev, "failed to request IRQ\n");
119f5e44 MD	548	ret = -ENOENT;
	549	goto err1;
	550	}
	551
8b092be9	552	dev_info(dev, "driving %d GPIOs\n", npins);
dc3465a9	553
119f5e44 MD	554	return 0;
	555
	556	err1:
4d84b9e4	557	gpiochip_remove(gpio_chip);
119f5e44	558	err0:
df0c6c80	559	pm_runtime_disable(dev);
119f5e44 MD	560	return ret;
	561	}
	562
	563	static int gpio_rcar_remove(struct platform_device *pdev)
	564	{
	565	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
119f5e44	566
9f5132ae	567	gpiochip_remove(&p->gpio_chip);
119f5e44	568
df0c6c80	569	pm_runtime_disable(&pdev->dev);
119f5e44 MD	570	return 0;
	571	}
	572
51750fb1 HD	573	#ifdef CONFIG_PM_SLEEP
	574	static int gpio_rcar_suspend(struct device *dev)
	575	{
	576	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
	577
	578	p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
	579	p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
	580	p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
	581	p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
	582	p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
	583	p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
208c80f1	584	if (p->info.has_both_edge_trigger)
51750fb1 HD	585	p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
51750fb1 HD	586
9ac79ba9 GU	587	if (atomic_read(&p->wakeup_path))
	588	device_set_wakeup_path(dev);
	589
51750fb1 HD	590	return 0;
	591	}
	592
	593	static int gpio_rcar_resume(struct device *dev)
	594	{
	595	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
	596	unsigned int offset;
	597	u32 mask;
	598
	599	for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
496069b8 BD	600	if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
	601	continue;
	602
51750fb1 HD	603	mask = BIT(offset);
	604	/* I/O pin */
	605	if (!(p->bank_info.iointsel & mask)) {
	606	if (p->bank_info.inoutsel & mask)
	607	gpio_rcar_direction_output(
	608	&p->gpio_chip, offset,
	609	!!(p->bank_info.outdt & mask));
	610	else
	611	gpio_rcar_direction_input(&p->gpio_chip,
	612	offset);
	613	} else {
	614	/* Interrupt pin */
	615	gpio_rcar_config_interrupt_input_mode(
	616	p,
	617	offset,
	618	!(p->bank_info.posneg & mask),
	619	!(p->bank_info.edglevel & mask),
	620	!!(p->bank_info.bothedge & mask));
	621
	622	if (p->bank_info.intmsk & mask)
	623	gpio_rcar_write(p, MSKCLR, mask);
	624	}
	625	}
	626
	627	return 0;
	628	}
	629	#endif /* CONFIG_PM_SLEEP*/
	630
	631	static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
	632
119f5e44 MD	633	static struct platform_driver gpio_rcar_device_driver = {
	634	.probe = gpio_rcar_probe,
	635	.remove = gpio_rcar_remove,
	636	.driver = {
	637	.name = "gpio_rcar",
51750fb1	638	.pm = &gpio_rcar_pm_ops,
159f8a02	639	.of_match_table = of_match_ptr(gpio_rcar_of_table),
119f5e44 MD	640	}
	641	};
	642
	643	module_platform_driver(gpio_rcar_device_driver);
	644
	645	MODULE_AUTHOR("Magnus Damm");
	646	MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
	647	MODULE_LICENSE("GPL v2");