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119f5e44 MD |
1 | /* |
2 | * Renesas R-Car GPIO Support | |
3 | * | |
4 | * Copyright (C) 2013 Magnus Damm | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/err.h> | |
17 | #include <linux/gpio.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/io.h> | |
21 | #include <linux/ioport.h> | |
22 | #include <linux/irq.h> | |
23 | #include <linux/irqdomain.h> | |
24 | #include <linux/module.h> | |
bd0bf468 | 25 | #include <linux/of.h> |
dc3465a9 | 26 | #include <linux/pinctrl/consumer.h> |
119f5e44 MD |
27 | #include <linux/platform_data/gpio-rcar.h> |
28 | #include <linux/platform_device.h> | |
29 | #include <linux/spinlock.h> | |
30 | #include <linux/slab.h> | |
31 | ||
32 | struct gpio_rcar_priv { | |
33 | void __iomem *base; | |
34 | spinlock_t lock; | |
35 | struct gpio_rcar_config config; | |
36 | struct platform_device *pdev; | |
37 | struct gpio_chip gpio_chip; | |
38 | struct irq_chip irq_chip; | |
39 | struct irq_domain *irq_domain; | |
40 | }; | |
41 | ||
42 | #define IOINTSEL 0x00 | |
43 | #define INOUTSEL 0x04 | |
44 | #define OUTDT 0x08 | |
45 | #define INDT 0x0c | |
46 | #define INTDT 0x10 | |
47 | #define INTCLR 0x14 | |
48 | #define INTMSK 0x18 | |
49 | #define MSKCLR 0x1c | |
50 | #define POSNEG 0x20 | |
51 | #define EDGLEVEL 0x24 | |
52 | #define FILONOFF 0x28 | |
7e1092b5 | 53 | #define BOTHEDGE 0x4c |
119f5e44 | 54 | |
159f8a02 LP |
55 | #define RCAR_MAX_GPIO_PER_BANK 32 |
56 | ||
119f5e44 MD |
57 | static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) |
58 | { | |
59 | return ioread32(p->base + offs); | |
60 | } | |
61 | ||
62 | static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs, | |
63 | u32 value) | |
64 | { | |
65 | iowrite32(value, p->base + offs); | |
66 | } | |
67 | ||
68 | static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs, | |
69 | int bit, bool value) | |
70 | { | |
71 | u32 tmp = gpio_rcar_read(p, offs); | |
72 | ||
73 | if (value) | |
74 | tmp |= BIT(bit); | |
75 | else | |
76 | tmp &= ~BIT(bit); | |
77 | ||
78 | gpio_rcar_write(p, offs, tmp); | |
79 | } | |
80 | ||
81 | static void gpio_rcar_irq_disable(struct irq_data *d) | |
82 | { | |
83 | struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); | |
84 | ||
85 | gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d))); | |
86 | } | |
87 | ||
88 | static void gpio_rcar_irq_enable(struct irq_data *d) | |
89 | { | |
90 | struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); | |
91 | ||
92 | gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); | |
93 | } | |
94 | ||
95 | static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, | |
96 | unsigned int hwirq, | |
97 | bool active_high_rising_edge, | |
7e1092b5 SH |
98 | bool level_trigger, |
99 | bool both) | |
119f5e44 MD |
100 | { |
101 | unsigned long flags; | |
102 | ||
103 | /* follow steps in the GPIO documentation for | |
104 | * "Setting Edge-Sensitive Interrupt Input Mode" and | |
105 | * "Setting Level-Sensitive Interrupt Input Mode" | |
106 | */ | |
107 | ||
108 | spin_lock_irqsave(&p->lock, flags); | |
109 | ||
110 | /* Configure postive or negative logic in POSNEG */ | |
111 | gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); | |
112 | ||
113 | /* Configure edge or level trigger in EDGLEVEL */ | |
114 | gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); | |
115 | ||
7e1092b5 SH |
116 | /* Select one edge or both edges in BOTHEDGE */ |
117 | if (p->config.has_both_edge_trigger) | |
118 | gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both); | |
119 | ||
119f5e44 MD |
120 | /* Select "Interrupt Input Mode" in IOINTSEL */ |
121 | gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); | |
122 | ||
123 | /* Write INTCLR in case of edge trigger */ | |
124 | if (!level_trigger) | |
125 | gpio_rcar_write(p, INTCLR, BIT(hwirq)); | |
126 | ||
127 | spin_unlock_irqrestore(&p->lock, flags); | |
128 | } | |
129 | ||
130 | static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) | |
131 | { | |
132 | struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d); | |
133 | unsigned int hwirq = irqd_to_hwirq(d); | |
134 | ||
135 | dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type); | |
136 | ||
137 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
138 | case IRQ_TYPE_LEVEL_HIGH: | |
7e1092b5 SH |
139 | gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true, |
140 | false); | |
119f5e44 MD |
141 | break; |
142 | case IRQ_TYPE_LEVEL_LOW: | |
7e1092b5 SH |
143 | gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true, |
144 | false); | |
119f5e44 MD |
145 | break; |
146 | case IRQ_TYPE_EDGE_RISING: | |
7e1092b5 SH |
147 | gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, |
148 | false); | |
119f5e44 MD |
149 | break; |
150 | case IRQ_TYPE_EDGE_FALLING: | |
7e1092b5 SH |
151 | gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false, |
152 | false); | |
153 | break; | |
154 | case IRQ_TYPE_EDGE_BOTH: | |
155 | if (!p->config.has_both_edge_trigger) | |
156 | return -EINVAL; | |
157 | gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, | |
158 | true); | |
119f5e44 MD |
159 | break; |
160 | default: | |
161 | return -EINVAL; | |
162 | } | |
163 | return 0; | |
164 | } | |
165 | ||
166 | static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) | |
167 | { | |
168 | struct gpio_rcar_priv *p = dev_id; | |
169 | u32 pending; | |
170 | unsigned int offset, irqs_handled = 0; | |
171 | ||
8808b64d VB |
172 | while ((pending = gpio_rcar_read(p, INTDT) & |
173 | gpio_rcar_read(p, INTMSK))) { | |
119f5e44 MD |
174 | offset = __ffs(pending); |
175 | gpio_rcar_write(p, INTCLR, BIT(offset)); | |
176 | generic_handle_irq(irq_find_mapping(p->irq_domain, offset)); | |
177 | irqs_handled++; | |
178 | } | |
179 | ||
180 | return irqs_handled ? IRQ_HANDLED : IRQ_NONE; | |
181 | } | |
182 | ||
183 | static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip) | |
184 | { | |
185 | return container_of(chip, struct gpio_rcar_priv, gpio_chip); | |
186 | } | |
187 | ||
188 | static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, | |
189 | unsigned int gpio, | |
190 | bool output) | |
191 | { | |
192 | struct gpio_rcar_priv *p = gpio_to_priv(chip); | |
193 | unsigned long flags; | |
194 | ||
195 | /* follow steps in the GPIO documentation for | |
196 | * "Setting General Output Mode" and | |
197 | * "Setting General Input Mode" | |
198 | */ | |
199 | ||
200 | spin_lock_irqsave(&p->lock, flags); | |
201 | ||
202 | /* Configure postive logic in POSNEG */ | |
203 | gpio_rcar_modify_bit(p, POSNEG, gpio, false); | |
204 | ||
205 | /* Select "General Input/Output Mode" in IOINTSEL */ | |
206 | gpio_rcar_modify_bit(p, IOINTSEL, gpio, false); | |
207 | ||
208 | /* Select Input Mode or Output Mode in INOUTSEL */ | |
209 | gpio_rcar_modify_bit(p, INOUTSEL, gpio, output); | |
210 | ||
211 | spin_unlock_irqrestore(&p->lock, flags); | |
212 | } | |
213 | ||
dc3465a9 LP |
214 | static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) |
215 | { | |
216 | return pinctrl_request_gpio(chip->base + offset); | |
217 | } | |
218 | ||
219 | static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) | |
220 | { | |
221 | pinctrl_free_gpio(chip->base + offset); | |
222 | ||
223 | /* Set the GPIO as an input to ensure that the next GPIO request won't | |
224 | * drive the GPIO pin as an output. | |
225 | */ | |
226 | gpio_rcar_config_general_input_output_mode(chip, offset, false); | |
227 | } | |
228 | ||
119f5e44 MD |
229 | static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) |
230 | { | |
231 | gpio_rcar_config_general_input_output_mode(chip, offset, false); | |
232 | return 0; | |
233 | } | |
234 | ||
235 | static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) | |
236 | { | |
ae9550f6 MD |
237 | u32 bit = BIT(offset); |
238 | ||
239 | /* testing on r8a7790 shows that INDT does not show correct pin state | |
240 | * when configured as output, so use OUTDT in case of output pins */ | |
241 | if (gpio_rcar_read(gpio_to_priv(chip), INOUTSEL) & bit) | |
242 | return (int)(gpio_rcar_read(gpio_to_priv(chip), OUTDT) & bit); | |
243 | else | |
244 | return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & bit); | |
119f5e44 MD |
245 | } |
246 | ||
247 | static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value) | |
248 | { | |
249 | struct gpio_rcar_priv *p = gpio_to_priv(chip); | |
250 | unsigned long flags; | |
251 | ||
252 | spin_lock_irqsave(&p->lock, flags); | |
253 | gpio_rcar_modify_bit(p, OUTDT, offset, value); | |
254 | spin_unlock_irqrestore(&p->lock, flags); | |
255 | } | |
256 | ||
257 | static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset, | |
258 | int value) | |
259 | { | |
260 | /* write GPIO value to output before selecting output mode of pin */ | |
261 | gpio_rcar_set(chip, offset, value); | |
262 | gpio_rcar_config_general_input_output_mode(chip, offset, true); | |
263 | return 0; | |
264 | } | |
265 | ||
266 | static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset) | |
267 | { | |
268 | return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset); | |
269 | } | |
270 | ||
c0d6c1ad LW |
271 | static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int irq, |
272 | irq_hw_number_t hwirq) | |
119f5e44 MD |
273 | { |
274 | struct gpio_rcar_priv *p = h->host_data; | |
275 | ||
c0d6c1ad | 276 | dev_dbg(&p->pdev->dev, "map hw irq = %d, irq = %d\n", (int)hwirq, irq); |
119f5e44 | 277 | |
c0d6c1ad LW |
278 | irq_set_chip_data(irq, h->host_data); |
279 | irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq); | |
280 | set_irq_flags(irq, IRQF_VALID); /* kill me now */ | |
119f5e44 MD |
281 | return 0; |
282 | } | |
283 | ||
284 | static struct irq_domain_ops gpio_rcar_irq_domain_ops = { | |
285 | .map = gpio_rcar_irq_domain_map, | |
286 | }; | |
287 | ||
159f8a02 LP |
288 | static void gpio_rcar_parse_pdata(struct gpio_rcar_priv *p) |
289 | { | |
e56aee18 | 290 | struct gpio_rcar_config *pdata = dev_get_platdata(&p->pdev->dev); |
159f8a02 LP |
291 | struct device_node *np = p->pdev->dev.of_node; |
292 | struct of_phandle_args args; | |
293 | int ret; | |
159f8a02 | 294 | |
e305062e | 295 | if (pdata) { |
159f8a02 | 296 | p->config = *pdata; |
e305062e | 297 | } else if (IS_ENABLED(CONFIG_OF) && np) { |
01eb2d18 LP |
298 | ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, |
299 | &args); | |
300 | p->config.number_of_pins = ret == 0 ? args.args[2] | |
159f8a02 LP |
301 | : RCAR_MAX_GPIO_PER_BANK; |
302 | p->config.gpio_base = -1; | |
303 | } | |
159f8a02 LP |
304 | |
305 | if (p->config.number_of_pins == 0 || | |
306 | p->config.number_of_pins > RCAR_MAX_GPIO_PER_BANK) { | |
307 | dev_warn(&p->pdev->dev, | |
308 | "Invalid number of gpio lines %u, using %u\n", | |
309 | p->config.number_of_pins, RCAR_MAX_GPIO_PER_BANK); | |
310 | p->config.number_of_pins = RCAR_MAX_GPIO_PER_BANK; | |
311 | } | |
312 | } | |
313 | ||
119f5e44 MD |
314 | static int gpio_rcar_probe(struct platform_device *pdev) |
315 | { | |
119f5e44 MD |
316 | struct gpio_rcar_priv *p; |
317 | struct resource *io, *irq; | |
318 | struct gpio_chip *gpio_chip; | |
319 | struct irq_chip *irq_chip; | |
320 | const char *name = dev_name(&pdev->dev); | |
321 | int ret; | |
322 | ||
323 | p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); | |
324 | if (!p) { | |
325 | dev_err(&pdev->dev, "failed to allocate driver data\n"); | |
326 | ret = -ENOMEM; | |
327 | goto err0; | |
328 | } | |
329 | ||
119f5e44 | 330 | p->pdev = pdev; |
119f5e44 MD |
331 | spin_lock_init(&p->lock); |
332 | ||
159f8a02 LP |
333 | /* Get device configuration from DT node or platform data. */ |
334 | gpio_rcar_parse_pdata(p); | |
335 | ||
336 | platform_set_drvdata(pdev, p); | |
337 | ||
119f5e44 MD |
338 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
339 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
340 | ||
341 | if (!io || !irq) { | |
342 | dev_err(&pdev->dev, "missing IRQ or IOMEM\n"); | |
343 | ret = -EINVAL; | |
344 | goto err0; | |
345 | } | |
346 | ||
347 | p->base = devm_ioremap_nocache(&pdev->dev, io->start, | |
348 | resource_size(io)); | |
349 | if (!p->base) { | |
350 | dev_err(&pdev->dev, "failed to remap I/O memory\n"); | |
351 | ret = -ENXIO; | |
352 | goto err0; | |
353 | } | |
354 | ||
355 | gpio_chip = &p->gpio_chip; | |
dc3465a9 LP |
356 | gpio_chip->request = gpio_rcar_request; |
357 | gpio_chip->free = gpio_rcar_free; | |
119f5e44 MD |
358 | gpio_chip->direction_input = gpio_rcar_direction_input; |
359 | gpio_chip->get = gpio_rcar_get; | |
360 | gpio_chip->direction_output = gpio_rcar_direction_output; | |
361 | gpio_chip->set = gpio_rcar_set; | |
362 | gpio_chip->to_irq = gpio_rcar_to_irq; | |
363 | gpio_chip->label = name; | |
159f8a02 | 364 | gpio_chip->dev = &pdev->dev; |
119f5e44 MD |
365 | gpio_chip->owner = THIS_MODULE; |
366 | gpio_chip->base = p->config.gpio_base; | |
367 | gpio_chip->ngpio = p->config.number_of_pins; | |
368 | ||
369 | irq_chip = &p->irq_chip; | |
370 | irq_chip->name = name; | |
371 | irq_chip->irq_mask = gpio_rcar_irq_disable; | |
372 | irq_chip->irq_unmask = gpio_rcar_irq_enable; | |
373 | irq_chip->irq_enable = gpio_rcar_irq_enable; | |
374 | irq_chip->irq_disable = gpio_rcar_irq_disable; | |
375 | irq_chip->irq_set_type = gpio_rcar_irq_set_type; | |
376 | irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED; | |
377 | ||
378 | p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, | |
379 | p->config.number_of_pins, | |
380 | p->config.irq_base, | |
381 | &gpio_rcar_irq_domain_ops, p); | |
382 | if (!p->irq_domain) { | |
383 | ret = -ENXIO; | |
384 | dev_err(&pdev->dev, "cannot initialize irq domain\n"); | |
0c8aab8e | 385 | goto err0; |
119f5e44 MD |
386 | } |
387 | ||
388 | if (devm_request_irq(&pdev->dev, irq->start, | |
c234962b | 389 | gpio_rcar_irq_handler, IRQF_SHARED, name, p)) { |
119f5e44 MD |
390 | dev_err(&pdev->dev, "failed to request IRQ\n"); |
391 | ret = -ENOENT; | |
392 | goto err1; | |
393 | } | |
394 | ||
395 | ret = gpiochip_add(gpio_chip); | |
396 | if (ret) { | |
397 | dev_err(&pdev->dev, "failed to add GPIO controller\n"); | |
398 | goto err1; | |
399 | } | |
400 | ||
401 | dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins); | |
402 | ||
403 | /* warn in case of mismatch if irq base is specified */ | |
404 | if (p->config.irq_base) { | |
405 | ret = irq_find_mapping(p->irq_domain, 0); | |
406 | if (p->config.irq_base != ret) | |
407 | dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n", | |
408 | p->config.irq_base, ret); | |
409 | } | |
410 | ||
159f8a02 LP |
411 | if (p->config.pctl_name) { |
412 | ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0, | |
413 | gpio_chip->base, gpio_chip->ngpio); | |
414 | if (ret < 0) | |
415 | dev_warn(&pdev->dev, "failed to add pin range\n"); | |
416 | } | |
dc3465a9 | 417 | |
119f5e44 MD |
418 | return 0; |
419 | ||
420 | err1: | |
421 | irq_domain_remove(p->irq_domain); | |
422 | err0: | |
423 | return ret; | |
424 | } | |
425 | ||
426 | static int gpio_rcar_remove(struct platform_device *pdev) | |
427 | { | |
428 | struct gpio_rcar_priv *p = platform_get_drvdata(pdev); | |
429 | int ret; | |
430 | ||
431 | ret = gpiochip_remove(&p->gpio_chip); | |
432 | if (ret) | |
433 | return ret; | |
434 | ||
435 | irq_domain_remove(p->irq_domain); | |
436 | return 0; | |
437 | } | |
438 | ||
159f8a02 LP |
439 | #ifdef CONFIG_OF |
440 | static const struct of_device_id gpio_rcar_of_table[] = { | |
441 | { | |
442 | .compatible = "renesas,gpio-rcar", | |
443 | }, | |
30d2266c | 444 | { }, |
159f8a02 LP |
445 | }; |
446 | ||
447 | MODULE_DEVICE_TABLE(of, gpio_rcar_of_table); | |
448 | #endif | |
449 | ||
119f5e44 MD |
450 | static struct platform_driver gpio_rcar_device_driver = { |
451 | .probe = gpio_rcar_probe, | |
452 | .remove = gpio_rcar_remove, | |
453 | .driver = { | |
454 | .name = "gpio_rcar", | |
159f8a02 | 455 | .of_match_table = of_match_ptr(gpio_rcar_of_table), |
119f5e44 MD |
456 | } |
457 | }; | |
458 | ||
459 | module_platform_driver(gpio_rcar_device_driver); | |
460 | ||
461 | MODULE_AUTHOR("Magnus Damm"); | |
462 | MODULE_DESCRIPTION("Renesas R-Car GPIO Driver"); | |
463 | MODULE_LICENSE("GPL v2"); |