Commit | Line | Data |
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119f5e44 MD |
1 | /* |
2 | * Renesas R-Car GPIO Support | |
3 | * | |
1fd2b49d | 4 | * Copyright (C) 2014 Renesas Electronics Corporation |
119f5e44 MD |
5 | * Copyright (C) 2013 Magnus Damm |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #include <linux/err.h> | |
18 | #include <linux/gpio.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/io.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/irq.h> | |
119f5e44 | 24 | #include <linux/module.h> |
bd0bf468 | 25 | #include <linux/of.h> |
f9f2a6fe | 26 | #include <linux/of_device.h> |
dc3465a9 | 27 | #include <linux/pinctrl/consumer.h> |
119f5e44 | 28 | #include <linux/platform_device.h> |
df0c6c80 | 29 | #include <linux/pm_runtime.h> |
119f5e44 MD |
30 | #include <linux/spinlock.h> |
31 | #include <linux/slab.h> | |
32 | ||
33 | struct gpio_rcar_priv { | |
34 | void __iomem *base; | |
35 | spinlock_t lock; | |
119f5e44 MD |
36 | struct platform_device *pdev; |
37 | struct gpio_chip gpio_chip; | |
38 | struct irq_chip irq_chip; | |
8b092be9 | 39 | unsigned int irq_parent; |
9ac79ba9 | 40 | atomic_t wakeup_path; |
8b092be9 | 41 | bool has_both_edge_trigger; |
119f5e44 MD |
42 | }; |
43 | ||
3dc1e685 GU |
44 | #define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */ |
45 | #define INOUTSEL 0x04 /* General Input/Output Switching Register */ | |
46 | #define OUTDT 0x08 /* General Output Register */ | |
47 | #define INDT 0x0c /* General Input Register */ | |
48 | #define INTDT 0x10 /* Interrupt Display Register */ | |
49 | #define INTCLR 0x14 /* Interrupt Clear Register */ | |
50 | #define INTMSK 0x18 /* Interrupt Mask Register */ | |
51 | #define MSKCLR 0x1c /* Interrupt Mask Clear Register */ | |
52 | #define POSNEG 0x20 /* Positive/Negative Logic Select Register */ | |
53 | #define EDGLEVEL 0x24 /* Edge/level Select Register */ | |
54 | #define FILONOFF 0x28 /* Chattering Prevention On/Off Register */ | |
55 | #define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */ | |
119f5e44 | 56 | |
159f8a02 LP |
57 | #define RCAR_MAX_GPIO_PER_BANK 32 |
58 | ||
119f5e44 MD |
59 | static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs) |
60 | { | |
61 | return ioread32(p->base + offs); | |
62 | } | |
63 | ||
64 | static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs, | |
65 | u32 value) | |
66 | { | |
67 | iowrite32(value, p->base + offs); | |
68 | } | |
69 | ||
70 | static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs, | |
71 | int bit, bool value) | |
72 | { | |
73 | u32 tmp = gpio_rcar_read(p, offs); | |
74 | ||
75 | if (value) | |
76 | tmp |= BIT(bit); | |
77 | else | |
78 | tmp &= ~BIT(bit); | |
79 | ||
80 | gpio_rcar_write(p, offs, tmp); | |
81 | } | |
82 | ||
83 | static void gpio_rcar_irq_disable(struct irq_data *d) | |
84 | { | |
c7f3c5d3 | 85 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
c7b6f457 | 86 | struct gpio_rcar_priv *p = gpiochip_get_data(gc); |
119f5e44 MD |
87 | |
88 | gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d))); | |
89 | } | |
90 | ||
91 | static void gpio_rcar_irq_enable(struct irq_data *d) | |
92 | { | |
c7f3c5d3 | 93 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
c7b6f457 | 94 | struct gpio_rcar_priv *p = gpiochip_get_data(gc); |
119f5e44 MD |
95 | |
96 | gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d))); | |
97 | } | |
98 | ||
99 | static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, | |
100 | unsigned int hwirq, | |
101 | bool active_high_rising_edge, | |
7e1092b5 SH |
102 | bool level_trigger, |
103 | bool both) | |
119f5e44 MD |
104 | { |
105 | unsigned long flags; | |
106 | ||
107 | /* follow steps in the GPIO documentation for | |
108 | * "Setting Edge-Sensitive Interrupt Input Mode" and | |
109 | * "Setting Level-Sensitive Interrupt Input Mode" | |
110 | */ | |
111 | ||
112 | spin_lock_irqsave(&p->lock, flags); | |
113 | ||
114 | /* Configure postive or negative logic in POSNEG */ | |
115 | gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); | |
116 | ||
117 | /* Configure edge or level trigger in EDGLEVEL */ | |
118 | gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); | |
119 | ||
7e1092b5 | 120 | /* Select one edge or both edges in BOTHEDGE */ |
8b092be9 | 121 | if (p->has_both_edge_trigger) |
7e1092b5 SH |
122 | gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both); |
123 | ||
119f5e44 MD |
124 | /* Select "Interrupt Input Mode" in IOINTSEL */ |
125 | gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); | |
126 | ||
127 | /* Write INTCLR in case of edge trigger */ | |
128 | if (!level_trigger) | |
129 | gpio_rcar_write(p, INTCLR, BIT(hwirq)); | |
130 | ||
131 | spin_unlock_irqrestore(&p->lock, flags); | |
132 | } | |
133 | ||
134 | static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type) | |
135 | { | |
c7f3c5d3 | 136 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
c7b6f457 | 137 | struct gpio_rcar_priv *p = gpiochip_get_data(gc); |
119f5e44 MD |
138 | unsigned int hwirq = irqd_to_hwirq(d); |
139 | ||
140 | dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type); | |
141 | ||
142 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
143 | case IRQ_TYPE_LEVEL_HIGH: | |
7e1092b5 SH |
144 | gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true, |
145 | false); | |
119f5e44 MD |
146 | break; |
147 | case IRQ_TYPE_LEVEL_LOW: | |
7e1092b5 SH |
148 | gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true, |
149 | false); | |
119f5e44 MD |
150 | break; |
151 | case IRQ_TYPE_EDGE_RISING: | |
7e1092b5 SH |
152 | gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, |
153 | false); | |
119f5e44 MD |
154 | break; |
155 | case IRQ_TYPE_EDGE_FALLING: | |
7e1092b5 SH |
156 | gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false, |
157 | false); | |
158 | break; | |
159 | case IRQ_TYPE_EDGE_BOTH: | |
8b092be9 | 160 | if (!p->has_both_edge_trigger) |
7e1092b5 SH |
161 | return -EINVAL; |
162 | gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false, | |
163 | true); | |
119f5e44 MD |
164 | break; |
165 | default: | |
166 | return -EINVAL; | |
167 | } | |
168 | return 0; | |
169 | } | |
170 | ||
ab82fa7d GU |
171 | static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on) |
172 | { | |
173 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
c7b6f457 | 174 | struct gpio_rcar_priv *p = gpiochip_get_data(gc); |
501ef0f9 GU |
175 | int error; |
176 | ||
177 | if (p->irq_parent) { | |
178 | error = irq_set_irq_wake(p->irq_parent, on); | |
179 | if (error) { | |
180 | dev_dbg(&p->pdev->dev, | |
181 | "irq %u doesn't support irq_set_wake\n", | |
182 | p->irq_parent); | |
183 | p->irq_parent = 0; | |
184 | } | |
185 | } | |
ab82fa7d | 186 | |
ab82fa7d | 187 | if (on) |
9ac79ba9 | 188 | atomic_inc(&p->wakeup_path); |
ab82fa7d | 189 | else |
9ac79ba9 | 190 | atomic_dec(&p->wakeup_path); |
ab82fa7d GU |
191 | |
192 | return 0; | |
193 | } | |
194 | ||
119f5e44 MD |
195 | static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id) |
196 | { | |
197 | struct gpio_rcar_priv *p = dev_id; | |
198 | u32 pending; | |
199 | unsigned int offset, irqs_handled = 0; | |
200 | ||
8808b64d VB |
201 | while ((pending = gpio_rcar_read(p, INTDT) & |
202 | gpio_rcar_read(p, INTMSK))) { | |
119f5e44 MD |
203 | offset = __ffs(pending); |
204 | gpio_rcar_write(p, INTCLR, BIT(offset)); | |
f0fbe7bc | 205 | generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain, |
c7f3c5d3 | 206 | offset)); |
119f5e44 MD |
207 | irqs_handled++; |
208 | } | |
209 | ||
210 | return irqs_handled ? IRQ_HANDLED : IRQ_NONE; | |
211 | } | |
212 | ||
119f5e44 MD |
213 | static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip, |
214 | unsigned int gpio, | |
215 | bool output) | |
216 | { | |
c7b6f457 | 217 | struct gpio_rcar_priv *p = gpiochip_get_data(chip); |
119f5e44 MD |
218 | unsigned long flags; |
219 | ||
220 | /* follow steps in the GPIO documentation for | |
221 | * "Setting General Output Mode" and | |
222 | * "Setting General Input Mode" | |
223 | */ | |
224 | ||
225 | spin_lock_irqsave(&p->lock, flags); | |
226 | ||
227 | /* Configure postive logic in POSNEG */ | |
228 | gpio_rcar_modify_bit(p, POSNEG, gpio, false); | |
229 | ||
230 | /* Select "General Input/Output Mode" in IOINTSEL */ | |
231 | gpio_rcar_modify_bit(p, IOINTSEL, gpio, false); | |
232 | ||
233 | /* Select Input Mode or Output Mode in INOUTSEL */ | |
234 | gpio_rcar_modify_bit(p, INOUTSEL, gpio, output); | |
235 | ||
236 | spin_unlock_irqrestore(&p->lock, flags); | |
237 | } | |
238 | ||
dc3465a9 LP |
239 | static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset) |
240 | { | |
2d65472b GU |
241 | struct gpio_rcar_priv *p = gpiochip_get_data(chip); |
242 | int error; | |
243 | ||
244 | error = pm_runtime_get_sync(&p->pdev->dev); | |
245 | if (error < 0) | |
246 | return error; | |
247 | ||
a9a1d2a7 | 248 | error = pinctrl_gpio_request(chip->base + offset); |
2d65472b GU |
249 | if (error) |
250 | pm_runtime_put(&p->pdev->dev); | |
251 | ||
252 | return error; | |
dc3465a9 LP |
253 | } |
254 | ||
255 | static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset) | |
256 | { | |
2d65472b GU |
257 | struct gpio_rcar_priv *p = gpiochip_get_data(chip); |
258 | ||
a9a1d2a7 | 259 | pinctrl_gpio_free(chip->base + offset); |
dc3465a9 | 260 | |
ce0e2c60 LW |
261 | /* |
262 | * Set the GPIO as an input to ensure that the next GPIO request won't | |
dc3465a9 LP |
263 | * drive the GPIO pin as an output. |
264 | */ | |
265 | gpio_rcar_config_general_input_output_mode(chip, offset, false); | |
2d65472b GU |
266 | |
267 | pm_runtime_put(&p->pdev->dev); | |
dc3465a9 LP |
268 | } |
269 | ||
119f5e44 MD |
270 | static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset) |
271 | { | |
272 | gpio_rcar_config_general_input_output_mode(chip, offset, false); | |
273 | return 0; | |
274 | } | |
275 | ||
276 | static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset) | |
277 | { | |
ae9550f6 MD |
278 | u32 bit = BIT(offset); |
279 | ||
280 | /* testing on r8a7790 shows that INDT does not show correct pin state | |
281 | * when configured as output, so use OUTDT in case of output pins */ | |
c7b6f457 LW |
282 | if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit) |
283 | return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit); | |
ae9550f6 | 284 | else |
c7b6f457 | 285 | return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit); |
119f5e44 MD |
286 | } |
287 | ||
288 | static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value) | |
289 | { | |
c7b6f457 | 290 | struct gpio_rcar_priv *p = gpiochip_get_data(chip); |
119f5e44 MD |
291 | unsigned long flags; |
292 | ||
293 | spin_lock_irqsave(&p->lock, flags); | |
294 | gpio_rcar_modify_bit(p, OUTDT, offset, value); | |
295 | spin_unlock_irqrestore(&p->lock, flags); | |
296 | } | |
297 | ||
dbb763b8 GU |
298 | static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask, |
299 | unsigned long *bits) | |
300 | { | |
301 | struct gpio_rcar_priv *p = gpiochip_get_data(chip); | |
302 | unsigned long flags; | |
303 | u32 val, bankmask; | |
304 | ||
305 | bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0); | |
306 | if (!bankmask) | |
307 | return; | |
308 | ||
309 | spin_lock_irqsave(&p->lock, flags); | |
310 | val = gpio_rcar_read(p, OUTDT); | |
311 | val &= ~bankmask; | |
312 | val |= (bankmask & bits[0]); | |
313 | gpio_rcar_write(p, OUTDT, val); | |
314 | spin_unlock_irqrestore(&p->lock, flags); | |
315 | } | |
316 | ||
119f5e44 MD |
317 | static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset, |
318 | int value) | |
319 | { | |
320 | /* write GPIO value to output before selecting output mode of pin */ | |
321 | gpio_rcar_set(chip, offset, value); | |
322 | gpio_rcar_config_general_input_output_mode(chip, offset, true); | |
323 | return 0; | |
324 | } | |
325 | ||
850dfe17 LP |
326 | struct gpio_rcar_info { |
327 | bool has_both_edge_trigger; | |
328 | }; | |
329 | ||
1fd2b49d HN |
330 | static const struct gpio_rcar_info gpio_rcar_info_gen1 = { |
331 | .has_both_edge_trigger = false, | |
332 | }; | |
333 | ||
334 | static const struct gpio_rcar_info gpio_rcar_info_gen2 = { | |
335 | .has_both_edge_trigger = true, | |
336 | }; | |
337 | ||
850dfe17 LP |
338 | static const struct of_device_id gpio_rcar_of_table[] = { |
339 | { | |
85bb4646 BD |
340 | .compatible = "renesas,gpio-r8a7743", |
341 | /* RZ/G1 GPIO is identical to R-Car Gen2. */ | |
342 | .data = &gpio_rcar_info_gen2, | |
343 | }, { | |
850dfe17 | 344 | .compatible = "renesas,gpio-r8a7790", |
1fd2b49d | 345 | .data = &gpio_rcar_info_gen2, |
850dfe17 LP |
346 | }, { |
347 | .compatible = "renesas,gpio-r8a7791", | |
1fd2b49d | 348 | .data = &gpio_rcar_info_gen2, |
e79c5830 SS |
349 | }, { |
350 | .compatible = "renesas,gpio-r8a7792", | |
351 | .data = &gpio_rcar_info_gen2, | |
1fd2b49d HN |
352 | }, { |
353 | .compatible = "renesas,gpio-r8a7793", | |
354 | .data = &gpio_rcar_info_gen2, | |
355 | }, { | |
356 | .compatible = "renesas,gpio-r8a7794", | |
357 | .data = &gpio_rcar_info_gen2, | |
8cd14702 UH |
358 | }, { |
359 | .compatible = "renesas,gpio-r8a7795", | |
360 | /* Gen3 GPIO is identical to Gen2. */ | |
361 | .data = &gpio_rcar_info_gen2, | |
5d2f1d6e SH |
362 | }, { |
363 | .compatible = "renesas,gpio-r8a7796", | |
364 | /* Gen3 GPIO is identical to Gen2. */ | |
365 | .data = &gpio_rcar_info_gen2, | |
dbd1dad2 SH |
366 | }, { |
367 | .compatible = "renesas,rcar-gen1-gpio", | |
368 | .data = &gpio_rcar_info_gen1, | |
369 | }, { | |
370 | .compatible = "renesas,rcar-gen2-gpio", | |
371 | .data = &gpio_rcar_info_gen2, | |
372 | }, { | |
373 | .compatible = "renesas,rcar-gen3-gpio", | |
374 | /* Gen3 GPIO is identical to Gen2. */ | |
375 | .data = &gpio_rcar_info_gen2, | |
850dfe17 LP |
376 | }, { |
377 | .compatible = "renesas,gpio-rcar", | |
1fd2b49d | 378 | .data = &gpio_rcar_info_gen1, |
850dfe17 LP |
379 | }, { |
380 | /* Terminator */ | |
381 | }, | |
382 | }; | |
383 | ||
384 | MODULE_DEVICE_TABLE(of, gpio_rcar_of_table); | |
385 | ||
8b092be9 | 386 | static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins) |
159f8a02 | 387 | { |
159f8a02 | 388 | struct device_node *np = p->pdev->dev.of_node; |
8b092be9 | 389 | const struct gpio_rcar_info *info; |
159f8a02 LP |
390 | struct of_phandle_args args; |
391 | int ret; | |
159f8a02 | 392 | |
f9f2a6fe | 393 | info = of_device_get_match_data(&p->pdev->dev); |
850dfe17 | 394 | |
8b092be9 GU |
395 | ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args); |
396 | *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK; | |
397 | p->has_both_edge_trigger = info->has_both_edge_trigger; | |
850dfe17 | 398 | |
8b092be9 | 399 | if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) { |
159f8a02 | 400 | dev_warn(&p->pdev->dev, |
8b092be9 GU |
401 | "Invalid number of gpio lines %u, using %u\n", *npins, |
402 | RCAR_MAX_GPIO_PER_BANK); | |
403 | *npins = RCAR_MAX_GPIO_PER_BANK; | |
159f8a02 | 404 | } |
850dfe17 LP |
405 | |
406 | return 0; | |
159f8a02 LP |
407 | } |
408 | ||
119f5e44 MD |
409 | static int gpio_rcar_probe(struct platform_device *pdev) |
410 | { | |
119f5e44 MD |
411 | struct gpio_rcar_priv *p; |
412 | struct resource *io, *irq; | |
413 | struct gpio_chip *gpio_chip; | |
414 | struct irq_chip *irq_chip; | |
b22978fc GU |
415 | struct device *dev = &pdev->dev; |
416 | const char *name = dev_name(dev); | |
8b092be9 | 417 | unsigned int npins; |
119f5e44 MD |
418 | int ret; |
419 | ||
b22978fc | 420 | p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); |
7d82bf34 GU |
421 | if (!p) |
422 | return -ENOMEM; | |
119f5e44 | 423 | |
119f5e44 | 424 | p->pdev = pdev; |
119f5e44 MD |
425 | spin_lock_init(&p->lock); |
426 | ||
8b092be9 GU |
427 | /* Get device configuration from DT node */ |
428 | ret = gpio_rcar_parse_dt(p, &npins); | |
850dfe17 LP |
429 | if (ret < 0) |
430 | return ret; | |
159f8a02 LP |
431 | |
432 | platform_set_drvdata(pdev, p); | |
433 | ||
df0c6c80 | 434 | pm_runtime_enable(dev); |
df0c6c80 | 435 | |
119f5e44 | 436 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
5a24d4b6 SS |
437 | if (!irq) { |
438 | dev_err(dev, "missing IRQ\n"); | |
119f5e44 MD |
439 | ret = -EINVAL; |
440 | goto err0; | |
441 | } | |
442 | ||
5a24d4b6 SS |
443 | io = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
444 | p->base = devm_ioremap_resource(dev, io); | |
445 | if (IS_ERR(p->base)) { | |
446 | ret = PTR_ERR(p->base); | |
119f5e44 MD |
447 | goto err0; |
448 | } | |
449 | ||
450 | gpio_chip = &p->gpio_chip; | |
dc3465a9 LP |
451 | gpio_chip->request = gpio_rcar_request; |
452 | gpio_chip->free = gpio_rcar_free; | |
119f5e44 MD |
453 | gpio_chip->direction_input = gpio_rcar_direction_input; |
454 | gpio_chip->get = gpio_rcar_get; | |
455 | gpio_chip->direction_output = gpio_rcar_direction_output; | |
456 | gpio_chip->set = gpio_rcar_set; | |
dbb763b8 | 457 | gpio_chip->set_multiple = gpio_rcar_set_multiple; |
119f5e44 | 458 | gpio_chip->label = name; |
58383c78 | 459 | gpio_chip->parent = dev; |
119f5e44 | 460 | gpio_chip->owner = THIS_MODULE; |
8b092be9 GU |
461 | gpio_chip->base = -1; |
462 | gpio_chip->ngpio = npins; | |
119f5e44 MD |
463 | |
464 | irq_chip = &p->irq_chip; | |
465 | irq_chip->name = name; | |
47bd38a3 | 466 | irq_chip->parent_device = dev; |
119f5e44 MD |
467 | irq_chip->irq_mask = gpio_rcar_irq_disable; |
468 | irq_chip->irq_unmask = gpio_rcar_irq_enable; | |
119f5e44 | 469 | irq_chip->irq_set_type = gpio_rcar_irq_set_type; |
ab82fa7d GU |
470 | irq_chip->irq_set_wake = gpio_rcar_irq_set_wake; |
471 | irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND; | |
119f5e44 | 472 | |
c7b6f457 | 473 | ret = gpiochip_add_data(gpio_chip, p); |
c7f3c5d3 GU |
474 | if (ret) { |
475 | dev_err(dev, "failed to add GPIO controller\n"); | |
0c8aab8e | 476 | goto err0; |
119f5e44 MD |
477 | } |
478 | ||
8b092be9 GU |
479 | ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq, |
480 | IRQ_TYPE_NONE); | |
c7f3c5d3 GU |
481 | if (ret) { |
482 | dev_err(dev, "cannot add irqchip\n"); | |
483 | goto err1; | |
484 | } | |
485 | ||
ab82fa7d | 486 | p->irq_parent = irq->start; |
b22978fc GU |
487 | if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler, |
488 | IRQF_SHARED, name, p)) { | |
489 | dev_err(dev, "failed to request IRQ\n"); | |
119f5e44 MD |
490 | ret = -ENOENT; |
491 | goto err1; | |
492 | } | |
493 | ||
8b092be9 | 494 | dev_info(dev, "driving %d GPIOs\n", npins); |
dc3465a9 | 495 | |
119f5e44 MD |
496 | return 0; |
497 | ||
498 | err1: | |
4d84b9e4 | 499 | gpiochip_remove(gpio_chip); |
119f5e44 | 500 | err0: |
df0c6c80 | 501 | pm_runtime_disable(dev); |
119f5e44 MD |
502 | return ret; |
503 | } | |
504 | ||
505 | static int gpio_rcar_remove(struct platform_device *pdev) | |
506 | { | |
507 | struct gpio_rcar_priv *p = platform_get_drvdata(pdev); | |
119f5e44 | 508 | |
9f5132ae | 509 | gpiochip_remove(&p->gpio_chip); |
119f5e44 | 510 | |
df0c6c80 | 511 | pm_runtime_disable(&pdev->dev); |
119f5e44 MD |
512 | return 0; |
513 | } | |
514 | ||
9ac79ba9 GU |
515 | static int __maybe_unused gpio_rcar_suspend(struct device *dev) |
516 | { | |
517 | struct gpio_rcar_priv *p = dev_get_drvdata(dev); | |
518 | ||
519 | if (atomic_read(&p->wakeup_path)) | |
520 | device_set_wakeup_path(dev); | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, NULL); | |
526 | ||
119f5e44 MD |
527 | static struct platform_driver gpio_rcar_device_driver = { |
528 | .probe = gpio_rcar_probe, | |
529 | .remove = gpio_rcar_remove, | |
530 | .driver = { | |
531 | .name = "gpio_rcar", | |
9ac79ba9 | 532 | .pm = &gpio_rcar_pm_ops, |
159f8a02 | 533 | .of_match_table = of_match_ptr(gpio_rcar_of_table), |
119f5e44 MD |
534 | } |
535 | }; | |
536 | ||
537 | module_platform_driver(gpio_rcar_device_driver); | |
538 | ||
539 | MODULE_AUTHOR("Magnus Damm"); | |
540 | MODULE_DESCRIPTION("Renesas R-Car GPIO Driver"); | |
541 | MODULE_LICENSE("GPL v2"); |