[linux-2.6-block.git] / drivers / gpio / gpio-rcar.c

/*
 * Renesas R-Car GPIO Support
 *
 *  Copyright (C) 2014 Renesas Electronics Corporation
 *  Copyright (C) 2013 Magnus Damm
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/err.h>
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spinlock.h>
#include <linux/slab.h>

struct gpio_rcar_bank_info {
	u32 iointsel;
	u32 inoutsel;
	u32 outdt;
	u32 posneg;
	u32 edglevel;
	u32 bothedge;
	u32 intmsk;
};

struct gpio_rcar_priv {
	void __iomem *base;
	spinlock_t lock;
	struct platform_device *pdev;
	struct gpio_chip gpio_chip;
	struct irq_chip irq_chip;
	unsigned int irq_parent;
	atomic_t wakeup_path;
	bool has_both_edge_trigger;
	struct gpio_rcar_bank_info bank_info;
};

#define IOINTSEL 0x00	/* General IO/Interrupt Switching Register */
#define INOUTSEL 0x04	/* General Input/Output Switching Register */
#define OUTDT 0x08	/* General Output Register */
#define INDT 0x0c	/* General Input Register */
#define INTDT 0x10	/* Interrupt Display Register */
#define INTCLR 0x14	/* Interrupt Clear Register */
#define INTMSK 0x18	/* Interrupt Mask Register */
#define MSKCLR 0x1c	/* Interrupt Mask Clear Register */
#define POSNEG 0x20	/* Positive/Negative Logic Select Register */
#define EDGLEVEL 0x24	/* Edge/level Select Register */
#define FILONOFF 0x28	/* Chattering Prevention On/Off Register */
#define BOTHEDGE 0x4c	/* One Edge/Both Edge Select Register */

#define RCAR_MAX_GPIO_PER_BANK		32

static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
{
	return ioread32(p->base + offs);
}

static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
				   u32 value)
{
	iowrite32(value, p->base + offs);
}

static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
				 int bit, bool value)
{
	u32 tmp = gpio_rcar_read(p, offs);

	if (value)
		tmp |= BIT(bit);
	else
		tmp &= ~BIT(bit);

	gpio_rcar_write(p, offs, tmp);
}

static void gpio_rcar_irq_disable(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);

	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
}

static void gpio_rcar_irq_enable(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);

	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
}

static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
						  unsigned int hwirq,
						  bool active_high_rising_edge,
						  bool level_trigger,
						  bool both)
{
	unsigned long flags;

	/* follow steps in the GPIO documentation for
	 * "Setting Edge-Sensitive Interrupt Input Mode" and
	 * "Setting Level-Sensitive Interrupt Input Mode"
	 */

	spin_lock_irqsave(&p->lock, flags);

	/* Configure postive or negative logic in POSNEG */
	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);

	/* Configure edge or level trigger in EDGLEVEL */
	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);

	/* Select one edge or both edges in BOTHEDGE */
	if (p->has_both_edge_trigger)
		gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);

	/* Select "Interrupt Input Mode" in IOINTSEL */
	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);

	/* Write INTCLR in case of edge trigger */
	if (!level_trigger)
		gpio_rcar_write(p, INTCLR, BIT(hwirq));

	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
	unsigned int hwirq = irqd_to_hwirq(d);

	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_LEVEL_HIGH:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
						      false);
		break;
	case IRQ_TYPE_LEVEL_LOW:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
						      false);
		break;
	case IRQ_TYPE_EDGE_RISING:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
						      false);
		break;
	case IRQ_TYPE_EDGE_FALLING:
		gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
						      false);
		break;
	case IRQ_TYPE_EDGE_BOTH:
		if (!p->has_both_edge_trigger)
			return -EINVAL;
		gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
						      true);
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
	int error;

	if (p->irq_parent) {
		error = irq_set_irq_wake(p->irq_parent, on);
		if (error) {
			dev_dbg(&p->pdev->dev,
				"irq %u doesn't support irq_set_wake\n",
				p->irq_parent);
			p->irq_parent = 0;
		}
	}

	if (on)
		atomic_inc(&p->wakeup_path);
	else
		atomic_dec(&p->wakeup_path);

	return 0;
}

static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
{
	struct gpio_rcar_priv *p = dev_id;
	u32 pending;
	unsigned int offset, irqs_handled = 0;

	while ((pending = gpio_rcar_read(p, INTDT) &
			  gpio_rcar_read(p, INTMSK))) {
		offset = __ffs(pending);
		gpio_rcar_write(p, INTCLR, BIT(offset));
		generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
						    offset));
		irqs_handled++;
	}

	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
}

static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
						       unsigned int gpio,
						       bool output)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;

	/* follow steps in the GPIO documentation for
	 * "Setting General Output Mode" and
	 * "Setting General Input Mode"
	 */

	spin_lock_irqsave(&p->lock, flags);

	/* Configure postive logic in POSNEG */
	gpio_rcar_modify_bit(p, POSNEG, gpio, false);

	/* Select "General Input/Output Mode" in IOINTSEL */
	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);

	/* Select Input Mode or Output Mode in INOUTSEL */
	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);

	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	int error;

	error = pm_runtime_get_sync(&p->pdev->dev);
	if (error < 0)
		return error;

	error = pinctrl_gpio_request(chip->base + offset);
	if (error)
		pm_runtime_put(&p->pdev->dev);

	return error;
}

static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);

	pinctrl_gpio_free(chip->base + offset);

	/*
	 * Set the GPIO as an input to ensure that the next GPIO request won't
	 * drive the GPIO pin as an output.
	 */
	gpio_rcar_config_general_input_output_mode(chip, offset, false);

	pm_runtime_put(&p->pdev->dev);
}

static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);

	return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset));
}

static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
{
	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	return 0;
}

static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
{
	u32 bit = BIT(offset);

	/* testing on r8a7790 shows that INDT does not show correct pin state
	 * when configured as output, so use OUTDT in case of output pins */
	if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
		return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
	else
		return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
}

static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;

	spin_lock_irqsave(&p->lock, flags);
	gpio_rcar_modify_bit(p, OUTDT, offset, value);
	spin_unlock_irqrestore(&p->lock, flags);
}

static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
				   unsigned long *bits)
{
	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	unsigned long flags;
	u32 val, bankmask;

	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
	if (chip->valid_mask)
		bankmask &= chip->valid_mask[0];

	if (!bankmask)
		return;

	spin_lock_irqsave(&p->lock, flags);
	val = gpio_rcar_read(p, OUTDT);
	val &= ~bankmask;
	val |= (bankmask & bits[0]);
	gpio_rcar_write(p, OUTDT, val);
	spin_unlock_irqrestore(&p->lock, flags);
}

static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
				      int value)
{
	/* write GPIO value to output before selecting output mode of pin */
	gpio_rcar_set(chip, offset, value);
	gpio_rcar_config_general_input_output_mode(chip, offset, true);
	return 0;
}

struct gpio_rcar_info {
	bool has_both_edge_trigger;
};

static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
	.has_both_edge_trigger = false,
};

static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
	.has_both_edge_trigger = true,
};

static const struct of_device_id gpio_rcar_of_table[] = {
	{
		.compatible = "renesas,gpio-r8a7743",
		/* RZ/G1 GPIO is identical to R-Car Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7790",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7791",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7792",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7793",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7794",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7795",
		/* Gen3 GPIO is identical to Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-r8a7796",
		/* Gen3 GPIO is identical to Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,rcar-gen1-gpio",
		.data = &gpio_rcar_info_gen1,
	}, {
		.compatible = "renesas,rcar-gen2-gpio",
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,rcar-gen3-gpio",
		/* Gen3 GPIO is identical to Gen2. */
		.data = &gpio_rcar_info_gen2,
	}, {
		.compatible = "renesas,gpio-rcar",
		.data = &gpio_rcar_info_gen1,
	}, {
		/* Terminator */
	},
};

MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);

static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
{
	struct device_node *np = p->pdev->dev.of_node;
	const struct gpio_rcar_info *info;
	struct of_phandle_args args;
	int ret;

	info = of_device_get_match_data(&p->pdev->dev);

	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
	p->has_both_edge_trigger = info->has_both_edge_trigger;

	if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
		dev_warn(&p->pdev->dev,
			 "Invalid number of gpio lines %u, using %u\n", *npins,
			 RCAR_MAX_GPIO_PER_BANK);
		*npins = RCAR_MAX_GPIO_PER_BANK;
	}

	return 0;
}

static int gpio_rcar_probe(struct platform_device *pdev)
{
	struct gpio_rcar_priv *p;
	struct resource *io, *irq;
	struct gpio_chip *gpio_chip;
	struct irq_chip *irq_chip;
	struct device *dev = &pdev->dev;
	const char *name = dev_name(dev);
	unsigned int npins;
	int ret;

	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
	if (!p)
		return -ENOMEM;

	p->pdev = pdev;
	spin_lock_init(&p->lock);

	/* Get device configuration from DT node */
	ret = gpio_rcar_parse_dt(p, &npins);
	if (ret < 0)
		return ret;

	platform_set_drvdata(pdev, p);

	pm_runtime_enable(dev);

	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (!irq) {
		dev_err(dev, "missing IRQ\n");
		ret = -EINVAL;
		goto err0;
	}

	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	p->base = devm_ioremap_resource(dev, io);
	if (IS_ERR(p->base)) {
		ret = PTR_ERR(p->base);
		goto err0;
	}

	gpio_chip = &p->gpio_chip;
	gpio_chip->request = gpio_rcar_request;
	gpio_chip->free = gpio_rcar_free;
	gpio_chip->get_direction = gpio_rcar_get_direction;
	gpio_chip->direction_input = gpio_rcar_direction_input;
	gpio_chip->get = gpio_rcar_get;
	gpio_chip->direction_output = gpio_rcar_direction_output;
	gpio_chip->set = gpio_rcar_set;
	gpio_chip->set_multiple = gpio_rcar_set_multiple;
	gpio_chip->label = name;
	gpio_chip->parent = dev;
	gpio_chip->owner = THIS_MODULE;
	gpio_chip->base = -1;
	gpio_chip->ngpio = npins;

	irq_chip = &p->irq_chip;
	irq_chip->name = name;
	irq_chip->parent_device = dev;
	irq_chip->irq_mask = gpio_rcar_irq_disable;
	irq_chip->irq_unmask = gpio_rcar_irq_enable;
	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
	irq_chip->flags	= IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;

	ret = gpiochip_add_data(gpio_chip, p);
	if (ret) {
		dev_err(dev, "failed to add GPIO controller\n");
		goto err0;
	}

	ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
				   IRQ_TYPE_NONE);
	if (ret) {
		dev_err(dev, "cannot add irqchip\n");
		goto err1;
	}

	p->irq_parent = irq->start;
	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
			     IRQF_SHARED, name, p)) {
		dev_err(dev, "failed to request IRQ\n");
		ret = -ENOENT;
		goto err1;
	}

	dev_info(dev, "driving %d GPIOs\n", npins);

	return 0;

err1:
	gpiochip_remove(gpio_chip);
err0:
	pm_runtime_disable(dev);
	return ret;
}

static int gpio_rcar_remove(struct platform_device *pdev)
{
	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);

	gpiochip_remove(&p->gpio_chip);

	pm_runtime_disable(&pdev->dev);
	return 0;
}

#ifdef CONFIG_PM_SLEEP
static int gpio_rcar_suspend(struct device *dev)
{
	struct gpio_rcar_priv *p = dev_get_drvdata(dev);

	p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
	p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
	p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
	p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
	p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
	p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
	if (p->has_both_edge_trigger)
		p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);

	if (atomic_read(&p->wakeup_path))
		device_set_wakeup_path(dev);

	return 0;
}

static int gpio_rcar_resume(struct device *dev)
{
	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
	unsigned int offset;
	u32 mask;

	for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
		if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
			continue;

		mask = BIT(offset);
		/* I/O pin */
		if (!(p->bank_info.iointsel & mask)) {
			if (p->bank_info.inoutsel & mask)
				gpio_rcar_direction_output(
					&p->gpio_chip, offset,
					!!(p->bank_info.outdt & mask));
			else
				gpio_rcar_direction_input(&p->gpio_chip,
							  offset);
		} else {
			/* Interrupt pin */
			gpio_rcar_config_interrupt_input_mode(
				p,
				offset,
				!(p->bank_info.posneg & mask),
				!(p->bank_info.edglevel & mask),
				!!(p->bank_info.bothedge & mask));

			if (p->bank_info.intmsk & mask)
				gpio_rcar_write(p, MSKCLR, mask);
		}
	}

	return 0;
}
#endif /* CONFIG_PM_SLEEP*/

static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);

static struct platform_driver gpio_rcar_device_driver = {
	.probe		= gpio_rcar_probe,
	.remove		= gpio_rcar_remove,
	.driver		= {
		.name	= "gpio_rcar",
		.pm     = &gpio_rcar_pm_ops,
		.of_match_table = of_match_ptr(gpio_rcar_of_table),
	}
};

module_platform_driver(gpio_rcar_device_driver);

MODULE_AUTHOR("Magnus Damm");
MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
119f5e44 MD	1	/*
	2	* Renesas R-Car GPIO Support
	3	*
1fd2b49d	4	* Copyright (C) 2014 Renesas Electronics Corporation
119f5e44 MD	5	* Copyright (C) 2013 Magnus Damm
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
	17	#include <linux/err.h>
4b1d8007	18	#include <linux/gpio/driver.h>
119f5e44 MD	19	#include <linux/init.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/io.h>
	22	#include <linux/ioport.h>
	23	#include <linux/irq.h>
119f5e44	24	#include <linux/module.h>
bd0bf468	25	#include <linux/of.h>
f9f2a6fe	26	#include <linux/of_device.h>
dc3465a9	27	#include <linux/pinctrl/consumer.h>
119f5e44	28	#include <linux/platform_device.h>
df0c6c80	29	#include <linux/pm_runtime.h>
119f5e44 MD	30	#include <linux/spinlock.h>
	31	#include <linux/slab.h>
	32
51750fb1 HD	33	struct gpio_rcar_bank_info {
	34	u32 iointsel;
	35	u32 inoutsel;
	36	u32 outdt;
	37	u32 posneg;
	38	u32 edglevel;
	39	u32 bothedge;
	40	u32 intmsk;
	41	};
	42
119f5e44 MD	43	struct gpio_rcar_priv {
	44	void __iomem *base;
	45	spinlock_t lock;
119f5e44 MD	46	struct platform_device *pdev;
	47	struct gpio_chip gpio_chip;
	48	struct irq_chip irq_chip;
8b092be9	49	unsigned int irq_parent;
9ac79ba9	50	atomic_t wakeup_path;
8b092be9	51	bool has_both_edge_trigger;
51750fb1	52	struct gpio_rcar_bank_info bank_info;
119f5e44 MD	53	};
119f5e44 MD	54
3dc1e685 GU	55	#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
	56	#define INOUTSEL 0x04 /* General Input/Output Switching Register */
	57	#define OUTDT 0x08 /* General Output Register */
	58	#define INDT 0x0c /* General Input Register */
	59	#define INTDT 0x10 /* Interrupt Display Register */
	60	#define INTCLR 0x14 /* Interrupt Clear Register */
	61	#define INTMSK 0x18 /* Interrupt Mask Register */
	62	#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
	63	#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
	64	#define EDGLEVEL 0x24 /* Edge/level Select Register */
	65	#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
	66	#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
119f5e44	67
159f8a02 LP	68	#define RCAR_MAX_GPIO_PER_BANK 32
159f8a02 LP	69
119f5e44 MD	70	static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
	71	{
	72	return ioread32(p->base + offs);
	73	}
	74
	75	static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
	76	u32 value)
	77	{
	78	iowrite32(value, p->base + offs);
	79	}
	80
	81	static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
	82	int bit, bool value)
	83	{
	84	u32 tmp = gpio_rcar_read(p, offs);
	85
	86	if (value)
	87	tmp \|= BIT(bit);
	88	else
	89	tmp &= ~BIT(bit);
	90
	91	gpio_rcar_write(p, offs, tmp);
	92	}
	93
	94	static void gpio_rcar_irq_disable(struct irq_data *d)
	95	{
c7f3c5d3	96	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	97	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	98
	99	gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
	100	}
	101
	102	static void gpio_rcar_irq_enable(struct irq_data *d)
	103	{
c7f3c5d3	104	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	105	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	106
	107	gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
	108	}
	109
	110	static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
	111	unsigned int hwirq,
	112	bool active_high_rising_edge,
7e1092b5 SH	113	bool level_trigger,
7e1092b5 SH	114	bool both)
119f5e44 MD	115	{
	116	unsigned long flags;
	117
	118	/* follow steps in the GPIO documentation for
	119	* "Setting Edge-Sensitive Interrupt Input Mode" and
	120	* "Setting Level-Sensitive Interrupt Input Mode"
	121	*/
	122
	123	spin_lock_irqsave(&p->lock, flags);
	124
	125	/* Configure postive or negative logic in POSNEG */
	126	gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
	127
	128	/* Configure edge or level trigger in EDGLEVEL */
	129	gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
	130
7e1092b5	131	/* Select one edge or both edges in BOTHEDGE */
8b092be9	132	if (p->has_both_edge_trigger)
7e1092b5 SH	133	gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
7e1092b5 SH	134
119f5e44 MD	135	/* Select "Interrupt Input Mode" in IOINTSEL */
	136	gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
	137
	138	/* Write INTCLR in case of edge trigger */
	139	if (!level_trigger)
	140	gpio_rcar_write(p, INTCLR, BIT(hwirq));
	141
	142	spin_unlock_irqrestore(&p->lock, flags);
	143	}
	144
	145	static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
	146	{
c7f3c5d3	147	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	148	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
119f5e44 MD	149	unsigned int hwirq = irqd_to_hwirq(d);
	150
	151	dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
	152
	153	switch (type & IRQ_TYPE_SENSE_MASK) {
	154	case IRQ_TYPE_LEVEL_HIGH:
7e1092b5 SH	155	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
7e1092b5 SH	156	false);
119f5e44 MD	157	break;
119f5e44 MD	158	case IRQ_TYPE_LEVEL_LOW:
7e1092b5 SH	159	gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
7e1092b5 SH	160	false);
119f5e44 MD	161	break;
119f5e44 MD	162	case IRQ_TYPE_EDGE_RISING:
7e1092b5 SH	163	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
7e1092b5 SH	164	false);
119f5e44 MD	165	break;
119f5e44 MD	166	case IRQ_TYPE_EDGE_FALLING:
7e1092b5 SH	167	gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
	168	false);
	169	break;
	170	case IRQ_TYPE_EDGE_BOTH:
8b092be9	171	if (!p->has_both_edge_trigger)
7e1092b5 SH	172	return -EINVAL;
	173	gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
	174	true);
119f5e44 MD	175	break;
	176	default:
	177	return -EINVAL;
	178	}
	179	return 0;
	180	}
	181
ab82fa7d GU	182	static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
	183	{
	184	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
c7b6f457	185	struct gpio_rcar_priv *p = gpiochip_get_data(gc);
501ef0f9 GU	186	int error;
	187
	188	if (p->irq_parent) {
	189	error = irq_set_irq_wake(p->irq_parent, on);
	190	if (error) {
	191	dev_dbg(&p->pdev->dev,
	192	"irq %u doesn't support irq_set_wake\n",
	193	p->irq_parent);
	194	p->irq_parent = 0;
	195	}
	196	}
ab82fa7d	197
ab82fa7d	198	if (on)
9ac79ba9	199	atomic_inc(&p->wakeup_path);
ab82fa7d	200	else
9ac79ba9	201	atomic_dec(&p->wakeup_path);
ab82fa7d GU	202
	203	return 0;
	204	}
	205
119f5e44 MD	206	static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
	207	{
	208	struct gpio_rcar_priv *p = dev_id;
	209	u32 pending;
	210	unsigned int offset, irqs_handled = 0;
	211
8808b64d VB	212	while ((pending = gpio_rcar_read(p, INTDT) &
8808b64d VB	213	gpio_rcar_read(p, INTMSK))) {
119f5e44 MD	214	offset = __ffs(pending);
119f5e44 MD	215	gpio_rcar_write(p, INTCLR, BIT(offset));
f0fbe7bc	216	generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
c7f3c5d3	217	offset));
119f5e44 MD	218	irqs_handled++;
	219	}
	220
	221	return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
	222	}
	223
119f5e44 MD	224	static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
	225	unsigned int gpio,
	226	bool output)
	227	{
c7b6f457	228	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
119f5e44 MD	229	unsigned long flags;
	230
	231	/* follow steps in the GPIO documentation for
	232	* "Setting General Output Mode" and
	233	* "Setting General Input Mode"
	234	*/
	235
	236	spin_lock_irqsave(&p->lock, flags);
	237
	238	/* Configure postive logic in POSNEG */
	239	gpio_rcar_modify_bit(p, POSNEG, gpio, false);
	240
	241	/* Select "General Input/Output Mode" in IOINTSEL */
	242	gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
	243
	244	/* Select Input Mode or Output Mode in INOUTSEL */
	245	gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
	246
	247	spin_unlock_irqrestore(&p->lock, flags);
	248	}
	249
dc3465a9 LP	250	static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
dc3465a9 LP	251	{
2d65472b GU	252	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	253	int error;
	254
	255	error = pm_runtime_get_sync(&p->pdev->dev);
	256	if (error < 0)
	257	return error;
	258
a9a1d2a7	259	error = pinctrl_gpio_request(chip->base + offset);
2d65472b GU	260	if (error)
	261	pm_runtime_put(&p->pdev->dev);
	262
	263	return error;
dc3465a9 LP	264	}
	265
	266	static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
	267	{
2d65472b GU	268	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
2d65472b GU	269
a9a1d2a7	270	pinctrl_gpio_free(chip->base + offset);
dc3465a9	271
ce0e2c60 LW	272	/*
ce0e2c60 LW	273	* Set the GPIO as an input to ensure that the next GPIO request won't
dc3465a9 LP	274	* drive the GPIO pin as an output.
	275	*/
	276	gpio_rcar_config_general_input_output_mode(chip, offset, false);
2d65472b GU	277
2d65472b GU	278	pm_runtime_put(&p->pdev->dev);
dc3465a9 LP	279	}
dc3465a9 LP	280
ad817297 GU	281	static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
	282	{
	283	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	284
	285	return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset));
	286	}
	287
119f5e44 MD	288	static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
	289	{
	290	gpio_rcar_config_general_input_output_mode(chip, offset, false);
	291	return 0;
	292	}
	293
	294	static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
	295	{
ae9550f6 MD	296	u32 bit = BIT(offset);
	297
	298	/* testing on r8a7790 shows that INDT does not show correct pin state
	299	* when configured as output, so use OUTDT in case of output pins */
c7b6f457 LW	300	if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
c7b6f457 LW	301	return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
ae9550f6	302	else
c7b6f457	303	return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
119f5e44 MD	304	}
	305
	306	static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
	307	{
c7b6f457	308	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
119f5e44 MD	309	unsigned long flags;
	310
	311	spin_lock_irqsave(&p->lock, flags);
	312	gpio_rcar_modify_bit(p, OUTDT, offset, value);
	313	spin_unlock_irqrestore(&p->lock, flags);
	314	}
	315
dbb763b8 GU	316	static void gpio_rcar_set_multiple(struct gpio_chip chip, unsigned long mask,
	317	unsigned long *bits)
	318	{
	319	struct gpio_rcar_priv *p = gpiochip_get_data(chip);
	320	unsigned long flags;
	321	u32 val, bankmask;
	322
	323	bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
496069b8 BD	324	if (chip->valid_mask)
	325	bankmask &= chip->valid_mask[0];
	326
dbb763b8 GU	327	if (!bankmask)
	328	return;
	329
	330	spin_lock_irqsave(&p->lock, flags);
	331	val = gpio_rcar_read(p, OUTDT);
	332	val &= ~bankmask;
	333	val \|= (bankmask & bits[0]);
	334	gpio_rcar_write(p, OUTDT, val);
	335	spin_unlock_irqrestore(&p->lock, flags);
	336	}
	337
119f5e44 MD	338	static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
	339	int value)
	340	{
	341	/* write GPIO value to output before selecting output mode of pin */
	342	gpio_rcar_set(chip, offset, value);
	343	gpio_rcar_config_general_input_output_mode(chip, offset, true);
	344	return 0;
	345	}
	346
850dfe17 LP	347	struct gpio_rcar_info {
	348	bool has_both_edge_trigger;
	349	};
	350
1fd2b49d HN	351	static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
	352	.has_both_edge_trigger = false,
	353	};
	354
	355	static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
	356	.has_both_edge_trigger = true,
	357	};
	358
850dfe17 LP	359	static const struct of_device_id gpio_rcar_of_table[] = {
850dfe17 LP	360	{
85bb4646 BD	361	.compatible = "renesas,gpio-r8a7743",
	362	/* RZ/G1 GPIO is identical to R-Car Gen2. */
	363	.data = &gpio_rcar_info_gen2,
	364	}, {
850dfe17	365	.compatible = "renesas,gpio-r8a7790",
1fd2b49d	366	.data = &gpio_rcar_info_gen2,
850dfe17 LP	367	}, {
850dfe17 LP	368	.compatible = "renesas,gpio-r8a7791",
1fd2b49d	369	.data = &gpio_rcar_info_gen2,
e79c5830 SS	370	}, {
	371	.compatible = "renesas,gpio-r8a7792",
	372	.data = &gpio_rcar_info_gen2,
1fd2b49d HN	373	}, {
	374	.compatible = "renesas,gpio-r8a7793",
	375	.data = &gpio_rcar_info_gen2,
	376	}, {
	377	.compatible = "renesas,gpio-r8a7794",
	378	.data = &gpio_rcar_info_gen2,
8cd14702 UH	379	}, {
	380	.compatible = "renesas,gpio-r8a7795",
	381	/* Gen3 GPIO is identical to Gen2. */
	382	.data = &gpio_rcar_info_gen2,
5d2f1d6e SH	383	}, {
	384	.compatible = "renesas,gpio-r8a7796",
	385	/* Gen3 GPIO is identical to Gen2. */
	386	.data = &gpio_rcar_info_gen2,
dbd1dad2 SH	387	}, {
	388	.compatible = "renesas,rcar-gen1-gpio",
	389	.data = &gpio_rcar_info_gen1,
	390	}, {
	391	.compatible = "renesas,rcar-gen2-gpio",
	392	.data = &gpio_rcar_info_gen2,
	393	}, {
	394	.compatible = "renesas,rcar-gen3-gpio",
	395	/* Gen3 GPIO is identical to Gen2. */
	396	.data = &gpio_rcar_info_gen2,
850dfe17 LP	397	}, {
850dfe17 LP	398	.compatible = "renesas,gpio-rcar",
1fd2b49d	399	.data = &gpio_rcar_info_gen1,
850dfe17 LP	400	}, {
	401	/* Terminator */
	402	},
	403	};
	404
	405	MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
	406
8b092be9	407	static int gpio_rcar_parse_dt(struct gpio_rcar_priv p, unsigned int npins)
159f8a02	408	{
159f8a02	409	struct device_node *np = p->pdev->dev.of_node;
8b092be9	410	const struct gpio_rcar_info *info;
159f8a02 LP	411	struct of_phandle_args args;
159f8a02 LP	412	int ret;
159f8a02	413
f9f2a6fe	414	info = of_device_get_match_data(&p->pdev->dev);
850dfe17	415
8b092be9 GU	416	ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
	417	*npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
	418	p->has_both_edge_trigger = info->has_both_edge_trigger;
850dfe17	419
8b092be9	420	if (npins == 0 \|\| npins > RCAR_MAX_GPIO_PER_BANK) {
159f8a02	421	dev_warn(&p->pdev->dev,
8b092be9 GU	422	"Invalid number of gpio lines %u, using %u\n", *npins,
	423	RCAR_MAX_GPIO_PER_BANK);
	424	*npins = RCAR_MAX_GPIO_PER_BANK;
159f8a02	425	}
850dfe17 LP	426
850dfe17 LP	427	return 0;
159f8a02 LP	428	}
159f8a02 LP	429
119f5e44 MD	430	static int gpio_rcar_probe(struct platform_device *pdev)
119f5e44 MD	431	{
119f5e44 MD	432	struct gpio_rcar_priv *p;
	433	struct resource io, irq;
	434	struct gpio_chip *gpio_chip;
	435	struct irq_chip *irq_chip;
b22978fc GU	436	struct device *dev = &pdev->dev;
b22978fc GU	437	const char *name = dev_name(dev);
8b092be9	438	unsigned int npins;
119f5e44 MD	439	int ret;
119f5e44 MD	440
b22978fc	441	p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
7d82bf34 GU	442	if (!p)
7d82bf34 GU	443	return -ENOMEM;
119f5e44	444
119f5e44	445	p->pdev = pdev;
119f5e44 MD	446	spin_lock_init(&p->lock);
119f5e44 MD	447
8b092be9 GU	448	/* Get device configuration from DT node */
8b092be9 GU	449	ret = gpio_rcar_parse_dt(p, &npins);
850dfe17 LP	450	if (ret < 0)
850dfe17 LP	451	return ret;
159f8a02 LP	452
	453	platform_set_drvdata(pdev, p);
	454
df0c6c80	455	pm_runtime_enable(dev);
df0c6c80	456
119f5e44	457	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
5a24d4b6 SS	458	if (!irq) {
5a24d4b6 SS	459	dev_err(dev, "missing IRQ\n");
119f5e44 MD	460	ret = -EINVAL;
	461	goto err0;
	462	}
	463
5a24d4b6 SS	464	io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	465	p->base = devm_ioremap_resource(dev, io);
	466	if (IS_ERR(p->base)) {
	467	ret = PTR_ERR(p->base);
119f5e44 MD	468	goto err0;
	469	}
	470
	471	gpio_chip = &p->gpio_chip;
dc3465a9 LP	472	gpio_chip->request = gpio_rcar_request;
dc3465a9 LP	473	gpio_chip->free = gpio_rcar_free;
ad817297	474	gpio_chip->get_direction = gpio_rcar_get_direction;
119f5e44 MD	475	gpio_chip->direction_input = gpio_rcar_direction_input;
	476	gpio_chip->get = gpio_rcar_get;
	477	gpio_chip->direction_output = gpio_rcar_direction_output;
	478	gpio_chip->set = gpio_rcar_set;
dbb763b8	479	gpio_chip->set_multiple = gpio_rcar_set_multiple;
119f5e44	480	gpio_chip->label = name;
58383c78	481	gpio_chip->parent = dev;
119f5e44	482	gpio_chip->owner = THIS_MODULE;
8b092be9 GU	483	gpio_chip->base = -1;
8b092be9 GU	484	gpio_chip->ngpio = npins;
119f5e44 MD	485
	486	irq_chip = &p->irq_chip;
	487	irq_chip->name = name;
47bd38a3	488	irq_chip->parent_device = dev;
119f5e44 MD	489	irq_chip->irq_mask = gpio_rcar_irq_disable;
119f5e44 MD	490	irq_chip->irq_unmask = gpio_rcar_irq_enable;
119f5e44	491	irq_chip->irq_set_type = gpio_rcar_irq_set_type;
ab82fa7d GU	492	irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
ab82fa7d GU	493	irq_chip->flags = IRQCHIP_SET_TYPE_MASKED \| IRQCHIP_MASK_ON_SUSPEND;
119f5e44	494
c7b6f457	495	ret = gpiochip_add_data(gpio_chip, p);
c7f3c5d3 GU	496	if (ret) {
c7f3c5d3 GU	497	dev_err(dev, "failed to add GPIO controller\n");
0c8aab8e	498	goto err0;
119f5e44 MD	499	}
119f5e44 MD	500
8b092be9 GU	501	ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
8b092be9 GU	502	IRQ_TYPE_NONE);
c7f3c5d3 GU	503	if (ret) {
	504	dev_err(dev, "cannot add irqchip\n");
	505	goto err1;
	506	}
	507
ab82fa7d	508	p->irq_parent = irq->start;
b22978fc GU	509	if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
	510	IRQF_SHARED, name, p)) {
	511	dev_err(dev, "failed to request IRQ\n");
119f5e44 MD	512	ret = -ENOENT;
	513	goto err1;
	514	}
	515
8b092be9	516	dev_info(dev, "driving %d GPIOs\n", npins);
dc3465a9	517
119f5e44 MD	518	return 0;
	519
	520	err1:
4d84b9e4	521	gpiochip_remove(gpio_chip);
119f5e44	522	err0:
df0c6c80	523	pm_runtime_disable(dev);
119f5e44 MD	524	return ret;
	525	}
	526
	527	static int gpio_rcar_remove(struct platform_device *pdev)
	528	{
	529	struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
119f5e44	530
9f5132ae	531	gpiochip_remove(&p->gpio_chip);
119f5e44	532
df0c6c80	533	pm_runtime_disable(&pdev->dev);
119f5e44 MD	534	return 0;
	535	}
	536
51750fb1 HD	537	#ifdef CONFIG_PM_SLEEP
	538	static int gpio_rcar_suspend(struct device *dev)
	539	{
	540	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
	541
	542	p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
	543	p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
	544	p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
	545	p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
	546	p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
	547	p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
	548	if (p->has_both_edge_trigger)
	549	p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
	550
9ac79ba9 GU	551	if (atomic_read(&p->wakeup_path))
	552	device_set_wakeup_path(dev);
	553
51750fb1 HD	554	return 0;
	555	}
	556
	557	static int gpio_rcar_resume(struct device *dev)
	558	{
	559	struct gpio_rcar_priv *p = dev_get_drvdata(dev);
	560	unsigned int offset;
	561	u32 mask;
	562
	563	for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
496069b8 BD	564	if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
	565	continue;
	566
51750fb1 HD	567	mask = BIT(offset);
	568	/* I/O pin */
	569	if (!(p->bank_info.iointsel & mask)) {
	570	if (p->bank_info.inoutsel & mask)
	571	gpio_rcar_direction_output(
	572	&p->gpio_chip, offset,
	573	!!(p->bank_info.outdt & mask));
	574	else
	575	gpio_rcar_direction_input(&p->gpio_chip,
	576	offset);
	577	} else {
	578	/* Interrupt pin */
	579	gpio_rcar_config_interrupt_input_mode(
	580	p,
	581	offset,
	582	!(p->bank_info.posneg & mask),
	583	!(p->bank_info.edglevel & mask),
	584	!!(p->bank_info.bothedge & mask));
	585
	586	if (p->bank_info.intmsk & mask)
	587	gpio_rcar_write(p, MSKCLR, mask);
	588	}
	589	}
	590
	591	return 0;
	592	}
	593	#endif /* CONFIG_PM_SLEEP*/
	594
	595	static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
	596
119f5e44 MD	597	static struct platform_driver gpio_rcar_device_driver = {
	598	.probe = gpio_rcar_probe,
	599	.remove = gpio_rcar_remove,
	600	.driver = {
	601	.name = "gpio_rcar",
51750fb1	602	.pm = &gpio_rcar_pm_ops,
159f8a02	603	.of_match_table = of_match_ptr(gpio_rcar_of_table),
119f5e44 MD	604	}
	605	};
	606
	607	module_platform_driver(gpio_rcar_device_driver);
	608
	609	MODULE_AUTHOR("Magnus Damm");
	610	MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
	611	MODULE_LICENSE("GPL v2");