Commit | Line | Data |
---|---|---|
1e9c2859 | 1 | /* |
c103de24 | 2 | * Copyright (C) 2008, 2009 Provigent Ltd. |
1e9c2859 BS |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061) | |
9 | * | |
10 | * Data sheet: ARM DDI 0190B, September 2000 | |
11 | */ | |
12 | #include <linux/spinlock.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/module.h> | |
1e9c2859 BS |
15 | #include <linux/io.h> |
16 | #include <linux/ioport.h> | |
17 | #include <linux/irq.h> | |
f1f70479 | 18 | #include <linux/irqdomain.h> |
de88cbb7 | 19 | #include <linux/irqchip/chained_irq.h> |
1e9c2859 BS |
20 | #include <linux/bitops.h> |
21 | #include <linux/workqueue.h> | |
22 | #include <linux/gpio.h> | |
23 | #include <linux/device.h> | |
24 | #include <linux/amba/bus.h> | |
25 | #include <linux/amba/pl061.h> | |
5a0e3ad6 | 26 | #include <linux/slab.h> |
39b70ee0 | 27 | #include <linux/pinctrl/consumer.h> |
e198a8de | 28 | #include <linux/pm.h> |
1e9c2859 BS |
29 | |
30 | #define GPIODIR 0x400 | |
31 | #define GPIOIS 0x404 | |
32 | #define GPIOIBE 0x408 | |
33 | #define GPIOIEV 0x40C | |
34 | #define GPIOIE 0x410 | |
35 | #define GPIORIS 0x414 | |
36 | #define GPIOMIS 0x418 | |
37 | #define GPIOIC 0x41C | |
38 | ||
39 | #define PL061_GPIO_NR 8 | |
40 | ||
e198a8de DS |
41 | #ifdef CONFIG_PM |
42 | struct pl061_context_save_regs { | |
43 | u8 gpio_data; | |
44 | u8 gpio_dir; | |
45 | u8 gpio_is; | |
46 | u8 gpio_ibe; | |
47 | u8 gpio_iev; | |
48 | u8 gpio_ie; | |
49 | }; | |
50 | #endif | |
1e9c2859 | 51 | |
1e9c2859 | 52 | struct pl061_gpio { |
835c192f | 53 | spinlock_t lock; |
1e9c2859 BS |
54 | |
55 | void __iomem *base; | |
f1f70479 | 56 | struct irq_domain *domain; |
1e9c2859 | 57 | struct gpio_chip gc; |
e198a8de DS |
58 | |
59 | #ifdef CONFIG_PM | |
60 | struct pl061_context_save_regs csave_regs; | |
61 | #endif | |
1e9c2859 BS |
62 | }; |
63 | ||
39b70ee0 HZ |
64 | static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset) |
65 | { | |
66 | /* | |
67 | * Map back to global GPIO space and request muxing, the direction | |
68 | * parameter does not matter for this controller. | |
69 | */ | |
70 | int gpio = chip->base + offset; | |
71 | ||
72 | return pinctrl_request_gpio(gpio); | |
73 | } | |
74 | ||
22ce4464 AL |
75 | static void pl061_gpio_free(struct gpio_chip *chip, unsigned offset) |
76 | { | |
77 | int gpio = chip->base + offset; | |
78 | ||
79 | pinctrl_free_gpio(gpio); | |
80 | } | |
81 | ||
1e9c2859 BS |
82 | static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) |
83 | { | |
84 | struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); | |
85 | unsigned long flags; | |
86 | unsigned char gpiodir; | |
87 | ||
88 | if (offset >= gc->ngpio) | |
89 | return -EINVAL; | |
90 | ||
91 | spin_lock_irqsave(&chip->lock, flags); | |
92 | gpiodir = readb(chip->base + GPIODIR); | |
93 | gpiodir &= ~(1 << offset); | |
94 | writeb(gpiodir, chip->base + GPIODIR); | |
95 | spin_unlock_irqrestore(&chip->lock, flags); | |
96 | ||
97 | return 0; | |
98 | } | |
99 | ||
100 | static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, | |
101 | int value) | |
102 | { | |
103 | struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); | |
104 | unsigned long flags; | |
105 | unsigned char gpiodir; | |
106 | ||
107 | if (offset >= gc->ngpio) | |
108 | return -EINVAL; | |
109 | ||
110 | spin_lock_irqsave(&chip->lock, flags); | |
111 | writeb(!!value << offset, chip->base + (1 << (offset + 2))); | |
112 | gpiodir = readb(chip->base + GPIODIR); | |
113 | gpiodir |= 1 << offset; | |
114 | writeb(gpiodir, chip->base + GPIODIR); | |
64b997c5 | 115 | |
116 | /* | |
117 | * gpio value is set again, because pl061 doesn't allow to set value of | |
118 | * a gpio pin before configuring it in OUT mode. | |
119 | */ | |
120 | writeb(!!value << offset, chip->base + (1 << (offset + 2))); | |
1e9c2859 BS |
121 | spin_unlock_irqrestore(&chip->lock, flags); |
122 | ||
123 | return 0; | |
124 | } | |
125 | ||
126 | static int pl061_get_value(struct gpio_chip *gc, unsigned offset) | |
127 | { | |
128 | struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); | |
129 | ||
130 | return !!readb(chip->base + (1 << (offset + 2))); | |
131 | } | |
132 | ||
133 | static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value) | |
134 | { | |
135 | struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); | |
136 | ||
137 | writeb(!!value << offset, chip->base + (1 << (offset + 2))); | |
138 | } | |
139 | ||
50efacf6 BS |
140 | static int pl061_to_irq(struct gpio_chip *gc, unsigned offset) |
141 | { | |
142 | struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); | |
143 | ||
f1f70479 | 144 | return irq_create_mapping(chip->domain, offset); |
50efacf6 BS |
145 | } |
146 | ||
b2221869 | 147 | static int pl061_irq_type(struct irq_data *d, unsigned trigger) |
1e9c2859 | 148 | { |
f1f70479 HZ |
149 | struct pl061_gpio *chip = irq_data_get_irq_chip_data(d); |
150 | int offset = irqd_to_hwirq(d); | |
1e9c2859 BS |
151 | unsigned long flags; |
152 | u8 gpiois, gpioibe, gpioiev; | |
153 | ||
c1cc9b97 | 154 | if (offset < 0 || offset >= PL061_GPIO_NR) |
1e9c2859 BS |
155 | return -EINVAL; |
156 | ||
f1f70479 | 157 | spin_lock_irqsave(&chip->lock, flags); |
1e9c2859 BS |
158 | |
159 | gpioiev = readb(chip->base + GPIOIEV); | |
160 | ||
161 | gpiois = readb(chip->base + GPIOIS); | |
162 | if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { | |
163 | gpiois |= 1 << offset; | |
164 | if (trigger & IRQ_TYPE_LEVEL_HIGH) | |
165 | gpioiev |= 1 << offset; | |
166 | else | |
167 | gpioiev &= ~(1 << offset); | |
168 | } else | |
169 | gpiois &= ~(1 << offset); | |
170 | writeb(gpiois, chip->base + GPIOIS); | |
171 | ||
172 | gpioibe = readb(chip->base + GPIOIBE); | |
173 | if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) | |
174 | gpioibe |= 1 << offset; | |
175 | else { | |
176 | gpioibe &= ~(1 << offset); | |
177 | if (trigger & IRQ_TYPE_EDGE_RISING) | |
178 | gpioiev |= 1 << offset; | |
db7e1bc4 | 179 | else if (trigger & IRQ_TYPE_EDGE_FALLING) |
1e9c2859 BS |
180 | gpioiev &= ~(1 << offset); |
181 | } | |
182 | writeb(gpioibe, chip->base + GPIOIBE); | |
183 | ||
184 | writeb(gpioiev, chip->base + GPIOIEV); | |
185 | ||
f1f70479 | 186 | spin_unlock_irqrestore(&chip->lock, flags); |
1e9c2859 BS |
187 | |
188 | return 0; | |
189 | } | |
190 | ||
1e9c2859 BS |
191 | static void pl061_irq_handler(unsigned irq, struct irq_desc *desc) |
192 | { | |
2de0dbc5 RH |
193 | unsigned long pending; |
194 | int offset; | |
195 | struct pl061_gpio *chip = irq_desc_get_handler_data(desc); | |
dece904d | 196 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
1e9c2859 | 197 | |
dece904d | 198 | chained_irq_enter(irqchip, desc); |
1e9c2859 | 199 | |
2de0dbc5 RH |
200 | pending = readb(chip->base + GPIOMIS); |
201 | writeb(pending, chip->base + GPIOIC); | |
202 | if (pending) { | |
984b3f57 | 203 | for_each_set_bit(offset, &pending, PL061_GPIO_NR) |
50efacf6 | 204 | generic_handle_irq(pl061_to_irq(&chip->gc, offset)); |
1e9c2859 | 205 | } |
2de0dbc5 | 206 | |
dece904d | 207 | chained_irq_exit(irqchip, desc); |
1e9c2859 BS |
208 | } |
209 | ||
f1f70479 | 210 | static void pl061_irq_mask(struct irq_data *d) |
3ab52475 | 211 | { |
f1f70479 HZ |
212 | struct pl061_gpio *chip = irq_data_get_irq_chip_data(d); |
213 | u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR); | |
214 | u8 gpioie; | |
215 | ||
216 | spin_lock(&chip->lock); | |
217 | gpioie = readb(chip->base + GPIOIE) & ~mask; | |
218 | writeb(gpioie, chip->base + GPIOIE); | |
219 | spin_unlock(&chip->lock); | |
220 | } | |
3ab52475 | 221 | |
f1f70479 HZ |
222 | static void pl061_irq_unmask(struct irq_data *d) |
223 | { | |
224 | struct pl061_gpio *chip = irq_data_get_irq_chip_data(d); | |
225 | u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR); | |
226 | u8 gpioie; | |
227 | ||
228 | spin_lock(&chip->lock); | |
229 | gpioie = readb(chip->base + GPIOIE) | mask; | |
230 | writeb(gpioie, chip->base + GPIOIE); | |
231 | spin_unlock(&chip->lock); | |
232 | } | |
233 | ||
234 | static struct irq_chip pl061_irqchip = { | |
235 | .name = "pl061 gpio", | |
236 | .irq_mask = pl061_irq_mask, | |
237 | .irq_unmask = pl061_irq_unmask, | |
238 | .irq_set_type = pl061_irq_type, | |
239 | }; | |
240 | ||
f8f669f7 LW |
241 | static int pl061_irq_map(struct irq_domain *d, unsigned int irq, |
242 | irq_hw_number_t hwirq) | |
f1f70479 HZ |
243 | { |
244 | struct pl061_gpio *chip = d->host_data; | |
3ab52475 | 245 | |
f8f669f7 | 246 | irq_set_chip_and_handler_name(irq, &pl061_irqchip, handle_simple_irq, |
f1f70479 | 247 | "pl061"); |
f8f669f7 LW |
248 | irq_set_chip_data(irq, chip); |
249 | irq_set_irq_type(irq, IRQ_TYPE_NONE); | |
3ab52475 | 250 | |
f1f70479 | 251 | return 0; |
1e9c2859 BS |
252 | } |
253 | ||
f1f70479 HZ |
254 | static const struct irq_domain_ops pl061_domain_ops = { |
255 | .map = pl061_irq_map, | |
256 | .xlate = irq_domain_xlate_twocell, | |
257 | }; | |
258 | ||
8944df72 | 259 | static int pl061_probe(struct amba_device *adev, const struct amba_id *id) |
1e9c2859 | 260 | { |
8944df72 | 261 | struct device *dev = &adev->dev; |
e56aee18 | 262 | struct pl061_platform_data *pdata = dev_get_platdata(dev); |
1e9c2859 | 263 | struct pl061_gpio *chip; |
f1f70479 | 264 | int ret, irq, i, irq_base; |
1e9c2859 | 265 | |
8944df72 | 266 | chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); |
1e9c2859 BS |
267 | if (chip == NULL) |
268 | return -ENOMEM; | |
269 | ||
76c05c8a RH |
270 | if (pdata) { |
271 | chip->gc.base = pdata->gpio_base; | |
f1f70479 HZ |
272 | irq_base = pdata->irq_base; |
273 | if (irq_base <= 0) | |
274 | return -ENODEV; | |
275 | } else { | |
76c05c8a | 276 | chip->gc.base = -1; |
f1f70479 HZ |
277 | irq_base = 0; |
278 | } | |
76c05c8a | 279 | |
8944df72 | 280 | if (!devm_request_mem_region(dev, adev->res.start, |
f1f70479 | 281 | resource_size(&adev->res), "pl061")) |
8944df72 | 282 | return -EBUSY; |
1e9c2859 | 283 | |
8944df72 | 284 | chip->base = devm_ioremap(dev, adev->res.start, |
f1f70479 HZ |
285 | resource_size(&adev->res)); |
286 | if (!chip->base) | |
8944df72 | 287 | return -ENOMEM; |
1e9c2859 BS |
288 | |
289 | spin_lock_init(&chip->lock); | |
1e9c2859 | 290 | |
39b70ee0 | 291 | chip->gc.request = pl061_gpio_request; |
22ce4464 | 292 | chip->gc.free = pl061_gpio_free; |
1e9c2859 BS |
293 | chip->gc.direction_input = pl061_direction_input; |
294 | chip->gc.direction_output = pl061_direction_output; | |
295 | chip->gc.get = pl061_get_value; | |
296 | chip->gc.set = pl061_set_value; | |
50efacf6 | 297 | chip->gc.to_irq = pl061_to_irq; |
1e9c2859 | 298 | chip->gc.ngpio = PL061_GPIO_NR; |
8944df72 TK |
299 | chip->gc.label = dev_name(dev); |
300 | chip->gc.dev = dev; | |
1e9c2859 BS |
301 | chip->gc.owner = THIS_MODULE; |
302 | ||
1e9c2859 BS |
303 | ret = gpiochip_add(&chip->gc); |
304 | if (ret) | |
8944df72 | 305 | return ret; |
1e9c2859 BS |
306 | |
307 | /* | |
308 | * irq_chip support | |
309 | */ | |
1e9c2859 | 310 | writeb(0, chip->base + GPIOIE); /* disable irqs */ |
8944df72 TK |
311 | irq = adev->irq[0]; |
312 | if (irq < 0) | |
313 | return -ENODEV; | |
314 | ||
b51804bc | 315 | irq_set_chained_handler(irq, pl061_irq_handler); |
2de0dbc5 | 316 | irq_set_handler_data(irq, chip); |
1e9c2859 | 317 | |
2ba3154d LW |
318 | chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR, |
319 | irq_base, &pl061_domain_ops, chip); | |
320 | if (!chip->domain) | |
321 | return -ENODEV; | |
322 | ||
1e9c2859 | 323 | for (i = 0; i < PL061_GPIO_NR; i++) { |
76c05c8a RH |
324 | if (pdata) { |
325 | if (pdata->directions & (1 << i)) | |
326 | pl061_direction_output(&chip->gc, i, | |
327 | pdata->values & (1 << i)); | |
328 | else | |
329 | pl061_direction_input(&chip->gc, i); | |
330 | } | |
1e9c2859 BS |
331 | } |
332 | ||
8944df72 | 333 | amba_set_drvdata(adev, chip); |
e198a8de | 334 | |
1e9c2859 | 335 | return 0; |
1e9c2859 BS |
336 | } |
337 | ||
e198a8de DS |
338 | #ifdef CONFIG_PM |
339 | static int pl061_suspend(struct device *dev) | |
340 | { | |
341 | struct pl061_gpio *chip = dev_get_drvdata(dev); | |
342 | int offset; | |
343 | ||
344 | chip->csave_regs.gpio_data = 0; | |
345 | chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR); | |
346 | chip->csave_regs.gpio_is = readb(chip->base + GPIOIS); | |
347 | chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE); | |
348 | chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV); | |
349 | chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE); | |
350 | ||
351 | for (offset = 0; offset < PL061_GPIO_NR; offset++) { | |
352 | if (chip->csave_regs.gpio_dir & (1 << offset)) | |
353 | chip->csave_regs.gpio_data |= | |
354 | pl061_get_value(&chip->gc, offset) << offset; | |
355 | } | |
356 | ||
357 | return 0; | |
358 | } | |
359 | ||
360 | static int pl061_resume(struct device *dev) | |
361 | { | |
362 | struct pl061_gpio *chip = dev_get_drvdata(dev); | |
363 | int offset; | |
364 | ||
365 | for (offset = 0; offset < PL061_GPIO_NR; offset++) { | |
366 | if (chip->csave_regs.gpio_dir & (1 << offset)) | |
367 | pl061_direction_output(&chip->gc, offset, | |
368 | chip->csave_regs.gpio_data & | |
369 | (1 << offset)); | |
370 | else | |
371 | pl061_direction_input(&chip->gc, offset); | |
372 | } | |
373 | ||
374 | writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS); | |
375 | writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE); | |
376 | writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV); | |
377 | writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE); | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
6e33aced VK |
382 | static const struct dev_pm_ops pl061_dev_pm_ops = { |
383 | .suspend = pl061_suspend, | |
384 | .resume = pl061_resume, | |
385 | .freeze = pl061_suspend, | |
386 | .restore = pl061_resume, | |
387 | }; | |
e198a8de DS |
388 | #endif |
389 | ||
2c39c9e1 | 390 | static struct amba_id pl061_ids[] = { |
1e9c2859 BS |
391 | { |
392 | .id = 0x00041061, | |
393 | .mask = 0x000fffff, | |
394 | }, | |
395 | { 0, 0 }, | |
396 | }; | |
397 | ||
955b678c DM |
398 | MODULE_DEVICE_TABLE(amba, pl061_ids); |
399 | ||
1e9c2859 BS |
400 | static struct amba_driver pl061_gpio_driver = { |
401 | .drv = { | |
402 | .name = "pl061_gpio", | |
e198a8de DS |
403 | #ifdef CONFIG_PM |
404 | .pm = &pl061_dev_pm_ops, | |
405 | #endif | |
1e9c2859 BS |
406 | }, |
407 | .id_table = pl061_ids, | |
408 | .probe = pl061_probe, | |
409 | }; | |
410 | ||
411 | static int __init pl061_gpio_init(void) | |
412 | { | |
413 | return amba_driver_register(&pl061_gpio_driver); | |
414 | } | |
5985d76c | 415 | module_init(pl061_gpio_init); |
1e9c2859 BS |
416 | |
417 | MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>"); | |
418 | MODULE_DESCRIPTION("PL061 GPIO driver"); | |
419 | MODULE_LICENSE("GPL"); |