Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1e9c2859 | 2 | /* |
c103de24 | 3 | * Copyright (C) 2008, 2009 Provigent Ltd. |
1e9c2859 | 4 | * |
ef3e7100 PG |
5 | * Author: Baruch Siach <baruch@tkos.co.il> |
6 | * | |
1e9c2859 BS |
7 | * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061) |
8 | * | |
9 | * Data sheet: ARM DDI 0190B, September 2000 | |
10 | */ | |
11 | #include <linux/spinlock.h> | |
12 | #include <linux/errno.h> | |
ef3e7100 | 13 | #include <linux/init.h> |
1e9c2859 BS |
14 | #include <linux/io.h> |
15 | #include <linux/ioport.h> | |
2f46205b | 16 | #include <linux/interrupt.h> |
1e9c2859 | 17 | #include <linux/irq.h> |
de88cbb7 | 18 | #include <linux/irqchip/chained_irq.h> |
1e9c2859 | 19 | #include <linux/bitops.h> |
dcc6ceef | 20 | #include <linux/gpio/driver.h> |
1e9c2859 BS |
21 | #include <linux/device.h> |
22 | #include <linux/amba/bus.h> | |
5a0e3ad6 | 23 | #include <linux/slab.h> |
39b70ee0 | 24 | #include <linux/pinctrl/consumer.h> |
e198a8de | 25 | #include <linux/pm.h> |
1e9c2859 BS |
26 | |
27 | #define GPIODIR 0x400 | |
28 | #define GPIOIS 0x404 | |
29 | #define GPIOIBE 0x408 | |
30 | #define GPIOIEV 0x40C | |
31 | #define GPIOIE 0x410 | |
32 | #define GPIORIS 0x414 | |
33 | #define GPIOMIS 0x418 | |
34 | #define GPIOIC 0x41C | |
35 | ||
36 | #define PL061_GPIO_NR 8 | |
37 | ||
e198a8de DS |
38 | #ifdef CONFIG_PM |
39 | struct pl061_context_save_regs { | |
40 | u8 gpio_data; | |
41 | u8 gpio_dir; | |
42 | u8 gpio_is; | |
43 | u8 gpio_ibe; | |
44 | u8 gpio_iev; | |
45 | u8 gpio_ie; | |
46 | }; | |
47 | #endif | |
1e9c2859 | 48 | |
538f76c5 | 49 | struct pl061 { |
99b9b45d | 50 | raw_spinlock_t lock; |
1e9c2859 BS |
51 | |
52 | void __iomem *base; | |
1e9c2859 | 53 | struct gpio_chip gc; |
ed8dce4c | 54 | struct irq_chip irq_chip; |
9c18be8e | 55 | int parent_irq; |
e198a8de DS |
56 | |
57 | #ifdef CONFIG_PM | |
58 | struct pl061_context_save_regs csave_regs; | |
59 | #endif | |
1e9c2859 BS |
60 | }; |
61 | ||
3484f1be LW |
62 | static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) |
63 | { | |
2796325f | 64 | struct pl061 *pl061 = gpiochip_get_data(gc); |
3484f1be | 65 | |
e42615ec MV |
66 | if (readb(pl061->base + GPIODIR) & BIT(offset)) |
67 | return GPIO_LINE_DIRECTION_OUT; | |
68 | ||
69 | return GPIO_LINE_DIRECTION_IN; | |
3484f1be LW |
70 | } |
71 | ||
1e9c2859 BS |
72 | static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) |
73 | { | |
2796325f | 74 | struct pl061 *pl061 = gpiochip_get_data(gc); |
1e9c2859 BS |
75 | unsigned long flags; |
76 | unsigned char gpiodir; | |
77 | ||
99b9b45d | 78 | raw_spin_lock_irqsave(&pl061->lock, flags); |
2796325f | 79 | gpiodir = readb(pl061->base + GPIODIR); |
bea41504 | 80 | gpiodir &= ~(BIT(offset)); |
2796325f | 81 | writeb(gpiodir, pl061->base + GPIODIR); |
99b9b45d | 82 | raw_spin_unlock_irqrestore(&pl061->lock, flags); |
1e9c2859 BS |
83 | |
84 | return 0; | |
85 | } | |
86 | ||
87 | static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, | |
88 | int value) | |
89 | { | |
2796325f | 90 | struct pl061 *pl061 = gpiochip_get_data(gc); |
1e9c2859 BS |
91 | unsigned long flags; |
92 | unsigned char gpiodir; | |
93 | ||
99b9b45d | 94 | raw_spin_lock_irqsave(&pl061->lock, flags); |
2796325f LW |
95 | writeb(!!value << offset, pl061->base + (BIT(offset + 2))); |
96 | gpiodir = readb(pl061->base + GPIODIR); | |
bea41504 | 97 | gpiodir |= BIT(offset); |
2796325f | 98 | writeb(gpiodir, pl061->base + GPIODIR); |
64b997c5 | 99 | |
100 | /* | |
101 | * gpio value is set again, because pl061 doesn't allow to set value of | |
102 | * a gpio pin before configuring it in OUT mode. | |
103 | */ | |
2796325f | 104 | writeb(!!value << offset, pl061->base + (BIT(offset + 2))); |
99b9b45d | 105 | raw_spin_unlock_irqrestore(&pl061->lock, flags); |
1e9c2859 BS |
106 | |
107 | return 0; | |
108 | } | |
109 | ||
110 | static int pl061_get_value(struct gpio_chip *gc, unsigned offset) | |
111 | { | |
2796325f | 112 | struct pl061 *pl061 = gpiochip_get_data(gc); |
1e9c2859 | 113 | |
2796325f | 114 | return !!readb(pl061->base + (BIT(offset + 2))); |
1e9c2859 BS |
115 | } |
116 | ||
117 | static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value) | |
118 | { | |
2796325f | 119 | struct pl061 *pl061 = gpiochip_get_data(gc); |
1e9c2859 | 120 | |
2796325f | 121 | writeb(!!value << offset, pl061->base + (BIT(offset + 2))); |
1e9c2859 BS |
122 | } |
123 | ||
b2221869 | 124 | static int pl061_irq_type(struct irq_data *d, unsigned trigger) |
1e9c2859 | 125 | { |
8d5b24bd | 126 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
2796325f | 127 | struct pl061 *pl061 = gpiochip_get_data(gc); |
f1f70479 | 128 | int offset = irqd_to_hwirq(d); |
1e9c2859 BS |
129 | unsigned long flags; |
130 | u8 gpiois, gpioibe, gpioiev; | |
438a2c9a | 131 | u8 bit = BIT(offset); |
1e9c2859 | 132 | |
c1cc9b97 | 133 | if (offset < 0 || offset >= PL061_GPIO_NR) |
1e9c2859 BS |
134 | return -EINVAL; |
135 | ||
1dbf7f29 LW |
136 | if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) && |
137 | (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) | |
138 | { | |
58383c78 | 139 | dev_err(gc->parent, |
1dbf7f29 LW |
140 | "trying to configure line %d for both level and edge " |
141 | "detection, choose one!\n", | |
142 | offset); | |
143 | return -EINVAL; | |
144 | } | |
145 | ||
21d4de14 | 146 | |
99b9b45d | 147 | raw_spin_lock_irqsave(&pl061->lock, flags); |
21d4de14 | 148 | |
2796325f LW |
149 | gpioiev = readb(pl061->base + GPIOIEV); |
150 | gpiois = readb(pl061->base + GPIOIS); | |
151 | gpioibe = readb(pl061->base + GPIOIBE); | |
21d4de14 | 152 | |
1e9c2859 | 153 | if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
1dbf7f29 LW |
154 | bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH; |
155 | ||
156 | /* Disable edge detection */ | |
157 | gpioibe &= ~bit; | |
158 | /* Enable level detection */ | |
438a2c9a | 159 | gpiois |= bit; |
1dbf7f29 LW |
160 | /* Select polarity */ |
161 | if (polarity) | |
438a2c9a | 162 | gpioiev |= bit; |
1e9c2859 | 163 | else |
438a2c9a | 164 | gpioiev &= ~bit; |
26ba9cd4 | 165 | irq_set_handler_locked(d, handle_level_irq); |
58383c78 | 166 | dev_dbg(gc->parent, "line %d: IRQ on %s level\n", |
1dbf7f29 LW |
167 | offset, |
168 | polarity ? "HIGH" : "LOW"); | |
169 | } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
170 | /* Disable level detection */ | |
171 | gpiois &= ~bit; | |
172 | /* Select both edges, setting this makes GPIOEV be ignored */ | |
438a2c9a | 173 | gpioibe |= bit; |
26ba9cd4 | 174 | irq_set_handler_locked(d, handle_edge_irq); |
58383c78 | 175 | dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset); |
1dbf7f29 LW |
176 | } else if ((trigger & IRQ_TYPE_EDGE_RISING) || |
177 | (trigger & IRQ_TYPE_EDGE_FALLING)) { | |
178 | bool rising = trigger & IRQ_TYPE_EDGE_RISING; | |
179 | ||
180 | /* Disable level detection */ | |
181 | gpiois &= ~bit; | |
182 | /* Clear detection on both edges */ | |
438a2c9a | 183 | gpioibe &= ~bit; |
1dbf7f29 LW |
184 | /* Select edge */ |
185 | if (rising) | |
438a2c9a | 186 | gpioiev |= bit; |
1dbf7f29 | 187 | else |
438a2c9a | 188 | gpioiev &= ~bit; |
26ba9cd4 | 189 | irq_set_handler_locked(d, handle_edge_irq); |
58383c78 | 190 | dev_dbg(gc->parent, "line %d: IRQ on %s edge\n", |
1dbf7f29 LW |
191 | offset, |
192 | rising ? "RISING" : "FALLING"); | |
193 | } else { | |
194 | /* No trigger: disable everything */ | |
195 | gpiois &= ~bit; | |
196 | gpioibe &= ~bit; | |
197 | gpioiev &= ~bit; | |
26ba9cd4 | 198 | irq_set_handler_locked(d, handle_bad_irq); |
58383c78 | 199 | dev_warn(gc->parent, "no trigger selected for line %d\n", |
1dbf7f29 | 200 | offset); |
1e9c2859 | 201 | } |
1e9c2859 | 202 | |
2796325f LW |
203 | writeb(gpiois, pl061->base + GPIOIS); |
204 | writeb(gpioibe, pl061->base + GPIOIBE); | |
205 | writeb(gpioiev, pl061->base + GPIOIEV); | |
1e9c2859 | 206 | |
99b9b45d | 207 | raw_spin_unlock_irqrestore(&pl061->lock, flags); |
1e9c2859 BS |
208 | |
209 | return 0; | |
210 | } | |
211 | ||
bd0b9ac4 | 212 | static void pl061_irq_handler(struct irq_desc *desc) |
1e9c2859 | 213 | { |
2de0dbc5 RH |
214 | unsigned long pending; |
215 | int offset; | |
8d5b24bd | 216 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
2796325f | 217 | struct pl061 *pl061 = gpiochip_get_data(gc); |
dece904d | 218 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
1e9c2859 | 219 | |
dece904d | 220 | chained_irq_enter(irqchip, desc); |
1e9c2859 | 221 | |
2796325f | 222 | pending = readb(pl061->base + GPIOMIS); |
2de0dbc5 | 223 | if (pending) { |
984b3f57 | 224 | for_each_set_bit(offset, &pending, PL061_GPIO_NR) |
f0fbe7bc | 225 | generic_handle_irq(irq_find_mapping(gc->irq.domain, |
8d5b24bd | 226 | offset)); |
1e9c2859 | 227 | } |
2de0dbc5 | 228 | |
dece904d | 229 | chained_irq_exit(irqchip, desc); |
1e9c2859 BS |
230 | } |
231 | ||
f1f70479 | 232 | static void pl061_irq_mask(struct irq_data *d) |
3ab52475 | 233 | { |
8d5b24bd | 234 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
2796325f | 235 | struct pl061 *pl061 = gpiochip_get_data(gc); |
bea41504 | 236 | u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); |
f1f70479 HZ |
237 | u8 gpioie; |
238 | ||
99b9b45d | 239 | raw_spin_lock(&pl061->lock); |
2796325f LW |
240 | gpioie = readb(pl061->base + GPIOIE) & ~mask; |
241 | writeb(gpioie, pl061->base + GPIOIE); | |
99b9b45d | 242 | raw_spin_unlock(&pl061->lock); |
f1f70479 | 243 | } |
3ab52475 | 244 | |
f1f70479 HZ |
245 | static void pl061_irq_unmask(struct irq_data *d) |
246 | { | |
8d5b24bd | 247 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
2796325f | 248 | struct pl061 *pl061 = gpiochip_get_data(gc); |
bea41504 | 249 | u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); |
f1f70479 HZ |
250 | u8 gpioie; |
251 | ||
99b9b45d | 252 | raw_spin_lock(&pl061->lock); |
2796325f LW |
253 | gpioie = readb(pl061->base + GPIOIE) | mask; |
254 | writeb(gpioie, pl061->base + GPIOIE); | |
99b9b45d | 255 | raw_spin_unlock(&pl061->lock); |
f1f70479 HZ |
256 | } |
257 | ||
26ba9cd4 LW |
258 | /** |
259 | * pl061_irq_ack() - ACK an edge IRQ | |
260 | * @d: IRQ data for this IRQ | |
261 | * | |
262 | * This gets called from the edge IRQ handler to ACK the edge IRQ | |
263 | * in the GPIOIC (interrupt-clear) register. For level IRQs this is | |
264 | * not needed: these go away when the level signal goes away. | |
265 | */ | |
266 | static void pl061_irq_ack(struct irq_data *d) | |
267 | { | |
268 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
2796325f | 269 | struct pl061 *pl061 = gpiochip_get_data(gc); |
26ba9cd4 LW |
270 | u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); |
271 | ||
99b9b45d | 272 | raw_spin_lock(&pl061->lock); |
2796325f | 273 | writeb(mask, pl061->base + GPIOIC); |
99b9b45d | 274 | raw_spin_unlock(&pl061->lock); |
26ba9cd4 LW |
275 | } |
276 | ||
2f46205b SH |
277 | static int pl061_irq_set_wake(struct irq_data *d, unsigned int state) |
278 | { | |
279 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
2796325f | 280 | struct pl061 *pl061 = gpiochip_get_data(gc); |
2f46205b | 281 | |
2796325f | 282 | return irq_set_irq_wake(pl061->parent_irq, state); |
2f46205b SH |
283 | } |
284 | ||
8944df72 | 285 | static int pl061_probe(struct amba_device *adev, const struct amba_id *id) |
1e9c2859 | 286 | { |
8944df72 | 287 | struct device *dev = &adev->dev; |
2796325f | 288 | struct pl061 *pl061; |
04ce935c | 289 | struct gpio_irq_chip *girq; |
6da7b0dd | 290 | int ret, irq; |
1e9c2859 | 291 | |
2796325f LW |
292 | pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); |
293 | if (pl061 == NULL) | |
1e9c2859 BS |
294 | return -ENOMEM; |
295 | ||
2796325f LW |
296 | pl061->base = devm_ioremap_resource(dev, &adev->res); |
297 | if (IS_ERR(pl061->base)) | |
298 | return PTR_ERR(pl061->base); | |
1e9c2859 | 299 | |
99b9b45d | 300 | raw_spin_lock_init(&pl061->lock); |
31831f41 | 301 | if (of_property_read_bool(dev->of_node, "gpio-ranges")) { |
2796325f LW |
302 | pl061->gc.request = gpiochip_generic_request; |
303 | pl061->gc.free = gpiochip_generic_free; | |
31831f41 | 304 | } |
1e9c2859 | 305 | |
6da7b0dd | 306 | pl061->gc.base = -1; |
2796325f LW |
307 | pl061->gc.get_direction = pl061_get_direction; |
308 | pl061->gc.direction_input = pl061_direction_input; | |
309 | pl061->gc.direction_output = pl061_direction_output; | |
310 | pl061->gc.get = pl061_get_value; | |
311 | pl061->gc.set = pl061_set_value; | |
312 | pl061->gc.ngpio = PL061_GPIO_NR; | |
313 | pl061->gc.label = dev_name(dev); | |
314 | pl061->gc.parent = dev; | |
315 | pl061->gc.owner = THIS_MODULE; | |
316 | ||
1e9c2859 BS |
317 | /* |
318 | * irq_chip support | |
319 | */ | |
ed8dce4c MS |
320 | pl061->irq_chip.name = dev_name(dev); |
321 | pl061->irq_chip.irq_ack = pl061_irq_ack; | |
322 | pl061->irq_chip.irq_mask = pl061_irq_mask; | |
323 | pl061->irq_chip.irq_unmask = pl061_irq_unmask; | |
324 | pl061->irq_chip.irq_set_type = pl061_irq_type; | |
325 | pl061->irq_chip.irq_set_wake = pl061_irq_set_wake; | |
326 | ||
2796325f | 327 | writeb(0, pl061->base + GPIOIE); /* disable irqs */ |
8944df72 | 328 | irq = adev->irq[0]; |
1a555713 AS |
329 | if (!irq) |
330 | dev_warn(&adev->dev, "IRQ support disabled\n"); | |
2796325f | 331 | pl061->parent_irq = irq; |
8944df72 | 332 | |
04ce935c LW |
333 | girq = &pl061->gc.irq; |
334 | girq->chip = &pl061->irq_chip; | |
335 | girq->parent_handler = pl061_irq_handler; | |
336 | girq->num_parents = 1; | |
337 | girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), | |
338 | GFP_KERNEL); | |
339 | if (!girq->parents) | |
340 | return -ENOMEM; | |
341 | girq->parents[0] = irq; | |
342 | girq->default_type = IRQ_TYPE_NONE; | |
343 | girq->handler = handle_bad_irq; | |
344 | ||
345 | ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061); | |
346 | if (ret) | |
8d5b24bd | 347 | return ret; |
2ba3154d | 348 | |
2796325f | 349 | amba_set_drvdata(adev, pl061); |
4d19addd | 350 | dev_info(dev, "PL061 GPIO chip registered\n"); |
e198a8de | 351 | |
1e9c2859 | 352 | return 0; |
1e9c2859 BS |
353 | } |
354 | ||
e198a8de DS |
355 | #ifdef CONFIG_PM |
356 | static int pl061_suspend(struct device *dev) | |
357 | { | |
2796325f | 358 | struct pl061 *pl061 = dev_get_drvdata(dev); |
e198a8de DS |
359 | int offset; |
360 | ||
2796325f LW |
361 | pl061->csave_regs.gpio_data = 0; |
362 | pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR); | |
363 | pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS); | |
364 | pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE); | |
365 | pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV); | |
366 | pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE); | |
e198a8de DS |
367 | |
368 | for (offset = 0; offset < PL061_GPIO_NR; offset++) { | |
2796325f LW |
369 | if (pl061->csave_regs.gpio_dir & (BIT(offset))) |
370 | pl061->csave_regs.gpio_data |= | |
371 | pl061_get_value(&pl061->gc, offset) << offset; | |
e198a8de DS |
372 | } |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | static int pl061_resume(struct device *dev) | |
378 | { | |
2796325f | 379 | struct pl061 *pl061 = dev_get_drvdata(dev); |
e198a8de DS |
380 | int offset; |
381 | ||
382 | for (offset = 0; offset < PL061_GPIO_NR; offset++) { | |
2796325f LW |
383 | if (pl061->csave_regs.gpio_dir & (BIT(offset))) |
384 | pl061_direction_output(&pl061->gc, offset, | |
385 | pl061->csave_regs.gpio_data & | |
bea41504 | 386 | (BIT(offset))); |
e198a8de | 387 | else |
2796325f | 388 | pl061_direction_input(&pl061->gc, offset); |
e198a8de DS |
389 | } |
390 | ||
2796325f LW |
391 | writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); |
392 | writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); | |
393 | writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); | |
394 | writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); | |
e198a8de DS |
395 | |
396 | return 0; | |
397 | } | |
398 | ||
6e33aced VK |
399 | static const struct dev_pm_ops pl061_dev_pm_ops = { |
400 | .suspend = pl061_suspend, | |
401 | .resume = pl061_resume, | |
402 | .freeze = pl061_suspend, | |
403 | .restore = pl061_resume, | |
404 | }; | |
e198a8de DS |
405 | #endif |
406 | ||
72c7c78e | 407 | static const struct amba_id pl061_ids[] = { |
1e9c2859 BS |
408 | { |
409 | .id = 0x00041061, | |
410 | .mask = 0x000fffff, | |
411 | }, | |
412 | { 0, 0 }, | |
413 | }; | |
414 | ||
415 | static struct amba_driver pl061_gpio_driver = { | |
416 | .drv = { | |
417 | .name = "pl061_gpio", | |
e198a8de DS |
418 | #ifdef CONFIG_PM |
419 | .pm = &pl061_dev_pm_ops, | |
420 | #endif | |
1e9c2859 BS |
421 | }, |
422 | .id_table = pl061_ids, | |
423 | .probe = pl061_probe, | |
424 | }; | |
425 | ||
426 | static int __init pl061_gpio_init(void) | |
427 | { | |
428 | return amba_driver_register(&pl061_gpio_driver); | |
429 | } | |
ef3e7100 | 430 | device_initcall(pl061_gpio_init); |