[linux-2.6-block.git] / drivers / gpio / gpio-pl061.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2008, 2009 Provigent Ltd.
 *
 * Author: Baruch Siach <baruch@tkos.co.il>
 *
 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
 *
 * Data sheet: ARM DDI 0190B, September 2000
 */
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/module.h>
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>

#define GPIODIR 0x400
#define GPIOIS  0x404
#define GPIOIBE 0x408
#define GPIOIEV 0x40C
#define GPIOIE  0x410
#define GPIORIS 0x414
#define GPIOMIS 0x418
#define GPIOIC  0x41C

#define PL061_GPIO_NR	8

#ifdef CONFIG_PM
struct pl061_context_save_regs {
	u8 gpio_data;
	u8 gpio_dir;
	u8 gpio_is;
	u8 gpio_ibe;
	u8 gpio_iev;
	u8 gpio_ie;
};
#endif

struct pl061 {
	raw_spinlock_t		lock;

	void __iomem		*base;
	struct gpio_chip	gc;
	struct irq_chip		irq_chip;
	int			parent_irq;

#ifdef CONFIG_PM
	struct pl061_context_save_regs csave_regs;
#endif
};

static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);

	if (readb(pl061->base + GPIODIR) & BIT(offset))
		return GPIO_LINE_DIRECTION_OUT;

	return GPIO_LINE_DIRECTION_IN;
}

static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);
	unsigned long flags;
	unsigned char gpiodir;

	raw_spin_lock_irqsave(&pl061->lock, flags);
	gpiodir = readb(pl061->base + GPIODIR);
	gpiodir &= ~(BIT(offset));
	writeb(gpiodir, pl061->base + GPIODIR);
	raw_spin_unlock_irqrestore(&pl061->lock, flags);

	return 0;
}

static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
		int value)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);
	unsigned long flags;
	unsigned char gpiodir;

	raw_spin_lock_irqsave(&pl061->lock, flags);
	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
	gpiodir = readb(pl061->base + GPIODIR);
	gpiodir |= BIT(offset);
	writeb(gpiodir, pl061->base + GPIODIR);

	/*
	 * gpio value is set again, because pl061 doesn't allow to set value of
	 * a gpio pin before configuring it in OUT mode.
	 */
	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
	raw_spin_unlock_irqrestore(&pl061->lock, flags);

	return 0;
}

static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);

	return !!readb(pl061->base + (BIT(offset + 2)));
}

static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);

	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
}

static int pl061_irq_type(struct irq_data *d, unsigned trigger)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	int offset = irqd_to_hwirq(d);
	unsigned long flags;
	u8 gpiois, gpioibe, gpioiev;
	u8 bit = BIT(offset);

	if (offset < 0 || offset >= PL061_GPIO_NR)
		return -EINVAL;

	if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
	    (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
	{
		dev_err(gc->parent,
			"trying to configure line %d for both level and edge "
			"detection, choose one!\n",
			offset);
		return -EINVAL;
	}


	raw_spin_lock_irqsave(&pl061->lock, flags);

	gpioiev = readb(pl061->base + GPIOIEV);
	gpiois = readb(pl061->base + GPIOIS);
	gpioibe = readb(pl061->base + GPIOIBE);

	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;

		/* Disable edge detection */
		gpioibe &= ~bit;
		/* Enable level detection */
		gpiois |= bit;
		/* Select polarity */
		if (polarity)
			gpioiev |= bit;
		else
			gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_level_irq);
		dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
			offset,
			polarity ? "HIGH" : "LOW");
	} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
		/* Disable level detection */
		gpiois &= ~bit;
		/* Select both edges, setting this makes GPIOEV be ignored */
		gpioibe |= bit;
		irq_set_handler_locked(d, handle_edge_irq);
		dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
	} else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
		   (trigger & IRQ_TYPE_EDGE_FALLING)) {
		bool rising = trigger & IRQ_TYPE_EDGE_RISING;

		/* Disable level detection */
		gpiois &= ~bit;
		/* Clear detection on both edges */
		gpioibe &= ~bit;
		/* Select edge */
		if (rising)
			gpioiev |= bit;
		else
			gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_edge_irq);
		dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
			offset,
			rising ? "RISING" : "FALLING");
	} else {
		/* No trigger: disable everything */
		gpiois &= ~bit;
		gpioibe &= ~bit;
		gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_bad_irq);
		dev_warn(gc->parent, "no trigger selected for line %d\n",
			 offset);
	}

	writeb(gpiois, pl061->base + GPIOIS);
	writeb(gpioibe, pl061->base + GPIOIBE);
	writeb(gpioiev, pl061->base + GPIOIEV);

	raw_spin_unlock_irqrestore(&pl061->lock, flags);

	return 0;
}

static void pl061_irq_handler(struct irq_desc *desc)
{
	unsigned long pending;
	int offset;
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);

	chained_irq_enter(irqchip, desc);

	pending = readb(pl061->base + GPIOMIS);
	if (pending) {
		for_each_set_bit(offset, &pending, PL061_GPIO_NR)
			generic_handle_irq(irq_find_mapping(gc->irq.domain,
							    offset));
	}

	chained_irq_exit(irqchip, desc);
}

static void pl061_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	raw_spin_lock(&pl061->lock);
	gpioie = readb(pl061->base + GPIOIE) & ~mask;
	writeb(gpioie, pl061->base + GPIOIE);
	raw_spin_unlock(&pl061->lock);
}

static void pl061_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	raw_spin_lock(&pl061->lock);
	gpioie = readb(pl061->base + GPIOIE) | mask;
	writeb(gpioie, pl061->base + GPIOIE);
	raw_spin_unlock(&pl061->lock);
}

/**
 * pl061_irq_ack() - ACK an edge IRQ
 * @d: IRQ data for this IRQ
 *
 * This gets called from the edge IRQ handler to ACK the edge IRQ
 * in the GPIOIC (interrupt-clear) register. For level IRQs this is
 * not needed: these go away when the level signal goes away.
 */
static void pl061_irq_ack(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);

	raw_spin_lock(&pl061->lock);
	writeb(mask, pl061->base + GPIOIC);
	raw_spin_unlock(&pl061->lock);
}

static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);

	return irq_set_irq_wake(pl061->parent_irq, state);
}

static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
{
	struct device *dev = &adev->dev;
	struct pl061 *pl061;
	struct gpio_irq_chip *girq;
	int ret, irq;

	pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
	if (pl061 == NULL)
		return -ENOMEM;

	pl061->base = devm_ioremap_resource(dev, &adev->res);
	if (IS_ERR(pl061->base))
		return PTR_ERR(pl061->base);

	raw_spin_lock_init(&pl061->lock);
	pl061->gc.request = gpiochip_generic_request;
	pl061->gc.free = gpiochip_generic_free;
	pl061->gc.base = -1;
	pl061->gc.get_direction = pl061_get_direction;
	pl061->gc.direction_input = pl061_direction_input;
	pl061->gc.direction_output = pl061_direction_output;
	pl061->gc.get = pl061_get_value;
	pl061->gc.set = pl061_set_value;
	pl061->gc.ngpio = PL061_GPIO_NR;
	pl061->gc.label = dev_name(dev);
	pl061->gc.parent = dev;
	pl061->gc.owner = THIS_MODULE;

	/*
	 * irq_chip support
	 */
	pl061->irq_chip.name = dev_name(dev);
	pl061->irq_chip.irq_ack	= pl061_irq_ack;
	pl061->irq_chip.irq_mask = pl061_irq_mask;
	pl061->irq_chip.irq_unmask = pl061_irq_unmask;
	pl061->irq_chip.irq_set_type = pl061_irq_type;
	pl061->irq_chip.irq_set_wake = pl061_irq_set_wake;

	writeb(0, pl061->base + GPIOIE); /* disable irqs */
	irq = adev->irq[0];
	if (!irq)
		dev_warn(&adev->dev, "IRQ support disabled\n");
	pl061->parent_irq = irq;

	girq = &pl061->gc.irq;
	girq->chip = &pl061->irq_chip;
	girq->parent_handler = pl061_irq_handler;
	girq->num_parents = 1;
	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
				     GFP_KERNEL);
	if (!girq->parents)
		return -ENOMEM;
	girq->parents[0] = irq;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_bad_irq;

	ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061);
	if (ret)
		return ret;

	amba_set_drvdata(adev, pl061);
	dev_info(dev, "PL061 GPIO chip registered\n");

	return 0;
}

#ifdef CONFIG_PM
static int pl061_suspend(struct device *dev)
{
	struct pl061 *pl061 = dev_get_drvdata(dev);
	int offset;

	pl061->csave_regs.gpio_data = 0;
	pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
	pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
	pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
	pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
	pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (pl061->csave_regs.gpio_dir & (BIT(offset)))
			pl061->csave_regs.gpio_data |=
				pl061_get_value(&pl061->gc, offset) << offset;
	}

	return 0;
}

static int pl061_resume(struct device *dev)
{
	struct pl061 *pl061 = dev_get_drvdata(dev);
	int offset;

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (pl061->csave_regs.gpio_dir & (BIT(offset)))
			pl061_direction_output(&pl061->gc, offset,
					pl061->csave_regs.gpio_data &
					(BIT(offset)));
		else
			pl061_direction_input(&pl061->gc, offset);
	}

	writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
	writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
	writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
	writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);

	return 0;
}

static const struct dev_pm_ops pl061_dev_pm_ops = {
	.suspend = pl061_suspend,
	.resume = pl061_resume,
	.freeze = pl061_suspend,
	.restore = pl061_resume,
};
#endif

static const struct amba_id pl061_ids[] = {
	{
		.id	= 0x00041061,
		.mask	= 0x000fffff,
	},
	{ 0, 0 },
};
MODULE_DEVICE_TABLE(amba, pl061_ids);

static struct amba_driver pl061_gpio_driver = {
	.drv = {
		.name	= "pl061_gpio",
#ifdef CONFIG_PM
		.pm	= &pl061_dev_pm_ops,
#endif
	},
	.id_table	= pl061_ids,
	.probe		= pl061_probe,
};
module_amba_driver(pl061_gpio_driver);

MODULE_LICENSE("GPL v2");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
1e9c2859	2	/*
c103de24	3	* Copyright (C) 2008, 2009 Provigent Ltd.
1e9c2859	4	*
ef3e7100 PG	5	* Author: Baruch Siach <baruch@tkos.co.il>
ef3e7100 PG	6	*
1e9c2859 BS	7	* Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
	8	*
	9	* Data sheet: ARM DDI 0190B, September 2000
	10	*/
	11	#include <linux/spinlock.h>
	12	#include <linux/errno.h>
ef3e7100	13	#include <linux/init.h>
1e9c2859 BS	14	#include <linux/io.h>
1e9c2859 BS	15	#include <linux/ioport.h>
2f46205b	16	#include <linux/interrupt.h>
1e9c2859	17	#include <linux/irq.h>
de88cbb7	18	#include <linux/irqchip/chained_irq.h>
61684440	19	#include <linux/module.h>
1e9c2859	20	#include <linux/bitops.h>
dcc6ceef	21	#include <linux/gpio/driver.h>
1e9c2859 BS	22	#include <linux/device.h>
1e9c2859 BS	23	#include <linux/amba/bus.h>
5a0e3ad6	24	#include <linux/slab.h>
39b70ee0	25	#include <linux/pinctrl/consumer.h>
e198a8de	26	#include <linux/pm.h>
1e9c2859 BS	27
	28	#define GPIODIR 0x400
	29	#define GPIOIS 0x404
	30	#define GPIOIBE 0x408
	31	#define GPIOIEV 0x40C
	32	#define GPIOIE 0x410
	33	#define GPIORIS 0x414
	34	#define GPIOMIS 0x418
	35	#define GPIOIC 0x41C
	36
	37	#define PL061_GPIO_NR 8
	38
e198a8de DS	39	#ifdef CONFIG_PM
	40	struct pl061_context_save_regs {
	41	u8 gpio_data;
	42	u8 gpio_dir;
	43	u8 gpio_is;
	44	u8 gpio_ibe;
	45	u8 gpio_iev;
	46	u8 gpio_ie;
	47	};
	48	#endif
1e9c2859	49
538f76c5	50	struct pl061 {
99b9b45d	51	raw_spinlock_t lock;
1e9c2859 BS	52
1e9c2859 BS	53	void __iomem *base;
1e9c2859	54	struct gpio_chip gc;
ed8dce4c	55	struct irq_chip irq_chip;
9c18be8e	56	int parent_irq;
e198a8de DS	57
	58	#ifdef CONFIG_PM
	59	struct pl061_context_save_regs csave_regs;
	60	#endif
1e9c2859 BS	61	};
1e9c2859 BS	62
3484f1be LW	63	static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
3484f1be LW	64	{
2796325f	65	struct pl061 *pl061 = gpiochip_get_data(gc);
3484f1be	66
e42615ec MV	67	if (readb(pl061->base + GPIODIR) & BIT(offset))
	68	return GPIO_LINE_DIRECTION_OUT;
	69
	70	return GPIO_LINE_DIRECTION_IN;
3484f1be LW	71	}
3484f1be LW	72
1e9c2859 BS	73	static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
1e9c2859 BS	74	{
2796325f	75	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859 BS	76	unsigned long flags;
	77	unsigned char gpiodir;
	78
99b9b45d	79	raw_spin_lock_irqsave(&pl061->lock, flags);
2796325f	80	gpiodir = readb(pl061->base + GPIODIR);
bea41504	81	gpiodir &= ~(BIT(offset));
2796325f	82	writeb(gpiodir, pl061->base + GPIODIR);
99b9b45d	83	raw_spin_unlock_irqrestore(&pl061->lock, flags);
1e9c2859 BS	84
	85	return 0;
	86	}
	87
	88	static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
	89	int value)
	90	{
2796325f	91	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859 BS	92	unsigned long flags;
	93	unsigned char gpiodir;
	94
99b9b45d	95	raw_spin_lock_irqsave(&pl061->lock, flags);
2796325f LW	96	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
2796325f LW	97	gpiodir = readb(pl061->base + GPIODIR);
bea41504	98	gpiodir \|= BIT(offset);
2796325f	99	writeb(gpiodir, pl061->base + GPIODIR);
64b997c5	100
	101	/*
	102	* gpio value is set again, because pl061 doesn't allow to set value of
	103	* a gpio pin before configuring it in OUT mode.
	104	*/
2796325f	105	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
99b9b45d	106	raw_spin_unlock_irqrestore(&pl061->lock, flags);
1e9c2859 BS	107
	108	return 0;
	109	}
	110
	111	static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
	112	{
2796325f	113	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859	114
2796325f	115	return !!readb(pl061->base + (BIT(offset + 2)));
1e9c2859 BS	116	}
	117
	118	static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
	119	{
2796325f	120	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859	121
2796325f	122	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
1e9c2859 BS	123	}
1e9c2859 BS	124
b2221869	125	static int pl061_irq_type(struct irq_data *d, unsigned trigger)
1e9c2859	126	{
8d5b24bd	127	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	128	struct pl061 *pl061 = gpiochip_get_data(gc);
f1f70479	129	int offset = irqd_to_hwirq(d);
1e9c2859 BS	130	unsigned long flags;
1e9c2859 BS	131	u8 gpiois, gpioibe, gpioiev;
438a2c9a	132	u8 bit = BIT(offset);
1e9c2859	133
c1cc9b97	134	if (offset < 0 \|\| offset >= PL061_GPIO_NR)
1e9c2859 BS	135	return -EINVAL;
1e9c2859 BS	136
1dbf7f29 LW	137	if ((trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) &&
	138	(trigger & (IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING)))
	139	{
58383c78	140	dev_err(gc->parent,
1dbf7f29 LW	141	"trying to configure line %d for both level and edge "
	142	"detection, choose one!\n",
	143	offset);
	144	return -EINVAL;
	145	}
	146
21d4de14	147
99b9b45d	148	raw_spin_lock_irqsave(&pl061->lock, flags);
21d4de14	149
2796325f LW	150	gpioiev = readb(pl061->base + GPIOIEV);
	151	gpiois = readb(pl061->base + GPIOIS);
	152	gpioibe = readb(pl061->base + GPIOIBE);
21d4de14	153
1e9c2859	154	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
1dbf7f29 LW	155	bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
	156
	157	/* Disable edge detection */
	158	gpioibe &= ~bit;
	159	/* Enable level detection */
438a2c9a	160	gpiois \|= bit;
1dbf7f29 LW	161	/* Select polarity */
1dbf7f29 LW	162	if (polarity)
438a2c9a	163	gpioiev \|= bit;
1e9c2859	164	else
438a2c9a	165	gpioiev &= ~bit;
26ba9cd4	166	irq_set_handler_locked(d, handle_level_irq);
58383c78	167	dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
1dbf7f29 LW	168	offset,
	169	polarity ? "HIGH" : "LOW");
	170	} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
	171	/* Disable level detection */
	172	gpiois &= ~bit;
	173	/* Select both edges, setting this makes GPIOEV be ignored */
438a2c9a	174	gpioibe \|= bit;
26ba9cd4	175	irq_set_handler_locked(d, handle_edge_irq);
58383c78	176	dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
1dbf7f29 LW	177	} else if ((trigger & IRQ_TYPE_EDGE_RISING) \|\|
	178	(trigger & IRQ_TYPE_EDGE_FALLING)) {
	179	bool rising = trigger & IRQ_TYPE_EDGE_RISING;
	180
	181	/* Disable level detection */
	182	gpiois &= ~bit;
	183	/* Clear detection on both edges */
438a2c9a	184	gpioibe &= ~bit;
1dbf7f29 LW	185	/* Select edge */
1dbf7f29 LW	186	if (rising)
438a2c9a	187	gpioiev \|= bit;
1dbf7f29	188	else
438a2c9a	189	gpioiev &= ~bit;
26ba9cd4	190	irq_set_handler_locked(d, handle_edge_irq);
58383c78	191	dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
1dbf7f29 LW	192	offset,
	193	rising ? "RISING" : "FALLING");
	194	} else {
	195	/* No trigger: disable everything */
	196	gpiois &= ~bit;
	197	gpioibe &= ~bit;
	198	gpioiev &= ~bit;
26ba9cd4	199	irq_set_handler_locked(d, handle_bad_irq);
58383c78	200	dev_warn(gc->parent, "no trigger selected for line %d\n",
1dbf7f29	201	offset);
1e9c2859	202	}
1e9c2859	203
2796325f LW	204	writeb(gpiois, pl061->base + GPIOIS);
	205	writeb(gpioibe, pl061->base + GPIOIBE);
	206	writeb(gpioiev, pl061->base + GPIOIEV);
1e9c2859	207
99b9b45d	208	raw_spin_unlock_irqrestore(&pl061->lock, flags);
1e9c2859 BS	209
	210	return 0;
	211	}
	212
bd0b9ac4	213	static void pl061_irq_handler(struct irq_desc *desc)
1e9c2859	214	{
2de0dbc5 RH	215	unsigned long pending;
2de0dbc5 RH	216	int offset;
8d5b24bd	217	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
2796325f	218	struct pl061 *pl061 = gpiochip_get_data(gc);
dece904d	219	struct irq_chip *irqchip = irq_desc_get_chip(desc);
1e9c2859	220
dece904d	221	chained_irq_enter(irqchip, desc);
1e9c2859	222
2796325f	223	pending = readb(pl061->base + GPIOMIS);
2de0dbc5	224	if (pending) {
984b3f57	225	for_each_set_bit(offset, &pending, PL061_GPIO_NR)
f0fbe7bc	226	generic_handle_irq(irq_find_mapping(gc->irq.domain,
8d5b24bd	227	offset));
1e9c2859	228	}
2de0dbc5	229
dece904d	230	chained_irq_exit(irqchip, desc);
1e9c2859 BS	231	}
1e9c2859 BS	232
f1f70479	233	static void pl061_irq_mask(struct irq_data *d)
3ab52475	234	{
8d5b24bd	235	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	236	struct pl061 *pl061 = gpiochip_get_data(gc);
bea41504	237	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
f1f70479 HZ	238	u8 gpioie;
f1f70479 HZ	239
99b9b45d	240	raw_spin_lock(&pl061->lock);
2796325f LW	241	gpioie = readb(pl061->base + GPIOIE) & ~mask;
2796325f LW	242	writeb(gpioie, pl061->base + GPIOIE);
99b9b45d	243	raw_spin_unlock(&pl061->lock);
f1f70479	244	}
3ab52475	245
f1f70479 HZ	246	static void pl061_irq_unmask(struct irq_data *d)
f1f70479 HZ	247	{
8d5b24bd	248	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	249	struct pl061 *pl061 = gpiochip_get_data(gc);
bea41504	250	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
f1f70479 HZ	251	u8 gpioie;
f1f70479 HZ	252
99b9b45d	253	raw_spin_lock(&pl061->lock);
2796325f LW	254	gpioie = readb(pl061->base + GPIOIE) \| mask;
2796325f LW	255	writeb(gpioie, pl061->base + GPIOIE);
99b9b45d	256	raw_spin_unlock(&pl061->lock);
f1f70479 HZ	257	}
f1f70479 HZ	258
26ba9cd4 LW	259	/**
	260	* pl061_irq_ack() - ACK an edge IRQ
	261	* @d: IRQ data for this IRQ
	262	*
	263	* This gets called from the edge IRQ handler to ACK the edge IRQ
	264	* in the GPIOIC (interrupt-clear) register. For level IRQs this is
	265	* not needed: these go away when the level signal goes away.
	266	*/
	267	static void pl061_irq_ack(struct irq_data *d)
	268	{
	269	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	270	struct pl061 *pl061 = gpiochip_get_data(gc);
26ba9cd4 LW	271	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
26ba9cd4 LW	272
99b9b45d	273	raw_spin_lock(&pl061->lock);
2796325f	274	writeb(mask, pl061->base + GPIOIC);
99b9b45d	275	raw_spin_unlock(&pl061->lock);
26ba9cd4 LW	276	}
26ba9cd4 LW	277
2f46205b SH	278	static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
	279	{
	280	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	281	struct pl061 *pl061 = gpiochip_get_data(gc);
2f46205b	282
2796325f	283	return irq_set_irq_wake(pl061->parent_irq, state);
2f46205b SH	284	}
2f46205b SH	285
8944df72	286	static int pl061_probe(struct amba_device adev, const struct amba_id id)
1e9c2859	287	{
8944df72	288	struct device *dev = &adev->dev;
2796325f	289	struct pl061 *pl061;
04ce935c	290	struct gpio_irq_chip *girq;
6da7b0dd	291	int ret, irq;
1e9c2859	292
2796325f LW	293	pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
2796325f LW	294	if (pl061 == NULL)
1e9c2859 BS	295	return -ENOMEM;
1e9c2859 BS	296
2796325f LW	297	pl061->base = devm_ioremap_resource(dev, &adev->res);
	298	if (IS_ERR(pl061->base))
	299	return PTR_ERR(pl061->base);
1e9c2859	300
99b9b45d	301	raw_spin_lock_init(&pl061->lock);
f0254b51 TR	302	pl061->gc.request = gpiochip_generic_request;
f0254b51 TR	303	pl061->gc.free = gpiochip_generic_free;
6da7b0dd	304	pl061->gc.base = -1;
2796325f LW	305	pl061->gc.get_direction = pl061_get_direction;
	306	pl061->gc.direction_input = pl061_direction_input;
	307	pl061->gc.direction_output = pl061_direction_output;
	308	pl061->gc.get = pl061_get_value;
	309	pl061->gc.set = pl061_set_value;
	310	pl061->gc.ngpio = PL061_GPIO_NR;
	311	pl061->gc.label = dev_name(dev);
	312	pl061->gc.parent = dev;
	313	pl061->gc.owner = THIS_MODULE;
	314
1e9c2859 BS	315	/*
	316	* irq_chip support
	317	*/
ed8dce4c MS	318	pl061->irq_chip.name = dev_name(dev);
	319	pl061->irq_chip.irq_ack = pl061_irq_ack;
	320	pl061->irq_chip.irq_mask = pl061_irq_mask;
	321	pl061->irq_chip.irq_unmask = pl061_irq_unmask;
	322	pl061->irq_chip.irq_set_type = pl061_irq_type;
	323	pl061->irq_chip.irq_set_wake = pl061_irq_set_wake;
	324
2796325f	325	writeb(0, pl061->base + GPIOIE); /* disable irqs */
8944df72	326	irq = adev->irq[0];
1a555713 AS	327	if (!irq)
1a555713 AS	328	dev_warn(&adev->dev, "IRQ support disabled\n");
2796325f	329	pl061->parent_irq = irq;
8944df72	330
04ce935c LW	331	girq = &pl061->gc.irq;
	332	girq->chip = &pl061->irq_chip;
	333	girq->parent_handler = pl061_irq_handler;
	334	girq->num_parents = 1;
	335	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
	336	GFP_KERNEL);
	337	if (!girq->parents)
	338	return -ENOMEM;
	339	girq->parents[0] = irq;
	340	girq->default_type = IRQ_TYPE_NONE;
	341	girq->handler = handle_bad_irq;
	342
	343	ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061);
	344	if (ret)
8d5b24bd	345	return ret;
2ba3154d	346
2796325f	347	amba_set_drvdata(adev, pl061);
4d19addd	348	dev_info(dev, "PL061 GPIO chip registered\n");
e198a8de	349
1e9c2859	350	return 0;
1e9c2859 BS	351	}
1e9c2859 BS	352
e198a8de DS	353	#ifdef CONFIG_PM
	354	static int pl061_suspend(struct device *dev)
	355	{
2796325f	356	struct pl061 *pl061 = dev_get_drvdata(dev);
e198a8de DS	357	int offset;
e198a8de DS	358
2796325f LW	359	pl061->csave_regs.gpio_data = 0;
	360	pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
	361	pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
	362	pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
	363	pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
	364	pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
e198a8de DS	365
e198a8de DS	366	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
2796325f LW	367	if (pl061->csave_regs.gpio_dir & (BIT(offset)))
	368	pl061->csave_regs.gpio_data \|=
	369	pl061_get_value(&pl061->gc, offset) << offset;
e198a8de DS	370	}
	371
	372	return 0;
	373	}
	374
	375	static int pl061_resume(struct device *dev)
	376	{
2796325f	377	struct pl061 *pl061 = dev_get_drvdata(dev);
e198a8de DS	378	int offset;
	379
	380	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
2796325f LW	381	if (pl061->csave_regs.gpio_dir & (BIT(offset)))
	382	pl061_direction_output(&pl061->gc, offset,
	383	pl061->csave_regs.gpio_data &
bea41504	384	(BIT(offset)));
e198a8de	385	else
2796325f	386	pl061_direction_input(&pl061->gc, offset);
e198a8de DS	387	}
e198a8de DS	388
2796325f LW	389	writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
	390	writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
	391	writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
	392	writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);
e198a8de DS	393
	394	return 0;
	395	}
	396
6e33aced VK	397	static const struct dev_pm_ops pl061_dev_pm_ops = {
	398	.suspend = pl061_suspend,
	399	.resume = pl061_resume,
	400	.freeze = pl061_suspend,
	401	.restore = pl061_resume,
	402	};
e198a8de DS	403	#endif
e198a8de DS	404
72c7c78e	405	static const struct amba_id pl061_ids[] = {
1e9c2859 BS	406	{
	407	.id = 0x00041061,
	408	.mask = 0x000fffff,
	409	},
	410	{ 0, 0 },
	411	};
61684440	412	MODULE_DEVICE_TABLE(amba, pl061_ids);
1e9c2859 BS	413
	414	static struct amba_driver pl061_gpio_driver = {
	415	.drv = {
	416	.name = "pl061_gpio",
e198a8de DS	417	#ifdef CONFIG_PM
	418	.pm = &pl061_dev_pm_ops,
	419	#endif
1e9c2859 BS	420	},
	421	.id_table = pl061_ids,
	422	.probe = pl061_probe,
	423	};
61684440	424	module_amba_driver(pl061_gpio_driver);
1e9c2859	425
61684440	426	MODULE_LICENSE("GPL v2");