[linux-2.6-block.git] / drivers / gpio / gpio-pl061.c

/*
 * Copyright (C) 2008, 2009 Provigent Ltd.
 *
 * Author: Baruch Siach <baruch@tkos.co.il>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
 *
 * Data sheet: ARM DDI 0190B, September 2000
 */
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/bitops.h>
#include <linux/gpio/driver.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>

#define GPIODIR 0x400
#define GPIOIS  0x404
#define GPIOIBE 0x408
#define GPIOIEV 0x40C
#define GPIOIE  0x410
#define GPIORIS 0x414
#define GPIOMIS 0x418
#define GPIOIC  0x41C

#define PL061_GPIO_NR	8

#ifdef CONFIG_PM
struct pl061_context_save_regs {
	u8 gpio_data;
	u8 gpio_dir;
	u8 gpio_is;
	u8 gpio_ibe;
	u8 gpio_iev;
	u8 gpio_ie;
};
#endif

struct pl061 {
	raw_spinlock_t		lock;

	void __iomem		*base;
	struct gpio_chip	gc;
	struct irq_chip		irq_chip;
	int			parent_irq;

#ifdef CONFIG_PM
	struct pl061_context_save_regs csave_regs;
#endif
};

static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);

	return !(readb(pl061->base + GPIODIR) & BIT(offset));
}

static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);
	unsigned long flags;
	unsigned char gpiodir;

	raw_spin_lock_irqsave(&pl061->lock, flags);
	gpiodir = readb(pl061->base + GPIODIR);
	gpiodir &= ~(BIT(offset));
	writeb(gpiodir, pl061->base + GPIODIR);
	raw_spin_unlock_irqrestore(&pl061->lock, flags);

	return 0;
}

static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
		int value)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);
	unsigned long flags;
	unsigned char gpiodir;

	raw_spin_lock_irqsave(&pl061->lock, flags);
	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
	gpiodir = readb(pl061->base + GPIODIR);
	gpiodir |= BIT(offset);
	writeb(gpiodir, pl061->base + GPIODIR);

	/*
	 * gpio value is set again, because pl061 doesn't allow to set value of
	 * a gpio pin before configuring it in OUT mode.
	 */
	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
	raw_spin_unlock_irqrestore(&pl061->lock, flags);

	return 0;
}

static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);

	return !!readb(pl061->base + (BIT(offset + 2)));
}

static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
{
	struct pl061 *pl061 = gpiochip_get_data(gc);

	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
}

static int pl061_irq_type(struct irq_data *d, unsigned trigger)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	int offset = irqd_to_hwirq(d);
	unsigned long flags;
	u8 gpiois, gpioibe, gpioiev;
	u8 bit = BIT(offset);

	if (offset < 0 || offset >= PL061_GPIO_NR)
		return -EINVAL;

	if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
	    (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
	{
		dev_err(gc->parent,
			"trying to configure line %d for both level and edge "
			"detection, choose one!\n",
			offset);
		return -EINVAL;
	}


	raw_spin_lock_irqsave(&pl061->lock, flags);

	gpioiev = readb(pl061->base + GPIOIEV);
	gpiois = readb(pl061->base + GPIOIS);
	gpioibe = readb(pl061->base + GPIOIBE);

	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;

		/* Disable edge detection */
		gpioibe &= ~bit;
		/* Enable level detection */
		gpiois |= bit;
		/* Select polarity */
		if (polarity)
			gpioiev |= bit;
		else
			gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_level_irq);
		dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
			offset,
			polarity ? "HIGH" : "LOW");
	} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
		/* Disable level detection */
		gpiois &= ~bit;
		/* Select both edges, setting this makes GPIOEV be ignored */
		gpioibe |= bit;
		irq_set_handler_locked(d, handle_edge_irq);
		dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
	} else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
		   (trigger & IRQ_TYPE_EDGE_FALLING)) {
		bool rising = trigger & IRQ_TYPE_EDGE_RISING;

		/* Disable level detection */
		gpiois &= ~bit;
		/* Clear detection on both edges */
		gpioibe &= ~bit;
		/* Select edge */
		if (rising)
			gpioiev |= bit;
		else
			gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_edge_irq);
		dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
			offset,
			rising ? "RISING" : "FALLING");
	} else {
		/* No trigger: disable everything */
		gpiois &= ~bit;
		gpioibe &= ~bit;
		gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_bad_irq);
		dev_warn(gc->parent, "no trigger selected for line %d\n",
			 offset);
	}

	writeb(gpiois, pl061->base + GPIOIS);
	writeb(gpioibe, pl061->base + GPIOIBE);
	writeb(gpioiev, pl061->base + GPIOIEV);

	raw_spin_unlock_irqrestore(&pl061->lock, flags);

	return 0;
}

static void pl061_irq_handler(struct irq_desc *desc)
{
	unsigned long pending;
	int offset;
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);

	chained_irq_enter(irqchip, desc);

	pending = readb(pl061->base + GPIOMIS);
	if (pending) {
		for_each_set_bit(offset, &pending, PL061_GPIO_NR)
			generic_handle_irq(irq_find_mapping(gc->irq.domain,
							    offset));
	}

	chained_irq_exit(irqchip, desc);
}

static void pl061_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	raw_spin_lock(&pl061->lock);
	gpioie = readb(pl061->base + GPIOIE) & ~mask;
	writeb(gpioie, pl061->base + GPIOIE);
	raw_spin_unlock(&pl061->lock);
}

static void pl061_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	raw_spin_lock(&pl061->lock);
	gpioie = readb(pl061->base + GPIOIE) | mask;
	writeb(gpioie, pl061->base + GPIOIE);
	raw_spin_unlock(&pl061->lock);
}

/**
 * pl061_irq_ack() - ACK an edge IRQ
 * @d: IRQ data for this IRQ
 *
 * This gets called from the edge IRQ handler to ACK the edge IRQ
 * in the GPIOIC (interrupt-clear) register. For level IRQs this is
 * not needed: these go away when the level signal goes away.
 */
static void pl061_irq_ack(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);

	raw_spin_lock(&pl061->lock);
	writeb(mask, pl061->base + GPIOIC);
	raw_spin_unlock(&pl061->lock);
}

static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061 *pl061 = gpiochip_get_data(gc);

	return irq_set_irq_wake(pl061->parent_irq, state);
}

static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
{
	struct device *dev = &adev->dev;
	struct pl061 *pl061;
	int ret, irq;

	pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
	if (pl061 == NULL)
		return -ENOMEM;

	pl061->base = devm_ioremap_resource(dev, &adev->res);
	if (IS_ERR(pl061->base))
		return PTR_ERR(pl061->base);

	raw_spin_lock_init(&pl061->lock);
	if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
		pl061->gc.request = gpiochip_generic_request;
		pl061->gc.free = gpiochip_generic_free;
	}

	pl061->gc.base = -1;
	pl061->gc.get_direction = pl061_get_direction;
	pl061->gc.direction_input = pl061_direction_input;
	pl061->gc.direction_output = pl061_direction_output;
	pl061->gc.get = pl061_get_value;
	pl061->gc.set = pl061_set_value;
	pl061->gc.ngpio = PL061_GPIO_NR;
	pl061->gc.label = dev_name(dev);
	pl061->gc.parent = dev;
	pl061->gc.owner = THIS_MODULE;

	ret = gpiochip_add_data(&pl061->gc, pl061);
	if (ret)
		return ret;

	/*
	 * irq_chip support
	 */
	pl061->irq_chip.name = dev_name(dev);
	pl061->irq_chip.irq_ack	= pl061_irq_ack;
	pl061->irq_chip.irq_mask = pl061_irq_mask;
	pl061->irq_chip.irq_unmask = pl061_irq_unmask;
	pl061->irq_chip.irq_set_type = pl061_irq_type;
	pl061->irq_chip.irq_set_wake = pl061_irq_set_wake;

	writeb(0, pl061->base + GPIOIE); /* disable irqs */
	irq = adev->irq[0];
	if (irq < 0) {
		dev_err(&adev->dev, "invalid IRQ\n");
		return -ENODEV;
	}
	pl061->parent_irq = irq;

	ret = gpiochip_irqchip_add(&pl061->gc, &pl061->irq_chip,
				   0, handle_bad_irq,
				   IRQ_TYPE_NONE);
	if (ret) {
		dev_info(&adev->dev, "could not add irqchip\n");
		return ret;
	}
	gpiochip_set_chained_irqchip(&pl061->gc, &pl061->irq_chip,
				     irq, pl061_irq_handler);

	amba_set_drvdata(adev, pl061);
	dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
		 &adev->res.start);

	return 0;
}

#ifdef CONFIG_PM
static int pl061_suspend(struct device *dev)
{
	struct pl061 *pl061 = dev_get_drvdata(dev);
	int offset;

	pl061->csave_regs.gpio_data = 0;
	pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
	pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
	pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
	pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
	pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (pl061->csave_regs.gpio_dir & (BIT(offset)))
			pl061->csave_regs.gpio_data |=
				pl061_get_value(&pl061->gc, offset) << offset;
	}

	return 0;
}

static int pl061_resume(struct device *dev)
{
	struct pl061 *pl061 = dev_get_drvdata(dev);
	int offset;

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (pl061->csave_regs.gpio_dir & (BIT(offset)))
			pl061_direction_output(&pl061->gc, offset,
					pl061->csave_regs.gpio_data &
					(BIT(offset)));
		else
			pl061_direction_input(&pl061->gc, offset);
	}

	writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
	writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
	writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
	writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);

	return 0;
}

static const struct dev_pm_ops pl061_dev_pm_ops = {
	.suspend = pl061_suspend,
	.resume = pl061_resume,
	.freeze = pl061_suspend,
	.restore = pl061_resume,
};
#endif

static const struct amba_id pl061_ids[] = {
	{
		.id	= 0x00041061,
		.mask	= 0x000fffff,
	},
	{ 0, 0 },
};

static struct amba_driver pl061_gpio_driver = {
	.drv = {
		.name	= "pl061_gpio",
#ifdef CONFIG_PM
		.pm	= &pl061_dev_pm_ops,
#endif
	},
	.id_table	= pl061_ids,
	.probe		= pl061_probe,
};

static int __init pl061_gpio_init(void)
{
	return amba_driver_register(&pl061_gpio_driver);
}
device_initcall(pl061_gpio_init);
Commit	Line	Data
1e9c2859	1	/*
c103de24	2	* Copyright (C) 2008, 2009 Provigent Ltd.
1e9c2859	3	*
ef3e7100 PG	4	* Author: Baruch Siach <baruch@tkos.co.il>
ef3e7100 PG	5	*
1e9c2859 BS	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
	11	*
	12	* Data sheet: ARM DDI 0190B, September 2000
	13	*/
	14	#include <linux/spinlock.h>
	15	#include <linux/errno.h>
ef3e7100	16	#include <linux/init.h>
1e9c2859 BS	17	#include <linux/io.h>
1e9c2859 BS	18	#include <linux/ioport.h>
2f46205b	19	#include <linux/interrupt.h>
1e9c2859	20	#include <linux/irq.h>
de88cbb7	21	#include <linux/irqchip/chained_irq.h>
1e9c2859	22	#include <linux/bitops.h>
dcc6ceef	23	#include <linux/gpio/driver.h>
1e9c2859 BS	24	#include <linux/device.h>
1e9c2859 BS	25	#include <linux/amba/bus.h>
5a0e3ad6	26	#include <linux/slab.h>
39b70ee0	27	#include <linux/pinctrl/consumer.h>
e198a8de	28	#include <linux/pm.h>
1e9c2859 BS	29
	30	#define GPIODIR 0x400
	31	#define GPIOIS 0x404
	32	#define GPIOIBE 0x408
	33	#define GPIOIEV 0x40C
	34	#define GPIOIE 0x410
	35	#define GPIORIS 0x414
	36	#define GPIOMIS 0x418
	37	#define GPIOIC 0x41C
	38
	39	#define PL061_GPIO_NR 8
	40
e198a8de DS	41	#ifdef CONFIG_PM
	42	struct pl061_context_save_regs {
	43	u8 gpio_data;
	44	u8 gpio_dir;
	45	u8 gpio_is;
	46	u8 gpio_ibe;
	47	u8 gpio_iev;
	48	u8 gpio_ie;
	49	};
	50	#endif
1e9c2859	51
538f76c5	52	struct pl061 {
99b9b45d	53	raw_spinlock_t lock;
1e9c2859 BS	54
1e9c2859 BS	55	void __iomem *base;
1e9c2859	56	struct gpio_chip gc;
ed8dce4c	57	struct irq_chip irq_chip;
9c18be8e	58	int parent_irq;
e198a8de DS	59
	60	#ifdef CONFIG_PM
	61	struct pl061_context_save_regs csave_regs;
	62	#endif
1e9c2859 BS	63	};
1e9c2859 BS	64
3484f1be LW	65	static int pl061_get_direction(struct gpio_chip *gc, unsigned offset)
3484f1be LW	66	{
2796325f	67	struct pl061 *pl061 = gpiochip_get_data(gc);
3484f1be	68
2796325f	69	return !(readb(pl061->base + GPIODIR) & BIT(offset));
3484f1be LW	70	}
3484f1be LW	71
1e9c2859 BS	72	static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
1e9c2859 BS	73	{
2796325f	74	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859 BS	75	unsigned long flags;
	76	unsigned char gpiodir;
	77
99b9b45d	78	raw_spin_lock_irqsave(&pl061->lock, flags);
2796325f	79	gpiodir = readb(pl061->base + GPIODIR);
bea41504	80	gpiodir &= ~(BIT(offset));
2796325f	81	writeb(gpiodir, pl061->base + GPIODIR);
99b9b45d	82	raw_spin_unlock_irqrestore(&pl061->lock, flags);
1e9c2859 BS	83
	84	return 0;
	85	}
	86
	87	static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
	88	int value)
	89	{
2796325f	90	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859 BS	91	unsigned long flags;
	92	unsigned char gpiodir;
	93
99b9b45d	94	raw_spin_lock_irqsave(&pl061->lock, flags);
2796325f LW	95	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
2796325f LW	96	gpiodir = readb(pl061->base + GPIODIR);
bea41504	97	gpiodir \|= BIT(offset);
2796325f	98	writeb(gpiodir, pl061->base + GPIODIR);
64b997c5	99
	100	/*
	101	* gpio value is set again, because pl061 doesn't allow to set value of
	102	* a gpio pin before configuring it in OUT mode.
	103	*/
2796325f	104	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
99b9b45d	105	raw_spin_unlock_irqrestore(&pl061->lock, flags);
1e9c2859 BS	106
	107	return 0;
	108	}
	109
	110	static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
	111	{
2796325f	112	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859	113
2796325f	114	return !!readb(pl061->base + (BIT(offset + 2)));
1e9c2859 BS	115	}
	116
	117	static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
	118	{
2796325f	119	struct pl061 *pl061 = gpiochip_get_data(gc);
1e9c2859	120
2796325f	121	writeb(!!value << offset, pl061->base + (BIT(offset + 2)));
1e9c2859 BS	122	}
1e9c2859 BS	123
b2221869	124	static int pl061_irq_type(struct irq_data *d, unsigned trigger)
1e9c2859	125	{
8d5b24bd	126	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	127	struct pl061 *pl061 = gpiochip_get_data(gc);
f1f70479	128	int offset = irqd_to_hwirq(d);
1e9c2859 BS	129	unsigned long flags;
1e9c2859 BS	130	u8 gpiois, gpioibe, gpioiev;
438a2c9a	131	u8 bit = BIT(offset);
1e9c2859	132
c1cc9b97	133	if (offset < 0 \|\| offset >= PL061_GPIO_NR)
1e9c2859 BS	134	return -EINVAL;
1e9c2859 BS	135
1dbf7f29 LW	136	if ((trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) &&
	137	(trigger & (IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING)))
	138	{
58383c78	139	dev_err(gc->parent,
1dbf7f29 LW	140	"trying to configure line %d for both level and edge "
	141	"detection, choose one!\n",
	142	offset);
	143	return -EINVAL;
	144	}
	145
21d4de14	146
99b9b45d	147	raw_spin_lock_irqsave(&pl061->lock, flags);
21d4de14	148
2796325f LW	149	gpioiev = readb(pl061->base + GPIOIEV);
	150	gpiois = readb(pl061->base + GPIOIS);
	151	gpioibe = readb(pl061->base + GPIOIBE);
21d4de14	152
1e9c2859	153	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
1dbf7f29 LW	154	bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
	155
	156	/* Disable edge detection */
	157	gpioibe &= ~bit;
	158	/* Enable level detection */
438a2c9a	159	gpiois \|= bit;
1dbf7f29 LW	160	/* Select polarity */
1dbf7f29 LW	161	if (polarity)
438a2c9a	162	gpioiev \|= bit;
1e9c2859	163	else
438a2c9a	164	gpioiev &= ~bit;
26ba9cd4	165	irq_set_handler_locked(d, handle_level_irq);
58383c78	166	dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
1dbf7f29 LW	167	offset,
	168	polarity ? "HIGH" : "LOW");
	169	} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
	170	/* Disable level detection */
	171	gpiois &= ~bit;
	172	/* Select both edges, setting this makes GPIOEV be ignored */
438a2c9a	173	gpioibe \|= bit;
26ba9cd4	174	irq_set_handler_locked(d, handle_edge_irq);
58383c78	175	dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
1dbf7f29 LW	176	} else if ((trigger & IRQ_TYPE_EDGE_RISING) \|\|
	177	(trigger & IRQ_TYPE_EDGE_FALLING)) {
	178	bool rising = trigger & IRQ_TYPE_EDGE_RISING;
	179
	180	/* Disable level detection */
	181	gpiois &= ~bit;
	182	/* Clear detection on both edges */
438a2c9a	183	gpioibe &= ~bit;
1dbf7f29 LW	184	/* Select edge */
1dbf7f29 LW	185	if (rising)
438a2c9a	186	gpioiev \|= bit;
1dbf7f29	187	else
438a2c9a	188	gpioiev &= ~bit;
26ba9cd4	189	irq_set_handler_locked(d, handle_edge_irq);
58383c78	190	dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
1dbf7f29 LW	191	offset,
	192	rising ? "RISING" : "FALLING");
	193	} else {
	194	/* No trigger: disable everything */
	195	gpiois &= ~bit;
	196	gpioibe &= ~bit;
	197	gpioiev &= ~bit;
26ba9cd4	198	irq_set_handler_locked(d, handle_bad_irq);
58383c78	199	dev_warn(gc->parent, "no trigger selected for line %d\n",
1dbf7f29	200	offset);
1e9c2859	201	}
1e9c2859	202
2796325f LW	203	writeb(gpiois, pl061->base + GPIOIS);
	204	writeb(gpioibe, pl061->base + GPIOIBE);
	205	writeb(gpioiev, pl061->base + GPIOIEV);
1e9c2859	206
99b9b45d	207	raw_spin_unlock_irqrestore(&pl061->lock, flags);
1e9c2859 BS	208
	209	return 0;
	210	}
	211
bd0b9ac4	212	static void pl061_irq_handler(struct irq_desc *desc)
1e9c2859	213	{
2de0dbc5 RH	214	unsigned long pending;
2de0dbc5 RH	215	int offset;
8d5b24bd	216	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
2796325f	217	struct pl061 *pl061 = gpiochip_get_data(gc);
dece904d	218	struct irq_chip *irqchip = irq_desc_get_chip(desc);
1e9c2859	219
dece904d	220	chained_irq_enter(irqchip, desc);
1e9c2859	221
2796325f	222	pending = readb(pl061->base + GPIOMIS);
2de0dbc5	223	if (pending) {
984b3f57	224	for_each_set_bit(offset, &pending, PL061_GPIO_NR)
f0fbe7bc	225	generic_handle_irq(irq_find_mapping(gc->irq.domain,
8d5b24bd	226	offset));
1e9c2859	227	}
2de0dbc5	228
dece904d	229	chained_irq_exit(irqchip, desc);
1e9c2859 BS	230	}
1e9c2859 BS	231
f1f70479	232	static void pl061_irq_mask(struct irq_data *d)
3ab52475	233	{
8d5b24bd	234	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	235	struct pl061 *pl061 = gpiochip_get_data(gc);
bea41504	236	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
f1f70479 HZ	237	u8 gpioie;
f1f70479 HZ	238
99b9b45d	239	raw_spin_lock(&pl061->lock);
2796325f LW	240	gpioie = readb(pl061->base + GPIOIE) & ~mask;
2796325f LW	241	writeb(gpioie, pl061->base + GPIOIE);
99b9b45d	242	raw_spin_unlock(&pl061->lock);
f1f70479	243	}
3ab52475	244
f1f70479 HZ	245	static void pl061_irq_unmask(struct irq_data *d)
f1f70479 HZ	246	{
8d5b24bd	247	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	248	struct pl061 *pl061 = gpiochip_get_data(gc);
bea41504	249	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
f1f70479 HZ	250	u8 gpioie;
f1f70479 HZ	251
99b9b45d	252	raw_spin_lock(&pl061->lock);
2796325f LW	253	gpioie = readb(pl061->base + GPIOIE) \| mask;
2796325f LW	254	writeb(gpioie, pl061->base + GPIOIE);
99b9b45d	255	raw_spin_unlock(&pl061->lock);
f1f70479 HZ	256	}
f1f70479 HZ	257
26ba9cd4 LW	258	/**
	259	* pl061_irq_ack() - ACK an edge IRQ
	260	* @d: IRQ data for this IRQ
	261	*
	262	* This gets called from the edge IRQ handler to ACK the edge IRQ
	263	* in the GPIOIC (interrupt-clear) register. For level IRQs this is
	264	* not needed: these go away when the level signal goes away.
	265	*/
	266	static void pl061_irq_ack(struct irq_data *d)
	267	{
	268	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	269	struct pl061 *pl061 = gpiochip_get_data(gc);
26ba9cd4 LW	270	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
26ba9cd4 LW	271
99b9b45d	272	raw_spin_lock(&pl061->lock);
2796325f	273	writeb(mask, pl061->base + GPIOIC);
99b9b45d	274	raw_spin_unlock(&pl061->lock);
26ba9cd4 LW	275	}
26ba9cd4 LW	276
2f46205b SH	277	static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
	278	{
	279	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
2796325f	280	struct pl061 *pl061 = gpiochip_get_data(gc);
2f46205b	281
2796325f	282	return irq_set_irq_wake(pl061->parent_irq, state);
2f46205b SH	283	}
2f46205b SH	284
8944df72	285	static int pl061_probe(struct amba_device adev, const struct amba_id id)
1e9c2859	286	{
8944df72	287	struct device *dev = &adev->dev;
2796325f	288	struct pl061 *pl061;
6da7b0dd	289	int ret, irq;
1e9c2859	290
2796325f LW	291	pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL);
2796325f LW	292	if (pl061 == NULL)
1e9c2859 BS	293	return -ENOMEM;
1e9c2859 BS	294
2796325f LW	295	pl061->base = devm_ioremap_resource(dev, &adev->res);
	296	if (IS_ERR(pl061->base))
	297	return PTR_ERR(pl061->base);
1e9c2859	298
99b9b45d	299	raw_spin_lock_init(&pl061->lock);
31831f41	300	if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
2796325f LW	301	pl061->gc.request = gpiochip_generic_request;
2796325f LW	302	pl061->gc.free = gpiochip_generic_free;
31831f41	303	}
1e9c2859	304
6da7b0dd	305	pl061->gc.base = -1;
2796325f LW	306	pl061->gc.get_direction = pl061_get_direction;
	307	pl061->gc.direction_input = pl061_direction_input;
	308	pl061->gc.direction_output = pl061_direction_output;
	309	pl061->gc.get = pl061_get_value;
	310	pl061->gc.set = pl061_set_value;
	311	pl061->gc.ngpio = PL061_GPIO_NR;
	312	pl061->gc.label = dev_name(dev);
	313	pl061->gc.parent = dev;
	314	pl061->gc.owner = THIS_MODULE;
	315
	316	ret = gpiochip_add_data(&pl061->gc, pl061);
1e9c2859	317	if (ret)
8944df72	318	return ret;
1e9c2859 BS	319
	320	/*
	321	* irq_chip support
	322	*/
ed8dce4c MS	323	pl061->irq_chip.name = dev_name(dev);
	324	pl061->irq_chip.irq_ack = pl061_irq_ack;
	325	pl061->irq_chip.irq_mask = pl061_irq_mask;
	326	pl061->irq_chip.irq_unmask = pl061_irq_unmask;
	327	pl061->irq_chip.irq_set_type = pl061_irq_type;
	328	pl061->irq_chip.irq_set_wake = pl061_irq_set_wake;
	329
2796325f	330	writeb(0, pl061->base + GPIOIE); /* disable irqs */
8944df72	331	irq = adev->irq[0];
7808755d LW	332	if (irq < 0) {
7808755d LW	333	dev_err(&adev->dev, "invalid IRQ\n");
8944df72	334	return -ENODEV;
7808755d	335	}
2796325f	336	pl061->parent_irq = irq;
8944df72	337
ed8dce4c	338	ret = gpiochip_irqchip_add(&pl061->gc, &pl061->irq_chip,
6da7b0dd	339	0, handle_bad_irq,
8d5b24bd LW	340	IRQ_TYPE_NONE);
	341	if (ret) {
	342	dev_info(&adev->dev, "could not add irqchip\n");
	343	return ret;
7808755d	344	}
ed8dce4c	345	gpiochip_set_chained_irqchip(&pl061->gc, &pl061->irq_chip,
8d5b24bd	346	irq, pl061_irq_handler);
2ba3154d	347
2796325f	348	amba_set_drvdata(adev, pl061);
76b3627e FE	349	dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
76b3627e FE	350	&adev->res.start);
e198a8de	351
1e9c2859	352	return 0;
1e9c2859 BS	353	}
1e9c2859 BS	354
e198a8de DS	355	#ifdef CONFIG_PM
	356	static int pl061_suspend(struct device *dev)
	357	{
2796325f	358	struct pl061 *pl061 = dev_get_drvdata(dev);
e198a8de DS	359	int offset;
e198a8de DS	360
2796325f LW	361	pl061->csave_regs.gpio_data = 0;
	362	pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR);
	363	pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS);
	364	pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE);
	365	pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV);
	366	pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE);
e198a8de DS	367
e198a8de DS	368	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
2796325f LW	369	if (pl061->csave_regs.gpio_dir & (BIT(offset)))
	370	pl061->csave_regs.gpio_data \|=
	371	pl061_get_value(&pl061->gc, offset) << offset;
e198a8de DS	372	}
	373
	374	return 0;
	375	}
	376
	377	static int pl061_resume(struct device *dev)
	378	{
2796325f	379	struct pl061 *pl061 = dev_get_drvdata(dev);
e198a8de DS	380	int offset;
	381
	382	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
2796325f LW	383	if (pl061->csave_regs.gpio_dir & (BIT(offset)))
	384	pl061_direction_output(&pl061->gc, offset,
	385	pl061->csave_regs.gpio_data &
bea41504	386	(BIT(offset)));
e198a8de	387	else
2796325f	388	pl061_direction_input(&pl061->gc, offset);
e198a8de DS	389	}
e198a8de DS	390
2796325f LW	391	writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS);
	392	writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE);
	393	writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV);
	394	writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE);
e198a8de DS	395
	396	return 0;
	397	}
	398
6e33aced VK	399	static const struct dev_pm_ops pl061_dev_pm_ops = {
	400	.suspend = pl061_suspend,
	401	.resume = pl061_resume,
	402	.freeze = pl061_suspend,
	403	.restore = pl061_resume,
	404	};
e198a8de DS	405	#endif
e198a8de DS	406
72c7c78e	407	static const struct amba_id pl061_ids[] = {
1e9c2859 BS	408	{
	409	.id = 0x00041061,
	410	.mask = 0x000fffff,
	411	},
	412	{ 0, 0 },
	413	};
	414
	415	static struct amba_driver pl061_gpio_driver = {
	416	.drv = {
	417	.name = "pl061_gpio",
e198a8de DS	418	#ifdef CONFIG_PM
	419	.pm = &pl061_dev_pm_ops,
	420	#endif
1e9c2859 BS	421	},
	422	.id_table = pl061_ids,
	423	.probe = pl061_probe,
	424	};
	425
	426	static int __init pl061_gpio_init(void)
	427	{
	428	return amba_driver_register(&pl061_gpio_driver);
	429	}
ef3e7100	430	device_initcall(pl061_gpio_init);