Commit | Line | Data |
---|---|---|
d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1e9c2859 | 2 | /* |
c103de24 | 3 | * Copyright (C) 2008, 2009 Provigent Ltd. |
1e9c2859 | 4 | * |
ef3e7100 PG |
5 | * Author: Baruch Siach <baruch@tkos.co.il> |
6 | * | |
1e9c2859 BS |
7 | * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061) |
8 | * | |
9 | * Data sheet: ARM DDI 0190B, September 2000 | |
10 | */ | |
5b937a83 AS |
11 | #include <linux/amba/bus.h> |
12 | #include <linux/bitops.h> | |
13 | #include <linux/device.h> | |
1e9c2859 | 14 | #include <linux/errno.h> |
5b937a83 | 15 | #include <linux/gpio/driver.h> |
ef3e7100 | 16 | #include <linux/init.h> |
5b937a83 | 17 | #include <linux/interrupt.h> |
1e9c2859 BS |
18 | #include <linux/io.h> |
19 | #include <linux/ioport.h> | |
20 | #include <linux/irq.h> | |
de88cbb7 | 21 | #include <linux/irqchip/chained_irq.h> |
61684440 | 22 | #include <linux/module.h> |
39b70ee0 | 23 | #include <linux/pinctrl/consumer.h> |
e198a8de | 24 | #include <linux/pm.h> |
5b937a83 AS |
25 | #include <linux/seq_file.h> |
26 | #include <linux/slab.h> | |
27 | #include <linux/spinlock.h> | |
1e9c2859 BS |
28 | |
29 | #define GPIODIR 0x400 | |
30 | #define GPIOIS 0x404 | |
31 | #define GPIOIBE 0x408 | |
32 | #define GPIOIEV 0x40C | |
33 | #define GPIOIE 0x410 | |
34 | #define GPIORIS 0x414 | |
35 | #define GPIOMIS 0x418 | |
36 | #define GPIOIC 0x41C | |
37 | ||
38 | #define PL061_GPIO_NR 8 | |
39 | ||
e198a8de DS |
40 | #ifdef CONFIG_PM |
41 | struct pl061_context_save_regs { | |
42 | u8 gpio_data; | |
43 | u8 gpio_dir; | |
44 | u8 gpio_is; | |
45 | u8 gpio_ibe; | |
46 | u8 gpio_iev; | |
47 | u8 gpio_ie; | |
48 | }; | |
49 | #endif | |
1e9c2859 | 50 | |
538f76c5 | 51 | struct pl061 { |
99b9b45d | 52 | raw_spinlock_t lock; |
1e9c2859 BS |
53 | |
54 | void __iomem *base; | |
1e9c2859 | 55 | struct gpio_chip gc; |
9c18be8e | 56 | int parent_irq; |
e198a8de DS |
57 | |
58 | #ifdef CONFIG_PM | |
59 | struct pl061_context_save_regs csave_regs; | |
60 | #endif | |
1e9c2859 BS |
61 | }; |
62 | ||
3484f1be LW |
63 | static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) |
64 | { | |
2796325f | 65 | struct pl061 *pl061 = gpiochip_get_data(gc); |
3484f1be | 66 | |
e42615ec MV |
67 | if (readb(pl061->base + GPIODIR) & BIT(offset)) |
68 | return GPIO_LINE_DIRECTION_OUT; | |
69 | ||
70 | return GPIO_LINE_DIRECTION_IN; | |
3484f1be LW |
71 | } |
72 | ||
1e9c2859 BS |
73 | static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) |
74 | { | |
2796325f | 75 | struct pl061 *pl061 = gpiochip_get_data(gc); |
1e9c2859 BS |
76 | unsigned long flags; |
77 | unsigned char gpiodir; | |
78 | ||
99b9b45d | 79 | raw_spin_lock_irqsave(&pl061->lock, flags); |
2796325f | 80 | gpiodir = readb(pl061->base + GPIODIR); |
bea41504 | 81 | gpiodir &= ~(BIT(offset)); |
2796325f | 82 | writeb(gpiodir, pl061->base + GPIODIR); |
99b9b45d | 83 | raw_spin_unlock_irqrestore(&pl061->lock, flags); |
1e9c2859 BS |
84 | |
85 | return 0; | |
86 | } | |
87 | ||
88 | static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, | |
89 | int value) | |
90 | { | |
2796325f | 91 | struct pl061 *pl061 = gpiochip_get_data(gc); |
1e9c2859 BS |
92 | unsigned long flags; |
93 | unsigned char gpiodir; | |
94 | ||
99b9b45d | 95 | raw_spin_lock_irqsave(&pl061->lock, flags); |
2796325f LW |
96 | writeb(!!value << offset, pl061->base + (BIT(offset + 2))); |
97 | gpiodir = readb(pl061->base + GPIODIR); | |
bea41504 | 98 | gpiodir |= BIT(offset); |
2796325f | 99 | writeb(gpiodir, pl061->base + GPIODIR); |
64b997c5 | 100 | |
101 | /* | |
102 | * gpio value is set again, because pl061 doesn't allow to set value of | |
103 | * a gpio pin before configuring it in OUT mode. | |
104 | */ | |
2796325f | 105 | writeb(!!value << offset, pl061->base + (BIT(offset + 2))); |
99b9b45d | 106 | raw_spin_unlock_irqrestore(&pl061->lock, flags); |
1e9c2859 BS |
107 | |
108 | return 0; | |
109 | } | |
110 | ||
111 | static int pl061_get_value(struct gpio_chip *gc, unsigned offset) | |
112 | { | |
2796325f | 113 | struct pl061 *pl061 = gpiochip_get_data(gc); |
1e9c2859 | 114 | |
2796325f | 115 | return !!readb(pl061->base + (BIT(offset + 2))); |
1e9c2859 BS |
116 | } |
117 | ||
118 | static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value) | |
119 | { | |
2796325f | 120 | struct pl061 *pl061 = gpiochip_get_data(gc); |
1e9c2859 | 121 | |
2796325f | 122 | writeb(!!value << offset, pl061->base + (BIT(offset + 2))); |
1e9c2859 BS |
123 | } |
124 | ||
b2221869 | 125 | static int pl061_irq_type(struct irq_data *d, unsigned trigger) |
1e9c2859 | 126 | { |
8d5b24bd | 127 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
2796325f | 128 | struct pl061 *pl061 = gpiochip_get_data(gc); |
f1f70479 | 129 | int offset = irqd_to_hwirq(d); |
1e9c2859 BS |
130 | unsigned long flags; |
131 | u8 gpiois, gpioibe, gpioiev; | |
438a2c9a | 132 | u8 bit = BIT(offset); |
1e9c2859 | 133 | |
c1cc9b97 | 134 | if (offset < 0 || offset >= PL061_GPIO_NR) |
1e9c2859 BS |
135 | return -EINVAL; |
136 | ||
1dbf7f29 LW |
137 | if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) && |
138 | (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) | |
139 | { | |
58383c78 | 140 | dev_err(gc->parent, |
1dbf7f29 LW |
141 | "trying to configure line %d for both level and edge " |
142 | "detection, choose one!\n", | |
143 | offset); | |
144 | return -EINVAL; | |
145 | } | |
146 | ||
21d4de14 | 147 | |
99b9b45d | 148 | raw_spin_lock_irqsave(&pl061->lock, flags); |
21d4de14 | 149 | |
2796325f LW |
150 | gpioiev = readb(pl061->base + GPIOIEV); |
151 | gpiois = readb(pl061->base + GPIOIS); | |
152 | gpioibe = readb(pl061->base + GPIOIBE); | |
21d4de14 | 153 | |
1e9c2859 | 154 | if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
1dbf7f29 LW |
155 | bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH; |
156 | ||
157 | /* Disable edge detection */ | |
158 | gpioibe &= ~bit; | |
159 | /* Enable level detection */ | |
438a2c9a | 160 | gpiois |= bit; |
1dbf7f29 LW |
161 | /* Select polarity */ |
162 | if (polarity) | |
438a2c9a | 163 | gpioiev |= bit; |
1e9c2859 | 164 | else |
438a2c9a | 165 | gpioiev &= ~bit; |
26ba9cd4 | 166 | irq_set_handler_locked(d, handle_level_irq); |
58383c78 | 167 | dev_dbg(gc->parent, "line %d: IRQ on %s level\n", |
1dbf7f29 LW |
168 | offset, |
169 | polarity ? "HIGH" : "LOW"); | |
170 | } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { | |
171 | /* Disable level detection */ | |
172 | gpiois &= ~bit; | |
173 | /* Select both edges, setting this makes GPIOEV be ignored */ | |
438a2c9a | 174 | gpioibe |= bit; |
26ba9cd4 | 175 | irq_set_handler_locked(d, handle_edge_irq); |
58383c78 | 176 | dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset); |
1dbf7f29 LW |
177 | } else if ((trigger & IRQ_TYPE_EDGE_RISING) || |
178 | (trigger & IRQ_TYPE_EDGE_FALLING)) { | |
179 | bool rising = trigger & IRQ_TYPE_EDGE_RISING; | |
180 | ||
181 | /* Disable level detection */ | |
182 | gpiois &= ~bit; | |
183 | /* Clear detection on both edges */ | |
438a2c9a | 184 | gpioibe &= ~bit; |
1dbf7f29 LW |
185 | /* Select edge */ |
186 | if (rising) | |
438a2c9a | 187 | gpioiev |= bit; |
1dbf7f29 | 188 | else |
438a2c9a | 189 | gpioiev &= ~bit; |
26ba9cd4 | 190 | irq_set_handler_locked(d, handle_edge_irq); |
58383c78 | 191 | dev_dbg(gc->parent, "line %d: IRQ on %s edge\n", |
1dbf7f29 LW |
192 | offset, |
193 | rising ? "RISING" : "FALLING"); | |
194 | } else { | |
195 | /* No trigger: disable everything */ | |
196 | gpiois &= ~bit; | |
197 | gpioibe &= ~bit; | |
198 | gpioiev &= ~bit; | |
26ba9cd4 | 199 | irq_set_handler_locked(d, handle_bad_irq); |
58383c78 | 200 | dev_warn(gc->parent, "no trigger selected for line %d\n", |
1dbf7f29 | 201 | offset); |
1e9c2859 | 202 | } |
1e9c2859 | 203 | |
2796325f LW |
204 | writeb(gpiois, pl061->base + GPIOIS); |
205 | writeb(gpioibe, pl061->base + GPIOIBE); | |
206 | writeb(gpioiev, pl061->base + GPIOIEV); | |
1e9c2859 | 207 | |
99b9b45d | 208 | raw_spin_unlock_irqrestore(&pl061->lock, flags); |
1e9c2859 BS |
209 | |
210 | return 0; | |
211 | } | |
212 | ||
bd0b9ac4 | 213 | static void pl061_irq_handler(struct irq_desc *desc) |
1e9c2859 | 214 | { |
2de0dbc5 RH |
215 | unsigned long pending; |
216 | int offset; | |
8d5b24bd | 217 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
2796325f | 218 | struct pl061 *pl061 = gpiochip_get_data(gc); |
dece904d | 219 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
1e9c2859 | 220 | |
dece904d | 221 | chained_irq_enter(irqchip, desc); |
1e9c2859 | 222 | |
2796325f | 223 | pending = readb(pl061->base + GPIOMIS); |
2de0dbc5 | 224 | if (pending) { |
984b3f57 | 225 | for_each_set_bit(offset, &pending, PL061_GPIO_NR) |
dbd1c54f MZ |
226 | generic_handle_domain_irq(gc->irq.domain, |
227 | offset); | |
1e9c2859 | 228 | } |
2de0dbc5 | 229 | |
dece904d | 230 | chained_irq_exit(irqchip, desc); |
1e9c2859 BS |
231 | } |
232 | ||
f1f70479 | 233 | static void pl061_irq_mask(struct irq_data *d) |
3ab52475 | 234 | { |
8d5b24bd | 235 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
2796325f | 236 | struct pl061 *pl061 = gpiochip_get_data(gc); |
bea41504 | 237 | u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); |
f1f70479 HZ |
238 | u8 gpioie; |
239 | ||
99b9b45d | 240 | raw_spin_lock(&pl061->lock); |
2796325f LW |
241 | gpioie = readb(pl061->base + GPIOIE) & ~mask; |
242 | writeb(gpioie, pl061->base + GPIOIE); | |
99b9b45d | 243 | raw_spin_unlock(&pl061->lock); |
15d8c14a MZ |
244 | |
245 | gpiochip_disable_irq(gc, d->hwirq); | |
f1f70479 | 246 | } |
3ab52475 | 247 | |
f1f70479 HZ |
248 | static void pl061_irq_unmask(struct irq_data *d) |
249 | { | |
8d5b24bd | 250 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
2796325f | 251 | struct pl061 *pl061 = gpiochip_get_data(gc); |
bea41504 | 252 | u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); |
f1f70479 HZ |
253 | u8 gpioie; |
254 | ||
15d8c14a MZ |
255 | gpiochip_enable_irq(gc, d->hwirq); |
256 | ||
99b9b45d | 257 | raw_spin_lock(&pl061->lock); |
2796325f LW |
258 | gpioie = readb(pl061->base + GPIOIE) | mask; |
259 | writeb(gpioie, pl061->base + GPIOIE); | |
99b9b45d | 260 | raw_spin_unlock(&pl061->lock); |
f1f70479 HZ |
261 | } |
262 | ||
26ba9cd4 LW |
263 | /** |
264 | * pl061_irq_ack() - ACK an edge IRQ | |
265 | * @d: IRQ data for this IRQ | |
266 | * | |
267 | * This gets called from the edge IRQ handler to ACK the edge IRQ | |
268 | * in the GPIOIC (interrupt-clear) register. For level IRQs this is | |
269 | * not needed: these go away when the level signal goes away. | |
270 | */ | |
271 | static void pl061_irq_ack(struct irq_data *d) | |
272 | { | |
273 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
2796325f | 274 | struct pl061 *pl061 = gpiochip_get_data(gc); |
26ba9cd4 LW |
275 | u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); |
276 | ||
99b9b45d | 277 | raw_spin_lock(&pl061->lock); |
2796325f | 278 | writeb(mask, pl061->base + GPIOIC); |
99b9b45d | 279 | raw_spin_unlock(&pl061->lock); |
26ba9cd4 LW |
280 | } |
281 | ||
2f46205b SH |
282 | static int pl061_irq_set_wake(struct irq_data *d, unsigned int state) |
283 | { | |
284 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); | |
2796325f | 285 | struct pl061 *pl061 = gpiochip_get_data(gc); |
2f46205b | 286 | |
2796325f | 287 | return irq_set_irq_wake(pl061->parent_irq, state); |
2f46205b SH |
288 | } |
289 | ||
15d8c14a MZ |
290 | static void pl061_irq_print_chip(struct irq_data *data, struct seq_file *p) |
291 | { | |
292 | struct gpio_chip *gc = irq_data_get_irq_chip_data(data); | |
293 | ||
294 | seq_printf(p, dev_name(gc->parent)); | |
295 | } | |
296 | ||
297 | static const struct irq_chip pl061_irq_chip = { | |
298 | .irq_ack = pl061_irq_ack, | |
299 | .irq_mask = pl061_irq_mask, | |
300 | .irq_unmask = pl061_irq_unmask, | |
301 | .irq_set_type = pl061_irq_type, | |
302 | .irq_set_wake = pl061_irq_set_wake, | |
303 | .irq_print_chip = pl061_irq_print_chip, | |
304 | .flags = IRQCHIP_IMMUTABLE, | |
305 | GPIOCHIP_IRQ_RESOURCE_HELPERS, | |
306 | }; | |
307 | ||
8944df72 | 308 | static int pl061_probe(struct amba_device *adev, const struct amba_id *id) |
1e9c2859 | 309 | { |
8944df72 | 310 | struct device *dev = &adev->dev; |
2796325f | 311 | struct pl061 *pl061; |
04ce935c | 312 | struct gpio_irq_chip *girq; |
6da7b0dd | 313 | int ret, irq; |
1e9c2859 | 314 | |
2796325f LW |
315 | pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); |
316 | if (pl061 == NULL) | |
1e9c2859 BS |
317 | return -ENOMEM; |
318 | ||
2796325f LW |
319 | pl061->base = devm_ioremap_resource(dev, &adev->res); |
320 | if (IS_ERR(pl061->base)) | |
321 | return PTR_ERR(pl061->base); | |
1e9c2859 | 322 | |
99b9b45d | 323 | raw_spin_lock_init(&pl061->lock); |
f0254b51 TR |
324 | pl061->gc.request = gpiochip_generic_request; |
325 | pl061->gc.free = gpiochip_generic_free; | |
6da7b0dd | 326 | pl061->gc.base = -1; |
2796325f LW |
327 | pl061->gc.get_direction = pl061_get_direction; |
328 | pl061->gc.direction_input = pl061_direction_input; | |
329 | pl061->gc.direction_output = pl061_direction_output; | |
330 | pl061->gc.get = pl061_get_value; | |
331 | pl061->gc.set = pl061_set_value; | |
332 | pl061->gc.ngpio = PL061_GPIO_NR; | |
333 | pl061->gc.label = dev_name(dev); | |
334 | pl061->gc.parent = dev; | |
335 | pl061->gc.owner = THIS_MODULE; | |
336 | ||
1e9c2859 BS |
337 | /* |
338 | * irq_chip support | |
339 | */ | |
2796325f | 340 | writeb(0, pl061->base + GPIOIE); /* disable irqs */ |
8944df72 | 341 | irq = adev->irq[0]; |
1a555713 AS |
342 | if (!irq) |
343 | dev_warn(&adev->dev, "IRQ support disabled\n"); | |
2796325f | 344 | pl061->parent_irq = irq; |
8944df72 | 345 | |
04ce935c | 346 | girq = &pl061->gc.irq; |
15d8c14a | 347 | gpio_irq_chip_set_chip(girq, &pl061_irq_chip); |
04ce935c LW |
348 | girq->parent_handler = pl061_irq_handler; |
349 | girq->num_parents = 1; | |
350 | girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), | |
351 | GFP_KERNEL); | |
352 | if (!girq->parents) | |
353 | return -ENOMEM; | |
354 | girq->parents[0] = irq; | |
355 | girq->default_type = IRQ_TYPE_NONE; | |
356 | girq->handler = handle_bad_irq; | |
357 | ||
358 | ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061); | |
359 | if (ret) | |
8d5b24bd | 360 | return ret; |
2ba3154d | 361 | |
2796325f | 362 | amba_set_drvdata(adev, pl061); |
4d19addd | 363 | dev_info(dev, "PL061 GPIO chip registered\n"); |
e198a8de | 364 | |
1e9c2859 | 365 | return 0; |
1e9c2859 BS |
366 | } |
367 | ||
e198a8de DS |
368 | #ifdef CONFIG_PM |
369 | static int pl061_suspend(struct device *dev) | |
370 | { | |
2796325f | 371 | struct pl061 *pl061 = dev_get_drvdata(dev); |
e198a8de DS |
372 | int offset; |
373 | ||
2796325f LW |
374 | pl061->csave_regs.gpio_data = 0; |
375 | pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR); | |
376 | pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS); | |
377 | pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE); | |
378 | pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV); | |
379 | pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE); | |
e198a8de DS |
380 | |
381 | for (offset = 0; offset < PL061_GPIO_NR; offset++) { | |
2796325f LW |
382 | if (pl061->csave_regs.gpio_dir & (BIT(offset))) |
383 | pl061->csave_regs.gpio_data |= | |
384 | pl061_get_value(&pl061->gc, offset) << offset; | |
e198a8de DS |
385 | } |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
390 | static int pl061_resume(struct device *dev) | |
391 | { | |
2796325f | 392 | struct pl061 *pl061 = dev_get_drvdata(dev); |
e198a8de DS |
393 | int offset; |
394 | ||
395 | for (offset = 0; offset < PL061_GPIO_NR; offset++) { | |
2796325f LW |
396 | if (pl061->csave_regs.gpio_dir & (BIT(offset))) |
397 | pl061_direction_output(&pl061->gc, offset, | |
398 | pl061->csave_regs.gpio_data & | |
bea41504 | 399 | (BIT(offset))); |
e198a8de | 400 | else |
2796325f | 401 | pl061_direction_input(&pl061->gc, offset); |
e198a8de DS |
402 | } |
403 | ||
2796325f LW |
404 | writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); |
405 | writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); | |
406 | writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); | |
407 | writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); | |
e198a8de DS |
408 | |
409 | return 0; | |
410 | } | |
411 | ||
6e33aced VK |
412 | static const struct dev_pm_ops pl061_dev_pm_ops = { |
413 | .suspend = pl061_suspend, | |
414 | .resume = pl061_resume, | |
415 | .freeze = pl061_suspend, | |
416 | .restore = pl061_resume, | |
417 | }; | |
e198a8de DS |
418 | #endif |
419 | ||
72c7c78e | 420 | static const struct amba_id pl061_ids[] = { |
1e9c2859 BS |
421 | { |
422 | .id = 0x00041061, | |
423 | .mask = 0x000fffff, | |
424 | }, | |
425 | { 0, 0 }, | |
426 | }; | |
61684440 | 427 | MODULE_DEVICE_TABLE(amba, pl061_ids); |
1e9c2859 BS |
428 | |
429 | static struct amba_driver pl061_gpio_driver = { | |
430 | .drv = { | |
431 | .name = "pl061_gpio", | |
e198a8de DS |
432 | #ifdef CONFIG_PM |
433 | .pm = &pl061_dev_pm_ops, | |
434 | #endif | |
1e9c2859 BS |
435 | }, |
436 | .id_table = pl061_ids, | |
437 | .probe = pl061_probe, | |
438 | }; | |
61684440 | 439 | module_amba_driver(pl061_gpio_driver); |
1e9c2859 | 440 | |
61684440 | 441 | MODULE_LICENSE("GPL v2"); |