[linux-2.6-block.git] / drivers / gpio / gpio-pl061.c

/*
 * Copyright (C) 2008, 2009 Provigent Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
 *
 * Data sheet: ARM DDI 0190B, September 2000
 */
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl061.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>

#define GPIODIR 0x400
#define GPIOIS  0x404
#define GPIOIBE 0x408
#define GPIOIEV 0x40C
#define GPIOIE  0x410
#define GPIORIS 0x414
#define GPIOMIS 0x418
#define GPIOIC  0x41C

#define PL061_GPIO_NR	8

#ifdef CONFIG_PM
struct pl061_context_save_regs {
	u8 gpio_data;
	u8 gpio_dir;
	u8 gpio_is;
	u8 gpio_ibe;
	u8 gpio_iev;
	u8 gpio_ie;
};
#endif

struct pl061_gpio {
	spinlock_t		lock;

	void __iomem		*base;
	struct gpio_chip	gc;

#ifdef CONFIG_PM
	struct pl061_context_save_regs csave_regs;
#endif
};

static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
{
	struct pl061_gpio *chip = gpiochip_get_data(gc);
	unsigned long flags;
	unsigned char gpiodir;

	if (offset >= gc->ngpio)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);
	gpiodir = readb(chip->base + GPIODIR);
	gpiodir &= ~(BIT(offset));
	writeb(gpiodir, chip->base + GPIODIR);
	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
		int value)
{
	struct pl061_gpio *chip = gpiochip_get_data(gc);
	unsigned long flags;
	unsigned char gpiodir;

	if (offset >= gc->ngpio)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);
	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
	gpiodir = readb(chip->base + GPIODIR);
	gpiodir |= BIT(offset);
	writeb(gpiodir, chip->base + GPIODIR);

	/*
	 * gpio value is set again, because pl061 doesn't allow to set value of
	 * a gpio pin before configuring it in OUT mode.
	 */
	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
{
	struct pl061_gpio *chip = gpiochip_get_data(gc);

	return !!readb(chip->base + (BIT(offset + 2)));
}

static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
{
	struct pl061_gpio *chip = gpiochip_get_data(gc);

	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
}

static int pl061_irq_type(struct irq_data *d, unsigned trigger)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061_gpio *chip = gpiochip_get_data(gc);
	int offset = irqd_to_hwirq(d);
	unsigned long flags;
	u8 gpiois, gpioibe, gpioiev;
	u8 bit = BIT(offset);

	if (offset < 0 || offset >= PL061_GPIO_NR)
		return -EINVAL;

	if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) &&
	    (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)))
	{
		dev_err(gc->parent,
			"trying to configure line %d for both level and edge "
			"detection, choose one!\n",
			offset);
		return -EINVAL;
	}


	spin_lock_irqsave(&chip->lock, flags);

	gpioiev = readb(chip->base + GPIOIEV);
	gpiois = readb(chip->base + GPIOIS);
	gpioibe = readb(chip->base + GPIOIBE);

	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;

		/* Disable edge detection */
		gpioibe &= ~bit;
		/* Enable level detection */
		gpiois |= bit;
		/* Select polarity */
		if (polarity)
			gpioiev |= bit;
		else
			gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_level_irq);
		dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
			offset,
			polarity ? "HIGH" : "LOW");
	} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
		/* Disable level detection */
		gpiois &= ~bit;
		/* Select both edges, setting this makes GPIOEV be ignored */
		gpioibe |= bit;
		irq_set_handler_locked(d, handle_edge_irq);
		dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
	} else if ((trigger & IRQ_TYPE_EDGE_RISING) ||
		   (trigger & IRQ_TYPE_EDGE_FALLING)) {
		bool rising = trigger & IRQ_TYPE_EDGE_RISING;

		/* Disable level detection */
		gpiois &= ~bit;
		/* Clear detection on both edges */
		gpioibe &= ~bit;
		/* Select edge */
		if (rising)
			gpioiev |= bit;
		else
			gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_edge_irq);
		dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
			offset,
			rising ? "RISING" : "FALLING");
	} else {
		/* No trigger: disable everything */
		gpiois &= ~bit;
		gpioibe &= ~bit;
		gpioiev &= ~bit;
		irq_set_handler_locked(d, handle_bad_irq);
		dev_warn(gc->parent, "no trigger selected for line %d\n",
			 offset);
	}

	writeb(gpiois, chip->base + GPIOIS);
	writeb(gpioibe, chip->base + GPIOIBE);
	writeb(gpioiev, chip->base + GPIOIEV);

	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static void pl061_irq_handler(struct irq_desc *desc)
{
	unsigned long pending;
	int offset;
	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
	struct pl061_gpio *chip = gpiochip_get_data(gc);
	struct irq_chip *irqchip = irq_desc_get_chip(desc);

	chained_irq_enter(irqchip, desc);

	pending = readb(chip->base + GPIOMIS);
	if (pending) {
		for_each_set_bit(offset, &pending, PL061_GPIO_NR)
			generic_handle_irq(irq_find_mapping(gc->irqdomain,
							    offset));
	}

	chained_irq_exit(irqchip, desc);
}

static void pl061_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061_gpio *chip = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	spin_lock(&chip->lock);
	gpioie = readb(chip->base + GPIOIE) & ~mask;
	writeb(gpioie, chip->base + GPIOIE);
	spin_unlock(&chip->lock);
}

static void pl061_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061_gpio *chip = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
	u8 gpioie;

	spin_lock(&chip->lock);
	gpioie = readb(chip->base + GPIOIE) | mask;
	writeb(gpioie, chip->base + GPIOIE);
	spin_unlock(&chip->lock);
}

/**
 * pl061_irq_ack() - ACK an edge IRQ
 * @d: IRQ data for this IRQ
 *
 * This gets called from the edge IRQ handler to ACK the edge IRQ
 * in the GPIOIC (interrupt-clear) register. For level IRQs this is
 * not needed: these go away when the level signal goes away.
 */
static void pl061_irq_ack(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pl061_gpio *chip = gpiochip_get_data(gc);
	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);

	spin_lock(&chip->lock);
	writeb(mask, chip->base + GPIOIC);
	spin_unlock(&chip->lock);
}

static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);

	return irq_set_irq_wake(gc->irq_parent, state);
}

static struct irq_chip pl061_irqchip = {
	.name		= "pl061",
	.irq_ack	= pl061_irq_ack,
	.irq_mask	= pl061_irq_mask,
	.irq_unmask	= pl061_irq_unmask,
	.irq_set_type	= pl061_irq_type,
	.irq_set_wake	= pl061_irq_set_wake,
};

static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
{
	struct device *dev = &adev->dev;
	struct pl061_platform_data *pdata = dev_get_platdata(dev);
	struct pl061_gpio *chip;
	int ret, irq, i, irq_base;

	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
	if (chip == NULL)
		return -ENOMEM;

	if (pdata) {
		chip->gc.base = pdata->gpio_base;
		irq_base = pdata->irq_base;
		if (irq_base <= 0) {
			dev_err(&adev->dev, "invalid IRQ base in pdata\n");
			return -ENODEV;
		}
	} else {
		chip->gc.base = -1;
		irq_base = 0;
	}

	chip->base = devm_ioremap_resource(dev, &adev->res);
	if (IS_ERR(chip->base))
		return PTR_ERR(chip->base);

	spin_lock_init(&chip->lock);
	if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
		chip->gc.request = gpiochip_generic_request;
		chip->gc.free = gpiochip_generic_free;
	}

	chip->gc.direction_input = pl061_direction_input;
	chip->gc.direction_output = pl061_direction_output;
	chip->gc.get = pl061_get_value;
	chip->gc.set = pl061_set_value;
	chip->gc.ngpio = PL061_GPIO_NR;
	chip->gc.label = dev_name(dev);
	chip->gc.parent = dev;
	chip->gc.owner = THIS_MODULE;

	ret = gpiochip_add_data(&chip->gc, chip);
	if (ret)
		return ret;

	/*
	 * irq_chip support
	 */
	writeb(0, chip->base + GPIOIE); /* disable irqs */
	irq = adev->irq[0];
	if (irq < 0) {
		dev_err(&adev->dev, "invalid IRQ\n");
		return -ENODEV;
	}

	ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
				   irq_base, handle_bad_irq,
				   IRQ_TYPE_NONE);
	if (ret) {
		dev_info(&adev->dev, "could not add irqchip\n");
		return ret;
	}
	gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
				     irq, pl061_irq_handler);

	for (i = 0; i < PL061_GPIO_NR; i++) {
		if (pdata) {
			if (pdata->directions & (BIT(i)))
				pl061_direction_output(&chip->gc, i,
						pdata->values & (BIT(i)));
			else
				pl061_direction_input(&chip->gc, i);
		}
	}

	amba_set_drvdata(adev, chip);
	dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
		 &adev->res.start);

	return 0;
}

#ifdef CONFIG_PM
static int pl061_suspend(struct device *dev)
{
	struct pl061_gpio *chip = dev_get_drvdata(dev);
	int offset;

	chip->csave_regs.gpio_data = 0;
	chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
	chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
	chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
	chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
	chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (chip->csave_regs.gpio_dir & (BIT(offset)))
			chip->csave_regs.gpio_data |=
				pl061_get_value(&chip->gc, offset) << offset;
	}

	return 0;
}

static int pl061_resume(struct device *dev)
{
	struct pl061_gpio *chip = dev_get_drvdata(dev);
	int offset;

	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
		if (chip->csave_regs.gpio_dir & (BIT(offset)))
			pl061_direction_output(&chip->gc, offset,
					chip->csave_regs.gpio_data &
					(BIT(offset)));
		else
			pl061_direction_input(&chip->gc, offset);
	}

	writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
	writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
	writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
	writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);

	return 0;
}

static const struct dev_pm_ops pl061_dev_pm_ops = {
	.suspend = pl061_suspend,
	.resume = pl061_resume,
	.freeze = pl061_suspend,
	.restore = pl061_resume,
};
#endif

static struct amba_id pl061_ids[] = {
	{
		.id	= 0x00041061,
		.mask	= 0x000fffff,
	},
	{ 0, 0 },
};

MODULE_DEVICE_TABLE(amba, pl061_ids);

static struct amba_driver pl061_gpio_driver = {
	.drv = {
		.name	= "pl061_gpio",
#ifdef CONFIG_PM
		.pm	= &pl061_dev_pm_ops,
#endif
	},
	.id_table	= pl061_ids,
	.probe		= pl061_probe,
};

static int __init pl061_gpio_init(void)
{
	return amba_driver_register(&pl061_gpio_driver);
}
module_init(pl061_gpio_init);

MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
MODULE_DESCRIPTION("PL061 GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1e9c2859	1	/*
c103de24	2	* Copyright (C) 2008, 2009 Provigent Ltd.
1e9c2859 BS	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
	9	*
	10	* Data sheet: ARM DDI 0190B, September 2000
	11	*/
	12	#include <linux/spinlock.h>
	13	#include <linux/errno.h>
	14	#include <linux/module.h>
1e9c2859 BS	15	#include <linux/io.h>
1e9c2859 BS	16	#include <linux/ioport.h>
2f46205b	17	#include <linux/interrupt.h>
1e9c2859	18	#include <linux/irq.h>
de88cbb7	19	#include <linux/irqchip/chained_irq.h>
1e9c2859	20	#include <linux/bitops.h>
1e9c2859 BS	21	#include <linux/gpio.h>
	22	#include <linux/device.h>
	23	#include <linux/amba/bus.h>
	24	#include <linux/amba/pl061.h>
5a0e3ad6	25	#include <linux/slab.h>
39b70ee0	26	#include <linux/pinctrl/consumer.h>
e198a8de	27	#include <linux/pm.h>
1e9c2859 BS	28
	29	#define GPIODIR 0x400
	30	#define GPIOIS 0x404
	31	#define GPIOIBE 0x408
	32	#define GPIOIEV 0x40C
	33	#define GPIOIE 0x410
	34	#define GPIORIS 0x414
	35	#define GPIOMIS 0x418
	36	#define GPIOIC 0x41C
	37
	38	#define PL061_GPIO_NR 8
	39
e198a8de DS	40	#ifdef CONFIG_PM
	41	struct pl061_context_save_regs {
	42	u8 gpio_data;
	43	u8 gpio_dir;
	44	u8 gpio_is;
	45	u8 gpio_ibe;
	46	u8 gpio_iev;
	47	u8 gpio_ie;
	48	};
	49	#endif
1e9c2859	50
1e9c2859	51	struct pl061_gpio {
835c192f	52	spinlock_t lock;
1e9c2859 BS	53
1e9c2859 BS	54	void __iomem *base;
1e9c2859	55	struct gpio_chip gc;
e198a8de DS	56
	57	#ifdef CONFIG_PM
	58	struct pl061_context_save_regs csave_regs;
	59	#endif
1e9c2859 BS	60	};
	61
	62	static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
	63	{
d81b37fc	64	struct pl061_gpio *chip = gpiochip_get_data(gc);
1e9c2859 BS	65	unsigned long flags;
	66	unsigned char gpiodir;
	67
	68	if (offset >= gc->ngpio)
	69	return -EINVAL;
	70
	71	spin_lock_irqsave(&chip->lock, flags);
	72	gpiodir = readb(chip->base + GPIODIR);
bea41504	73	gpiodir &= ~(BIT(offset));
1e9c2859 BS	74	writeb(gpiodir, chip->base + GPIODIR);
	75	spin_unlock_irqrestore(&chip->lock, flags);
	76
	77	return 0;
	78	}
	79
	80	static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
	81	int value)
	82	{
d81b37fc	83	struct pl061_gpio *chip = gpiochip_get_data(gc);
1e9c2859 BS	84	unsigned long flags;
	85	unsigned char gpiodir;
	86
	87	if (offset >= gc->ngpio)
	88	return -EINVAL;
	89
	90	spin_lock_irqsave(&chip->lock, flags);
bea41504	91	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
1e9c2859	92	gpiodir = readb(chip->base + GPIODIR);
bea41504	93	gpiodir \|= BIT(offset);
1e9c2859	94	writeb(gpiodir, chip->base + GPIODIR);
64b997c5	95
	96	/*
	97	* gpio value is set again, because pl061 doesn't allow to set value of
	98	* a gpio pin before configuring it in OUT mode.
	99	*/
bea41504	100	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
1e9c2859 BS	101	spin_unlock_irqrestore(&chip->lock, flags);
	102
	103	return 0;
	104	}
	105
	106	static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
	107	{
d81b37fc	108	struct pl061_gpio *chip = gpiochip_get_data(gc);
1e9c2859	109
bea41504	110	return !!readb(chip->base + (BIT(offset + 2)));
1e9c2859 BS	111	}
	112
	113	static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
	114	{
d81b37fc	115	struct pl061_gpio *chip = gpiochip_get_data(gc);
1e9c2859	116
bea41504	117	writeb(!!value << offset, chip->base + (BIT(offset + 2)));
1e9c2859 BS	118	}
1e9c2859 BS	119
b2221869	120	static int pl061_irq_type(struct irq_data *d, unsigned trigger)
1e9c2859	121	{
8d5b24bd	122	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
d81b37fc	123	struct pl061_gpio *chip = gpiochip_get_data(gc);
f1f70479	124	int offset = irqd_to_hwirq(d);
1e9c2859 BS	125	unsigned long flags;
1e9c2859 BS	126	u8 gpiois, gpioibe, gpioiev;
438a2c9a	127	u8 bit = BIT(offset);
1e9c2859	128
c1cc9b97	129	if (offset < 0 \|\| offset >= PL061_GPIO_NR)
1e9c2859 BS	130	return -EINVAL;
1e9c2859 BS	131
1dbf7f29 LW	132	if ((trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) &&
	133	(trigger & (IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING)))
	134	{
58383c78	135	dev_err(gc->parent,
1dbf7f29 LW	136	"trying to configure line %d for both level and edge "
	137	"detection, choose one!\n",
	138	offset);
	139	return -EINVAL;
	140	}
	141
21d4de14 DC	142
	143	spin_lock_irqsave(&chip->lock, flags);
	144
	145	gpioiev = readb(chip->base + GPIOIEV);
	146	gpiois = readb(chip->base + GPIOIS);
	147	gpioibe = readb(chip->base + GPIOIBE);
	148
1e9c2859	149	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
1dbf7f29 LW	150	bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH;
	151
	152	/* Disable edge detection */
	153	gpioibe &= ~bit;
	154	/* Enable level detection */
438a2c9a	155	gpiois \|= bit;
1dbf7f29 LW	156	/* Select polarity */
1dbf7f29 LW	157	if (polarity)
438a2c9a	158	gpioiev \|= bit;
1e9c2859	159	else
438a2c9a	160	gpioiev &= ~bit;
26ba9cd4	161	irq_set_handler_locked(d, handle_level_irq);
58383c78	162	dev_dbg(gc->parent, "line %d: IRQ on %s level\n",
1dbf7f29 LW	163	offset,
	164	polarity ? "HIGH" : "LOW");
	165	} else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
	166	/* Disable level detection */
	167	gpiois &= ~bit;
	168	/* Select both edges, setting this makes GPIOEV be ignored */
438a2c9a	169	gpioibe \|= bit;
26ba9cd4	170	irq_set_handler_locked(d, handle_edge_irq);
58383c78	171	dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset);
1dbf7f29 LW	172	} else if ((trigger & IRQ_TYPE_EDGE_RISING) \|\|
	173	(trigger & IRQ_TYPE_EDGE_FALLING)) {
	174	bool rising = trigger & IRQ_TYPE_EDGE_RISING;
	175
	176	/* Disable level detection */
	177	gpiois &= ~bit;
	178	/* Clear detection on both edges */
438a2c9a	179	gpioibe &= ~bit;
1dbf7f29 LW	180	/* Select edge */
1dbf7f29 LW	181	if (rising)
438a2c9a	182	gpioiev \|= bit;
1dbf7f29	183	else
438a2c9a	184	gpioiev &= ~bit;
26ba9cd4	185	irq_set_handler_locked(d, handle_edge_irq);
58383c78	186	dev_dbg(gc->parent, "line %d: IRQ on %s edge\n",
1dbf7f29 LW	187	offset,
	188	rising ? "RISING" : "FALLING");
	189	} else {
	190	/* No trigger: disable everything */
	191	gpiois &= ~bit;
	192	gpioibe &= ~bit;
	193	gpioiev &= ~bit;
26ba9cd4	194	irq_set_handler_locked(d, handle_bad_irq);
58383c78	195	dev_warn(gc->parent, "no trigger selected for line %d\n",
1dbf7f29	196	offset);
1e9c2859	197	}
1e9c2859	198
438a2c9a LW	199	writeb(gpiois, chip->base + GPIOIS);
438a2c9a LW	200	writeb(gpioibe, chip->base + GPIOIBE);
1e9c2859 BS	201	writeb(gpioiev, chip->base + GPIOIEV);
1e9c2859 BS	202
f1f70479	203	spin_unlock_irqrestore(&chip->lock, flags);
1e9c2859 BS	204
	205	return 0;
	206	}
	207
bd0b9ac4	208	static void pl061_irq_handler(struct irq_desc *desc)
1e9c2859	209	{
2de0dbc5 RH	210	unsigned long pending;
2de0dbc5 RH	211	int offset;
8d5b24bd	212	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
d81b37fc	213	struct pl061_gpio *chip = gpiochip_get_data(gc);
dece904d	214	struct irq_chip *irqchip = irq_desc_get_chip(desc);
1e9c2859	215
dece904d	216	chained_irq_enter(irqchip, desc);
1e9c2859	217
2de0dbc5	218	pending = readb(chip->base + GPIOMIS);
2de0dbc5	219	if (pending) {
984b3f57	220	for_each_set_bit(offset, &pending, PL061_GPIO_NR)
8d5b24bd LW	221	generic_handle_irq(irq_find_mapping(gc->irqdomain,
8d5b24bd LW	222	offset));
1e9c2859	223	}
2de0dbc5	224
dece904d	225	chained_irq_exit(irqchip, desc);
1e9c2859 BS	226	}
1e9c2859 BS	227
f1f70479	228	static void pl061_irq_mask(struct irq_data *d)
3ab52475	229	{
8d5b24bd	230	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
d81b37fc	231	struct pl061_gpio *chip = gpiochip_get_data(gc);
bea41504	232	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
f1f70479 HZ	233	u8 gpioie;
	234
	235	spin_lock(&chip->lock);
	236	gpioie = readb(chip->base + GPIOIE) & ~mask;
	237	writeb(gpioie, chip->base + GPIOIE);
	238	spin_unlock(&chip->lock);
	239	}
3ab52475	240
f1f70479 HZ	241	static void pl061_irq_unmask(struct irq_data *d)
f1f70479 HZ	242	{
8d5b24bd	243	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
d81b37fc	244	struct pl061_gpio *chip = gpiochip_get_data(gc);
bea41504	245	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
f1f70479 HZ	246	u8 gpioie;
	247
	248	spin_lock(&chip->lock);
	249	gpioie = readb(chip->base + GPIOIE) \| mask;
	250	writeb(gpioie, chip->base + GPIOIE);
	251	spin_unlock(&chip->lock);
	252	}
	253
26ba9cd4 LW	254	/**
	255	* pl061_irq_ack() - ACK an edge IRQ
	256	* @d: IRQ data for this IRQ
	257	*
	258	* This gets called from the edge IRQ handler to ACK the edge IRQ
	259	* in the GPIOIC (interrupt-clear) register. For level IRQs this is
	260	* not needed: these go away when the level signal goes away.
	261	*/
	262	static void pl061_irq_ack(struct irq_data *d)
	263	{
	264	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
d81b37fc	265	struct pl061_gpio *chip = gpiochip_get_data(gc);
26ba9cd4 LW	266	u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR);
	267
	268	spin_lock(&chip->lock);
	269	writeb(mask, chip->base + GPIOIC);
	270	spin_unlock(&chip->lock);
	271	}
	272
2f46205b SH	273	static int pl061_irq_set_wake(struct irq_data *d, unsigned int state)
	274	{
	275	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	276
	277	return irq_set_irq_wake(gc->irq_parent, state);
	278	}
	279
f1f70479	280	static struct irq_chip pl061_irqchip = {
9ae7e9e3	281	.name = "pl061",
26ba9cd4	282	.irq_ack = pl061_irq_ack,
f1f70479 HZ	283	.irq_mask = pl061_irq_mask,
	284	.irq_unmask = pl061_irq_unmask,
	285	.irq_set_type = pl061_irq_type,
2f46205b	286	.irq_set_wake = pl061_irq_set_wake,
f1f70479 HZ	287	};
f1f70479 HZ	288
8944df72	289	static int pl061_probe(struct amba_device adev, const struct amba_id id)
1e9c2859	290	{
8944df72	291	struct device *dev = &adev->dev;
e56aee18	292	struct pl061_platform_data *pdata = dev_get_platdata(dev);
1e9c2859	293	struct pl061_gpio *chip;
f1f70479	294	int ret, irq, i, irq_base;
1e9c2859	295
8944df72	296	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
1e9c2859 BS	297	if (chip == NULL)
	298	return -ENOMEM;
	299
76c05c8a RH	300	if (pdata) {
76c05c8a RH	301	chip->gc.base = pdata->gpio_base;
f1f70479	302	irq_base = pdata->irq_base;
7808755d LW	303	if (irq_base <= 0) {
7808755d LW	304	dev_err(&adev->dev, "invalid IRQ base in pdata\n");
f1f70479	305	return -ENODEV;
7808755d	306	}
f1f70479	307	} else {
76c05c8a	308	chip->gc.base = -1;
f1f70479 HZ	309	irq_base = 0;
f1f70479 HZ	310	}
76c05c8a	311
09bafc30 JH	312	chip->base = devm_ioremap_resource(dev, &adev->res);
	313	if (IS_ERR(chip->base))
	314	return PTR_ERR(chip->base);
1e9c2859 BS	315
1e9c2859 BS	316	spin_lock_init(&chip->lock);
31831f41 JG	317	if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
	318	chip->gc.request = gpiochip_generic_request;
	319	chip->gc.free = gpiochip_generic_free;
	320	}
1e9c2859 BS	321
	322	chip->gc.direction_input = pl061_direction_input;
	323	chip->gc.direction_output = pl061_direction_output;
	324	chip->gc.get = pl061_get_value;
	325	chip->gc.set = pl061_set_value;
1e9c2859	326	chip->gc.ngpio = PL061_GPIO_NR;
8944df72	327	chip->gc.label = dev_name(dev);
58383c78	328	chip->gc.parent = dev;
1e9c2859 BS	329	chip->gc.owner = THIS_MODULE;
1e9c2859 BS	330
d81b37fc	331	ret = gpiochip_add_data(&chip->gc, chip);
1e9c2859	332	if (ret)
8944df72	333	return ret;
1e9c2859 BS	334
	335	/*
	336	* irq_chip support
	337	*/
1e9c2859	338	writeb(0, chip->base + GPIOIE); /* disable irqs */
8944df72	339	irq = adev->irq[0];
7808755d LW	340	if (irq < 0) {
7808755d LW	341	dev_err(&adev->dev, "invalid IRQ\n");
8944df72	342	return -ENODEV;
7808755d	343	}
8944df72	344
8d5b24bd	345	ret = gpiochip_irqchip_add(&chip->gc, &pl061_irqchip,
26ba9cd4	346	irq_base, handle_bad_irq,
8d5b24bd LW	347	IRQ_TYPE_NONE);
	348	if (ret) {
	349	dev_info(&adev->dev, "could not add irqchip\n");
	350	return ret;
7808755d	351	}
8d5b24bd LW	352	gpiochip_set_chained_irqchip(&chip->gc, &pl061_irqchip,
8d5b24bd LW	353	irq, pl061_irq_handler);
2ba3154d	354
1e9c2859	355	for (i = 0; i < PL061_GPIO_NR; i++) {
76c05c8a	356	if (pdata) {
bea41504	357	if (pdata->directions & (BIT(i)))
76c05c8a	358	pl061_direction_output(&chip->gc, i,
bea41504	359	pdata->values & (BIT(i)));
76c05c8a RH	360	else
	361	pl061_direction_input(&chip->gc, i);
	362	}
1e9c2859 BS	363	}
1e9c2859 BS	364
8944df72	365	amba_set_drvdata(adev, chip);
76b3627e FE	366	dev_info(&adev->dev, "PL061 GPIO chip @%pa registered\n",
76b3627e FE	367	&adev->res.start);
e198a8de	368
1e9c2859	369	return 0;
1e9c2859 BS	370	}
1e9c2859 BS	371
e198a8de DS	372	#ifdef CONFIG_PM
	373	static int pl061_suspend(struct device *dev)
	374	{
	375	struct pl061_gpio *chip = dev_get_drvdata(dev);
	376	int offset;
	377
	378	chip->csave_regs.gpio_data = 0;
	379	chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);
	380	chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);
	381	chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);
	382	chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);
	383	chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);
	384
	385	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
bea41504	386	if (chip->csave_regs.gpio_dir & (BIT(offset)))
e198a8de DS	387	chip->csave_regs.gpio_data \|=
	388	pl061_get_value(&chip->gc, offset) << offset;
	389	}
	390
	391	return 0;
	392	}
	393
	394	static int pl061_resume(struct device *dev)
	395	{
	396	struct pl061_gpio *chip = dev_get_drvdata(dev);
	397	int offset;
	398
	399	for (offset = 0; offset < PL061_GPIO_NR; offset++) {
bea41504	400	if (chip->csave_regs.gpio_dir & (BIT(offset)))
e198a8de DS	401	pl061_direction_output(&chip->gc, offset,
e198a8de DS	402	chip->csave_regs.gpio_data &
bea41504	403	(BIT(offset)));
e198a8de DS	404	else
	405	pl061_direction_input(&chip->gc, offset);
	406	}
	407
	408	writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);
	409	writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);
	410	writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);
	411	writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);
	412
	413	return 0;
	414	}
	415
6e33aced VK	416	static const struct dev_pm_ops pl061_dev_pm_ops = {
	417	.suspend = pl061_suspend,
	418	.resume = pl061_resume,
	419	.freeze = pl061_suspend,
	420	.restore = pl061_resume,
	421	};
e198a8de DS	422	#endif
e198a8de DS	423
2c39c9e1	424	static struct amba_id pl061_ids[] = {
1e9c2859 BS	425	{
	426	.id = 0x00041061,
	427	.mask = 0x000fffff,
	428	},
	429	{ 0, 0 },
	430	};
	431
955b678c DM	432	MODULE_DEVICE_TABLE(amba, pl061_ids);
955b678c DM	433
1e9c2859 BS	434	static struct amba_driver pl061_gpio_driver = {
	435	.drv = {
	436	.name = "pl061_gpio",
e198a8de DS	437	#ifdef CONFIG_PM
	438	.pm = &pl061_dev_pm_ops,
	439	#endif
1e9c2859 BS	440	},
	441	.id_table = pl061_ids,
	442	.probe = pl061_probe,
	443	};
	444
	445	static int __init pl061_gpio_init(void)
	446	{
	447	return amba_driver_register(&pl061_gpio_driver);
	448	}
5985d76c	449	module_init(pl061_gpio_init);
1e9c2859 BS	450
	451	MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
	452	MODULE_DESCRIPTION("PL061 GPIO driver");
	453	MODULE_LICENSE("GPL");