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abd46274 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
df6df93c | 2 | /* |
212892b8 AD |
3 | * Copyright (C) 2015-2023 Texas Instruments Incorporated - https://www.ti.com/ |
4 | * Andrew Davis <afd@ti.com> | |
df6df93c AD |
5 | */ |
6 | ||
40bb5d72 MHT |
7 | #include <linux/bitmap.h> |
8 | #include <linux/bitops.h> | |
df6df93c AD |
9 | #include <linux/delay.h> |
10 | #include <linux/gpio/consumer.h> | |
11 | #include <linux/gpio/driver.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/mutex.h> | |
14 | #include <linux/spi/spi.h> | |
15 | ||
16 | #define DEFAULT_NGPIO 8 | |
17 | ||
18 | /** | |
19 | * struct pisosr_gpio - GPIO driver data | |
20 | * @chip: GPIO controller chip | |
21 | * @spi: SPI device pointer | |
22 | * @buffer: Buffer for device reads | |
23 | * @buffer_size: Size of buffer | |
24 | * @load_gpio: GPIO pin used to load input into device | |
25 | * @lock: Protects read sequences | |
26 | */ | |
27 | struct pisosr_gpio { | |
28 | struct gpio_chip chip; | |
29 | struct spi_device *spi; | |
30 | u8 *buffer; | |
31 | size_t buffer_size; | |
32 | struct gpio_desc *load_gpio; | |
33 | struct mutex lock; | |
34 | }; | |
35 | ||
36 | static int pisosr_gpio_refresh(struct pisosr_gpio *gpio) | |
37 | { | |
38 | int ret; | |
39 | ||
40 | mutex_lock(&gpio->lock); | |
41 | ||
42 | if (gpio->load_gpio) { | |
ea04a7ca | 43 | gpiod_set_value_cansleep(gpio->load_gpio, 1); |
df6df93c | 44 | udelay(1); /* registers load time (~10ns) */ |
ea04a7ca | 45 | gpiod_set_value_cansleep(gpio->load_gpio, 0); |
df6df93c AD |
46 | udelay(1); /* registers recovery time (~5ns) */ |
47 | } | |
48 | ||
49 | ret = spi_read(gpio->spi, gpio->buffer, gpio->buffer_size); | |
df6df93c AD |
50 | |
51 | mutex_unlock(&gpio->lock); | |
52 | ||
3e089d9f | 53 | return ret; |
df6df93c AD |
54 | } |
55 | ||
56 | static int pisosr_gpio_get_direction(struct gpio_chip *chip, | |
57 | unsigned offset) | |
58 | { | |
59 | /* This device always input */ | |
e42615ec | 60 | return GPIO_LINE_DIRECTION_IN; |
df6df93c AD |
61 | } |
62 | ||
63 | static int pisosr_gpio_direction_input(struct gpio_chip *chip, | |
64 | unsigned offset) | |
65 | { | |
66 | /* This device always input */ | |
67 | return 0; | |
68 | } | |
69 | ||
70 | static int pisosr_gpio_direction_output(struct gpio_chip *chip, | |
71 | unsigned offset, int value) | |
72 | { | |
73 | /* This device is input only */ | |
74 | return -EINVAL; | |
75 | } | |
76 | ||
77 | static int pisosr_gpio_get(struct gpio_chip *chip, unsigned offset) | |
78 | { | |
79 | struct pisosr_gpio *gpio = gpiochip_get_data(chip); | |
80 | ||
81 | /* Refresh may not always be needed */ | |
82 | pisosr_gpio_refresh(gpio); | |
83 | ||
84 | return (gpio->buffer[offset / 8] >> (offset % 8)) & 0x1; | |
85 | } | |
86 | ||
40bb5d72 MHT |
87 | static int pisosr_gpio_get_multiple(struct gpio_chip *chip, |
88 | unsigned long *mask, unsigned long *bits) | |
89 | { | |
90 | struct pisosr_gpio *gpio = gpiochip_get_data(chip); | |
608bd5fd WBG |
91 | unsigned long offset; |
92 | unsigned long gpio_mask; | |
93 | unsigned long buffer_state; | |
40bb5d72 MHT |
94 | |
95 | pisosr_gpio_refresh(gpio); | |
96 | ||
97 | bitmap_zero(bits, chip->ngpio); | |
608bd5fd WBG |
98 | for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) { |
99 | buffer_state = gpio->buffer[offset / 8] & gpio_mask; | |
100 | bitmap_set_value8(bits, buffer_state, offset); | |
40bb5d72 MHT |
101 | } |
102 | ||
103 | return 0; | |
104 | } | |
105 | ||
e35b5ab0 | 106 | static const struct gpio_chip template_chip = { |
df6df93c AD |
107 | .label = "pisosr-gpio", |
108 | .owner = THIS_MODULE, | |
109 | .get_direction = pisosr_gpio_get_direction, | |
110 | .direction_input = pisosr_gpio_direction_input, | |
111 | .direction_output = pisosr_gpio_direction_output, | |
112 | .get = pisosr_gpio_get, | |
40bb5d72 | 113 | .get_multiple = pisosr_gpio_get_multiple, |
df6df93c AD |
114 | .base = -1, |
115 | .ngpio = DEFAULT_NGPIO, | |
116 | .can_sleep = true, | |
117 | }; | |
118 | ||
212892b8 AD |
119 | static void pisosr_mutex_destroy(void *lock) |
120 | { | |
121 | mutex_destroy(lock); | |
122 | } | |
123 | ||
df6df93c AD |
124 | static int pisosr_gpio_probe(struct spi_device *spi) |
125 | { | |
126 | struct device *dev = &spi->dev; | |
127 | struct pisosr_gpio *gpio; | |
128 | int ret; | |
129 | ||
130 | gpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL); | |
131 | if (!gpio) | |
132 | return -ENOMEM; | |
133 | ||
df6df93c AD |
134 | gpio->chip = template_chip; |
135 | gpio->chip.parent = dev; | |
136 | of_property_read_u16(dev->of_node, "ngpios", &gpio->chip.ngpio); | |
137 | ||
138 | gpio->spi = spi; | |
139 | ||
140 | gpio->buffer_size = DIV_ROUND_UP(gpio->chip.ngpio, 8); | |
141 | gpio->buffer = devm_kzalloc(dev, gpio->buffer_size, GFP_KERNEL); | |
142 | if (!gpio->buffer) | |
143 | return -ENOMEM; | |
144 | ||
21d08ab9 | 145 | gpio->load_gpio = devm_gpiod_get_optional(dev, "load", GPIOD_OUT_LOW); |
308a028d KK |
146 | if (IS_ERR(gpio->load_gpio)) |
147 | return dev_err_probe(dev, PTR_ERR(gpio->load_gpio), | |
148 | "Unable to allocate load GPIO\n"); | |
df6df93c AD |
149 | |
150 | mutex_init(&gpio->lock); | |
212892b8 AD |
151 | ret = devm_add_action_or_reset(dev, pisosr_mutex_destroy, &gpio->lock); |
152 | if (ret) | |
153 | return ret; | |
df6df93c | 154 | |
212892b8 | 155 | ret = devm_gpiochip_add_data(dev, &gpio->chip, gpio); |
df6df93c AD |
156 | if (ret < 0) { |
157 | dev_err(dev, "Unable to register gpiochip\n"); | |
158 | return ret; | |
159 | } | |
160 | ||
161 | return 0; | |
162 | } | |
163 | ||
df6df93c AD |
164 | static const struct spi_device_id pisosr_gpio_id_table[] = { |
165 | { "pisosr-gpio", }, | |
166 | { /* sentinel */ } | |
167 | }; | |
168 | MODULE_DEVICE_TABLE(spi, pisosr_gpio_id_table); | |
169 | ||
170 | static const struct of_device_id pisosr_gpio_of_match_table[] = { | |
171 | { .compatible = "pisosr-gpio", }, | |
172 | { /* sentinel */ } | |
173 | }; | |
174 | MODULE_DEVICE_TABLE(of, pisosr_gpio_of_match_table); | |
175 | ||
176 | static struct spi_driver pisosr_gpio_driver = { | |
177 | .driver = { | |
178 | .name = "pisosr-gpio", | |
179 | .of_match_table = pisosr_gpio_of_match_table, | |
180 | }, | |
181 | .probe = pisosr_gpio_probe, | |
df6df93c AD |
182 | .id_table = pisosr_gpio_id_table, |
183 | }; | |
184 | module_spi_driver(pisosr_gpio_driver); | |
185 | ||
212892b8 | 186 | MODULE_AUTHOR("Andrew Davis <afd@ti.com>"); |
df6df93c AD |
187 | MODULE_DESCRIPTION("SPI Compatible PISO Shift Register GPIO Driver"); |
188 | MODULE_LICENSE("GPL v2"); |