Commit | Line | Data |
---|---|---|
04c17aa8 | 1 | /* |
f4574beb | 2 | * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. |
04c17aa8 TM |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; version 2 of the License. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program; if not, write to the Free Software | |
15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. | |
16 | */ | |
bb207ef1 | 17 | #include <linux/module.h> |
04c17aa8 TM |
18 | #include <linux/kernel.h> |
19 | #include <linux/pci.h> | |
5db1f873 | 20 | #include <linux/gpio/driver.h> |
38eb18a6 TM |
21 | #include <linux/interrupt.h> |
22 | #include <linux/irq.h> | |
349b6c53 | 23 | #include <linux/slab.h> |
38eb18a6 TM |
24 | |
25 | #define PCH_EDGE_FALLING 0 | |
26 | #define PCH_EDGE_RISING BIT(0) | |
27 | #define PCH_LEVEL_L BIT(1) | |
28 | #define PCH_LEVEL_H (BIT(0) | BIT(1)) | |
29 | #define PCH_EDGE_BOTH BIT(2) | |
30 | #define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2)) | |
31 | ||
32 | #define PCH_IRQ_BASE 24 | |
04c17aa8 | 33 | |
04c17aa8 TM |
34 | struct pch_regs { |
35 | u32 ien; | |
36 | u32 istatus; | |
37 | u32 idisp; | |
38 | u32 iclr; | |
39 | u32 imask; | |
40 | u32 imaskclr; | |
41 | u32 po; | |
42 | u32 pi; | |
43 | u32 pm; | |
44 | u32 im0; | |
45 | u32 im1; | |
e98bed7f TM |
46 | u32 reserved[3]; |
47 | u32 gpio_use_sel; | |
04c17aa8 TM |
48 | u32 reset; |
49 | }; | |
50 | ||
d4260e6d TM |
51 | enum pch_type_t { |
52 | INTEL_EG20T_PCH, | |
f4574beb TM |
53 | OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */ |
54 | OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */ | |
d4260e6d TM |
55 | }; |
56 | ||
57 | /* Specifies number of GPIO PINS */ | |
58 | static int gpio_pins[] = { | |
59 | [INTEL_EG20T_PCH] = 12, | |
60 | [OKISEMI_ML7223m_IOH] = 8, | |
61 | [OKISEMI_ML7223n_IOH] = 8, | |
62 | }; | |
63 | ||
04c17aa8 TM |
64 | /** |
65 | * struct pch_gpio_reg_data - The register store data. | |
38eb18a6 TM |
66 | * @ien_reg: To store contents of IEN register. |
67 | * @imask_reg: To store contents of IMASK register. | |
04c17aa8 TM |
68 | * @po_reg: To store contents of PO register. |
69 | * @pm_reg: To store contents of PM register. | |
e98bed7f TM |
70 | * @im0_reg: To store contents of IM0 register. |
71 | * @im1_reg: To store contents of IM1 register. | |
72 | * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register. | |
73 | * (Only ML7223 Bus-n) | |
04c17aa8 TM |
74 | */ |
75 | struct pch_gpio_reg_data { | |
38eb18a6 TM |
76 | u32 ien_reg; |
77 | u32 imask_reg; | |
04c17aa8 TM |
78 | u32 po_reg; |
79 | u32 pm_reg; | |
e98bed7f TM |
80 | u32 im0_reg; |
81 | u32 im1_reg; | |
82 | u32 gpio_use_sel_reg; | |
04c17aa8 TM |
83 | }; |
84 | ||
85 | /** | |
86 | * struct pch_gpio - GPIO private data structure. | |
87 | * @base: PCI base address of Memory mapped I/O register. | |
88 | * @reg: Memory mapped PCH GPIO register list. | |
89 | * @dev: Pointer to device structure. | |
90 | * @gpio: Data for GPIO infrastructure. | |
91 | * @pch_gpio_reg: Memory mapped Register data is saved here | |
92 | * when suspend. | |
38eb18a6 TM |
93 | * @lock: Used for register access protection |
94 | * @irq_base: Save base of IRQ number for interrupt | |
d4260e6d | 95 | * @ioh: IOH ID |
7cb6580c | 96 | * @spinlock: Used for register access protection |
04c17aa8 TM |
97 | */ |
98 | struct pch_gpio { | |
99 | void __iomem *base; | |
100 | struct pch_regs __iomem *reg; | |
101 | struct device *dev; | |
102 | struct gpio_chip gpio; | |
103 | struct pch_gpio_reg_data pch_gpio_reg; | |
38eb18a6 | 104 | int irq_base; |
d4260e6d | 105 | enum pch_type_t ioh; |
d568a681 | 106 | spinlock_t spinlock; |
04c17aa8 TM |
107 | }; |
108 | ||
109 | static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val) | |
110 | { | |
111 | u32 reg_val; | |
510f4871 | 112 | struct pch_gpio *chip = gpiochip_get_data(gpio); |
7cb6580c | 113 | unsigned long flags; |
04c17aa8 | 114 | |
7cb6580c | 115 | spin_lock_irqsave(&chip->spinlock, flags); |
04c17aa8 TM |
116 | reg_val = ioread32(&chip->reg->po); |
117 | if (val) | |
118 | reg_val |= (1 << nr); | |
119 | else | |
120 | reg_val &= ~(1 << nr); | |
121 | ||
122 | iowrite32(reg_val, &chip->reg->po); | |
7cb6580c | 123 | spin_unlock_irqrestore(&chip->spinlock, flags); |
04c17aa8 TM |
124 | } |
125 | ||
126 | static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr) | |
127 | { | |
510f4871 | 128 | struct pch_gpio *chip = gpiochip_get_data(gpio); |
04c17aa8 | 129 | |
166814d8 | 130 | return (ioread32(&chip->reg->pi) >> nr) & 1; |
04c17aa8 TM |
131 | } |
132 | ||
133 | static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, | |
134 | int val) | |
135 | { | |
510f4871 | 136 | struct pch_gpio *chip = gpiochip_get_data(gpio); |
04c17aa8 TM |
137 | u32 pm; |
138 | u32 reg_val; | |
7cb6580c | 139 | unsigned long flags; |
04c17aa8 | 140 | |
7cb6580c | 141 | spin_lock_irqsave(&chip->spinlock, flags); |
04c17aa8 TM |
142 | |
143 | reg_val = ioread32(&chip->reg->po); | |
144 | if (val) | |
145 | reg_val |= (1 << nr); | |
146 | else | |
147 | reg_val &= ~(1 << nr); | |
88aab934 | 148 | iowrite32(reg_val, &chip->reg->po); |
2ddf6cd6 DK |
149 | |
150 | pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); | |
151 | pm |= (1 << nr); | |
152 | iowrite32(pm, &chip->reg->pm); | |
153 | ||
7cb6580c | 154 | spin_unlock_irqrestore(&chip->spinlock, flags); |
04c17aa8 TM |
155 | |
156 | return 0; | |
157 | } | |
158 | ||
159 | static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) | |
160 | { | |
510f4871 | 161 | struct pch_gpio *chip = gpiochip_get_data(gpio); |
04c17aa8 | 162 | u32 pm; |
7cb6580c | 163 | unsigned long flags; |
04c17aa8 | 164 | |
7cb6580c | 165 | spin_lock_irqsave(&chip->spinlock, flags); |
d4260e6d | 166 | pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1); |
04c17aa8 TM |
167 | pm &= ~(1 << nr); |
168 | iowrite32(pm, &chip->reg->pm); | |
7cb6580c | 169 | spin_unlock_irqrestore(&chip->spinlock, flags); |
04c17aa8 TM |
170 | |
171 | return 0; | |
172 | } | |
173 | ||
a092e19b | 174 | #ifdef CONFIG_PM |
04c17aa8 TM |
175 | /* |
176 | * Save register configuration and disable interrupts. | |
177 | */ | |
178 | static void pch_gpio_save_reg_conf(struct pch_gpio *chip) | |
179 | { | |
38eb18a6 TM |
180 | chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien); |
181 | chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask); | |
04c17aa8 TM |
182 | chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po); |
183 | chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm); | |
e98bed7f TM |
184 | chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0); |
185 | if (chip->ioh == INTEL_EG20T_PCH) | |
186 | chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1); | |
187 | if (chip->ioh == OKISEMI_ML7223n_IOH) | |
188 | chip->pch_gpio_reg.gpio_use_sel_reg =\ | |
189 | ioread32(&chip->reg->gpio_use_sel); | |
04c17aa8 TM |
190 | } |
191 | ||
192 | /* | |
193 | * This function restores the register configuration of the GPIO device. | |
194 | */ | |
195 | static void pch_gpio_restore_reg_conf(struct pch_gpio *chip) | |
196 | { | |
38eb18a6 TM |
197 | iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien); |
198 | iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask); | |
04c17aa8 TM |
199 | /* to store contents of PO register */ |
200 | iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po); | |
201 | /* to store contents of PM register */ | |
202 | iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm); | |
e98bed7f TM |
203 | iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0); |
204 | if (chip->ioh == INTEL_EG20T_PCH) | |
205 | iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1); | |
206 | if (chip->ioh == OKISEMI_ML7223n_IOH) | |
207 | iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, | |
208 | &chip->reg->gpio_use_sel); | |
04c17aa8 | 209 | } |
a092e19b | 210 | #endif |
04c17aa8 | 211 | |
38eb18a6 TM |
212 | static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset) |
213 | { | |
510f4871 | 214 | struct pch_gpio *chip = gpiochip_get_data(gpio); |
38eb18a6 TM |
215 | return chip->irq_base + offset; |
216 | } | |
217 | ||
04c17aa8 TM |
218 | static void pch_gpio_setup(struct pch_gpio *chip) |
219 | { | |
220 | struct gpio_chip *gpio = &chip->gpio; | |
221 | ||
222 | gpio->label = dev_name(chip->dev); | |
58383c78 | 223 | gpio->parent = chip->dev; |
04c17aa8 TM |
224 | gpio->owner = THIS_MODULE; |
225 | gpio->direction_input = pch_gpio_direction_input; | |
226 | gpio->get = pch_gpio_get; | |
227 | gpio->direction_output = pch_gpio_direction_output; | |
228 | gpio->set = pch_gpio_set; | |
229 | gpio->dbg_show = NULL; | |
230 | gpio->base = -1; | |
d4260e6d | 231 | gpio->ngpio = gpio_pins[chip->ioh]; |
9fb1f39e | 232 | gpio->can_sleep = false; |
38eb18a6 TM |
233 | gpio->to_irq = pch_gpio_to_irq; |
234 | } | |
235 | ||
236 | static int pch_irq_type(struct irq_data *d, unsigned int type) | |
237 | { | |
38eb18a6 TM |
238 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
239 | struct pch_gpio *chip = gc->private; | |
df9541a6 TG |
240 | u32 im, im_pos, val; |
241 | u32 __iomem *im_reg; | |
242 | unsigned long flags; | |
243 | int ch, irq = d->irq; | |
38eb18a6 TM |
244 | |
245 | ch = irq - chip->irq_base; | |
246 | if (irq <= chip->irq_base + 7) { | |
247 | im_reg = &chip->reg->im0; | |
248 | im_pos = ch; | |
249 | } else { | |
250 | im_reg = &chip->reg->im1; | |
251 | im_pos = ch - 8; | |
252 | } | |
253 | dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d\n", | |
254 | __func__, irq, type, ch, im_pos); | |
255 | ||
256 | spin_lock_irqsave(&chip->spinlock, flags); | |
257 | ||
258 | switch (type) { | |
259 | case IRQ_TYPE_EDGE_RISING: | |
260 | val = PCH_EDGE_RISING; | |
261 | break; | |
262 | case IRQ_TYPE_EDGE_FALLING: | |
263 | val = PCH_EDGE_FALLING; | |
264 | break; | |
265 | case IRQ_TYPE_EDGE_BOTH: | |
266 | val = PCH_EDGE_BOTH; | |
267 | break; | |
268 | case IRQ_TYPE_LEVEL_HIGH: | |
269 | val = PCH_LEVEL_H; | |
270 | break; | |
271 | case IRQ_TYPE_LEVEL_LOW: | |
272 | val = PCH_LEVEL_L; | |
273 | break; | |
38eb18a6 | 274 | default: |
df9541a6 | 275 | goto unlock; |
38eb18a6 TM |
276 | } |
277 | ||
278 | /* Set interrupt mode */ | |
279 | im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4)); | |
280 | iowrite32(im | (val << (im_pos * 4)), im_reg); | |
281 | ||
df9541a6 TG |
282 | /* And the handler */ |
283 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
2456d869 | 284 | irq_set_handler_locked(d, handle_level_irq); |
df9541a6 | 285 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
2456d869 | 286 | irq_set_handler_locked(d, handle_edge_irq); |
38eb18a6 | 287 | |
df9541a6 | 288 | unlock: |
38eb18a6 | 289 | spin_unlock_irqrestore(&chip->spinlock, flags); |
38eb18a6 TM |
290 | return 0; |
291 | } | |
292 | ||
293 | static void pch_irq_unmask(struct irq_data *d) | |
294 | { | |
295 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
296 | struct pch_gpio *chip = gc->private; | |
297 | ||
298 | iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr); | |
299 | } | |
300 | ||
301 | static void pch_irq_mask(struct irq_data *d) | |
302 | { | |
303 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
304 | struct pch_gpio *chip = gc->private; | |
305 | ||
306 | iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask); | |
307 | } | |
308 | ||
df9541a6 TG |
309 | static void pch_irq_ack(struct irq_data *d) |
310 | { | |
311 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
312 | struct pch_gpio *chip = gc->private; | |
313 | ||
314 | iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr); | |
315 | } | |
316 | ||
38eb18a6 TM |
317 | static irqreturn_t pch_gpio_handler(int irq, void *dev_id) |
318 | { | |
319 | struct pch_gpio *chip = dev_id; | |
320 | u32 reg_val = ioread32(&chip->reg->istatus); | |
df9541a6 | 321 | int i, ret = IRQ_NONE; |
38eb18a6 TM |
322 | |
323 | for (i = 0; i < gpio_pins[chip->ioh]; i++) { | |
324 | if (reg_val & BIT(i)) { | |
325 | dev_dbg(chip->dev, "%s:[%d]:irq=%d status=0x%x\n", | |
326 | __func__, i, irq, reg_val); | |
38eb18a6 TM |
327 | generic_handle_irq(chip->irq_base + i); |
328 | ret = IRQ_HANDLED; | |
329 | } | |
330 | } | |
331 | return ret; | |
332 | } | |
333 | ||
09445a10 BG |
334 | static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip, |
335 | unsigned int irq_start, | |
336 | unsigned int num) | |
38eb18a6 TM |
337 | { |
338 | struct irq_chip_generic *gc; | |
339 | struct irq_chip_type *ct; | |
e0fc5a1b | 340 | int rv; |
38eb18a6 | 341 | |
e0fc5a1b BG |
342 | gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start, |
343 | chip->base, handle_simple_irq); | |
09445a10 BG |
344 | if (!gc) |
345 | return -ENOMEM; | |
346 | ||
38eb18a6 TM |
347 | gc->private = chip; |
348 | ct = gc->chip_types; | |
349 | ||
df9541a6 | 350 | ct->chip.irq_ack = pch_irq_ack; |
38eb18a6 TM |
351 | ct->chip.irq_mask = pch_irq_mask; |
352 | ct->chip.irq_unmask = pch_irq_unmask; | |
353 | ct->chip.irq_set_type = pch_irq_type; | |
354 | ||
e0fc5a1b BG |
355 | rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num), |
356 | IRQ_GC_INIT_MASK_CACHE, | |
357 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | |
09445a10 | 358 | |
e0fc5a1b | 359 | return rv; |
04c17aa8 TM |
360 | } |
361 | ||
3836309d | 362 | static int pch_gpio_probe(struct pci_dev *pdev, |
04c17aa8 TM |
363 | const struct pci_device_id *id) |
364 | { | |
365 | s32 ret; | |
366 | struct pch_gpio *chip; | |
38eb18a6 | 367 | int irq_base; |
df9541a6 | 368 | u32 msk; |
04c17aa8 | 369 | |
6ad02b29 | 370 | chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); |
04c17aa8 TM |
371 | if (chip == NULL) |
372 | return -ENOMEM; | |
373 | ||
374 | chip->dev = &pdev->dev; | |
6ad02b29 | 375 | ret = pcim_enable_device(pdev); |
04c17aa8 TM |
376 | if (ret) { |
377 | dev_err(&pdev->dev, "%s : pci_enable_device FAILED", __func__); | |
6ad02b29 | 378 | return ret; |
04c17aa8 TM |
379 | } |
380 | ||
6ad02b29 | 381 | ret = pcim_iomap_regions(pdev, 1 << 1, KBUILD_MODNAME); |
04c17aa8 TM |
382 | if (ret) { |
383 | dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret); | |
6ad02b29 | 384 | return ret; |
04c17aa8 TM |
385 | } |
386 | ||
6ad02b29 | 387 | chip->base = pcim_iomap_table(pdev)[1]; |
04c17aa8 | 388 | |
d4260e6d TM |
389 | if (pdev->device == 0x8803) |
390 | chip->ioh = INTEL_EG20T_PCH; | |
391 | else if (pdev->device == 0x8014) | |
392 | chip->ioh = OKISEMI_ML7223m_IOH; | |
393 | else if (pdev->device == 0x8043) | |
394 | chip->ioh = OKISEMI_ML7223n_IOH; | |
395 | ||
04c17aa8 TM |
396 | chip->reg = chip->base; |
397 | pci_set_drvdata(pdev, chip); | |
d166370a | 398 | spin_lock_init(&chip->spinlock); |
04c17aa8 | 399 | pch_gpio_setup(chip); |
a9f1a3e4 | 400 | #ifdef CONFIG_OF_GPIO |
1cfadea8 | 401 | chip->gpio.of_node = pdev->dev.of_node; |
a9f1a3e4 | 402 | #endif |
6ad02b29 | 403 | ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip); |
04c17aa8 TM |
404 | if (ret) { |
405 | dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n"); | |
6ad02b29 | 406 | return ret; |
04c17aa8 TM |
407 | } |
408 | ||
f57f3e60 BG |
409 | irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, |
410 | gpio_pins[chip->ioh], NUMA_NO_NODE); | |
38eb18a6 TM |
411 | if (irq_base < 0) { |
412 | dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n"); | |
413 | chip->irq_base = -1; | |
6ad02b29 | 414 | return 0; |
38eb18a6 TM |
415 | } |
416 | chip->irq_base = irq_base; | |
417 | ||
df9541a6 TG |
418 | /* Mask all interrupts, but enable them */ |
419 | msk = (1 << gpio_pins[chip->ioh]) - 1; | |
420 | iowrite32(msk, &chip->reg->imask); | |
421 | iowrite32(msk, &chip->reg->ien); | |
422 | ||
f57f3e60 BG |
423 | ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler, |
424 | IRQF_SHARED, KBUILD_MODNAME, chip); | |
6ad02b29 | 425 | if (ret) { |
38eb18a6 TM |
426 | dev_err(&pdev->dev, |
427 | "%s request_irq failed\n", __func__); | |
6ad02b29 | 428 | return ret; |
38eb18a6 TM |
429 | } |
430 | ||
6ad02b29 | 431 | return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]); |
04c17aa8 TM |
432 | } |
433 | ||
434 | #ifdef CONFIG_PM | |
435 | static int pch_gpio_suspend(struct pci_dev *pdev, pm_message_t state) | |
436 | { | |
437 | s32 ret; | |
438 | struct pch_gpio *chip = pci_get_drvdata(pdev); | |
d568a681 | 439 | unsigned long flags; |
04c17aa8 | 440 | |
d568a681 | 441 | spin_lock_irqsave(&chip->spinlock, flags); |
04c17aa8 | 442 | pch_gpio_save_reg_conf(chip); |
d568a681 | 443 | spin_unlock_irqrestore(&chip->spinlock, flags); |
04c17aa8 TM |
444 | |
445 | ret = pci_save_state(pdev); | |
446 | if (ret) { | |
447 | dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret); | |
448 | return ret; | |
449 | } | |
450 | pci_disable_device(pdev); | |
451 | pci_set_power_state(pdev, PCI_D0); | |
452 | ret = pci_enable_wake(pdev, PCI_D0, 1); | |
453 | if (ret) | |
454 | dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret); | |
455 | ||
456 | return 0; | |
457 | } | |
458 | ||
459 | static int pch_gpio_resume(struct pci_dev *pdev) | |
460 | { | |
461 | s32 ret; | |
462 | struct pch_gpio *chip = pci_get_drvdata(pdev); | |
d568a681 | 463 | unsigned long flags; |
04c17aa8 TM |
464 | |
465 | ret = pci_enable_wake(pdev, PCI_D0, 0); | |
466 | ||
467 | pci_set_power_state(pdev, PCI_D0); | |
468 | ret = pci_enable_device(pdev); | |
469 | if (ret) { | |
470 | dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret); | |
471 | return ret; | |
472 | } | |
473 | pci_restore_state(pdev); | |
474 | ||
d568a681 | 475 | spin_lock_irqsave(&chip->spinlock, flags); |
04c17aa8 TM |
476 | iowrite32(0x01, &chip->reg->reset); |
477 | iowrite32(0x00, &chip->reg->reset); | |
478 | pch_gpio_restore_reg_conf(chip); | |
d568a681 | 479 | spin_unlock_irqrestore(&chip->spinlock, flags); |
04c17aa8 TM |
480 | |
481 | return 0; | |
482 | } | |
483 | #else | |
484 | #define pch_gpio_suspend NULL | |
485 | #define pch_gpio_resume NULL | |
486 | #endif | |
487 | ||
bc786cce | 488 | #define PCI_VENDOR_ID_ROHM 0x10DB |
14f4a883 | 489 | static const struct pci_device_id pch_gpio_pcidev_id[] = { |
04c17aa8 | 490 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) }, |
bc786cce | 491 | { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) }, |
c3520a1a | 492 | { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) }, |
868fea05 | 493 | { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) }, |
04c17aa8 TM |
494 | { 0, } |
495 | }; | |
19234cdd | 496 | MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id); |
04c17aa8 TM |
497 | |
498 | static struct pci_driver pch_gpio_driver = { | |
499 | .name = "pch_gpio", | |
500 | .id_table = pch_gpio_pcidev_id, | |
501 | .probe = pch_gpio_probe, | |
04c17aa8 TM |
502 | .suspend = pch_gpio_suspend, |
503 | .resume = pch_gpio_resume | |
504 | }; | |
505 | ||
93baa65f | 506 | module_pci_driver(pch_gpio_driver); |
04c17aa8 TM |
507 | |
508 | MODULE_DESCRIPTION("PCH GPIO PCI Driver"); | |
509 | MODULE_LICENSE("GPL"); |