[linux-2.6-block.git] / drivers / gpio / gpio-pch.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
 */
#include <linux/bits.h>
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/slab.h>

#define PCH_EDGE_FALLING	0
#define PCH_EDGE_RISING		1
#define PCH_LEVEL_L		2
#define PCH_LEVEL_H		3
#define PCH_EDGE_BOTH		4
#define PCH_IM_MASK		GENMASK(2, 0)

#define PCH_IRQ_BASE		24

struct pch_regs {
	u32	ien;
	u32	istatus;
	u32	idisp;
	u32	iclr;
	u32	imask;
	u32	imaskclr;
	u32	po;
	u32	pi;
	u32	pm;
	u32	im0;
	u32	im1;
	u32	reserved[3];
	u32	gpio_use_sel;
	u32	reset;
};

enum pch_type_t {
	INTEL_EG20T_PCH,
	OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
	OKISEMI_ML7223n_IOH  /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
};

/* Specifies number of GPIO PINS */
static int gpio_pins[] = {
	[INTEL_EG20T_PCH] = 12,
	[OKISEMI_ML7223m_IOH] = 8,
	[OKISEMI_ML7223n_IOH] = 8,
};

/**
 * struct pch_gpio_reg_data - The register store data.
 * @ien_reg:	To store contents of IEN register.
 * @imask_reg:	To store contents of IMASK register.
 * @po_reg:	To store contents of PO register.
 * @pm_reg:	To store contents of PM register.
 * @im0_reg:	To store contents of IM0 register.
 * @im1_reg:	To store contents of IM1 register.
 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
 *		       (Only ML7223 Bus-n)
 */
struct pch_gpio_reg_data {
	u32 ien_reg;
	u32 imask_reg;
	u32 po_reg;
	u32 pm_reg;
	u32 im0_reg;
	u32 im1_reg;
	u32 gpio_use_sel_reg;
};

/**
 * struct pch_gpio - GPIO private data structure.
 * @base:			PCI base address of Memory mapped I/O register.
 * @reg:			Memory mapped PCH GPIO register list.
 * @dev:			Pointer to device structure.
 * @gpio:			Data for GPIO infrastructure.
 * @pch_gpio_reg:		Memory mapped Register data is saved here
 *				when suspend.
 * @lock:			Used for register access protection
 * @irq_base:		Save base of IRQ number for interrupt
 * @ioh:		IOH ID
 * @spinlock:		Used for register access protection
 */
struct pch_gpio {
	void __iomem *base;
	struct pch_regs __iomem *reg;
	struct device *dev;
	struct gpio_chip gpio;
	struct pch_gpio_reg_data pch_gpio_reg;
	int irq_base;
	enum pch_type_t ioh;
	spinlock_t spinlock;
};

static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
{
	u32 reg_val;
	struct pch_gpio *chip =	gpiochip_get_data(gpio);
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	reg_val = ioread32(&chip->reg->po);
	if (val)
		reg_val |= BIT(nr);
	else
		reg_val &= ~BIT(nr);

	iowrite32(reg_val, &chip->reg->po);
	spin_unlock_irqrestore(&chip->spinlock, flags);
}

static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr)
{
	struct pch_gpio *chip =	gpiochip_get_data(gpio);

	return !!(ioread32(&chip->reg->pi) & BIT(nr));
}

static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
				     int val)
{
	struct pch_gpio *chip =	gpiochip_get_data(gpio);
	u32 pm;
	u32 reg_val;
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);

	reg_val = ioread32(&chip->reg->po);
	if (val)
		reg_val |= BIT(nr);
	else
		reg_val &= ~BIT(nr);
	iowrite32(reg_val, &chip->reg->po);

	pm = ioread32(&chip->reg->pm);
	pm &= BIT(gpio_pins[chip->ioh]) - 1;
	pm |= BIT(nr);
	iowrite32(pm, &chip->reg->pm);

	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
{
	struct pch_gpio *chip =	gpiochip_get_data(gpio);
	u32 pm;
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	pm = ioread32(&chip->reg->pm);
	pm &= BIT(gpio_pins[chip->ioh]) - 1;
	pm &= ~BIT(nr);
	iowrite32(pm, &chip->reg->pm);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

/*
 * Save register configuration and disable interrupts.
 */
static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
{
	chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
	chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
	chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
	chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
	chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
	if (chip->ioh == INTEL_EG20T_PCH)
		chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
	if (chip->ioh == OKISEMI_ML7223n_IOH)
		chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
}

/*
 * This function restores the register configuration of the GPIO device.
 */
static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
{
	iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
	iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
	/* to store contents of PO register */
	iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
	/* to store contents of PM register */
	iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
	iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
	if (chip->ioh == INTEL_EG20T_PCH)
		iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
	if (chip->ioh == OKISEMI_ML7223n_IOH)
		iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
}

static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned int offset)
{
	struct pch_gpio *chip = gpiochip_get_data(gpio);

	return chip->irq_base + offset;
}

static void pch_gpio_setup(struct pch_gpio *chip)
{
	struct gpio_chip *gpio = &chip->gpio;

	gpio->label = dev_name(chip->dev);
	gpio->parent = chip->dev;
	gpio->owner = THIS_MODULE;
	gpio->direction_input = pch_gpio_direction_input;
	gpio->get = pch_gpio_get;
	gpio->direction_output = pch_gpio_direction_output;
	gpio->set = pch_gpio_set;
	gpio->base = -1;
	gpio->ngpio = gpio_pins[chip->ioh];
	gpio->can_sleep = false;
	gpio->to_irq = pch_gpio_to_irq;
}

static int pch_irq_type(struct irq_data *d, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;
	u32 im, im_pos, val;
	u32 __iomem *im_reg;
	unsigned long flags;
	int ch, irq = d->irq;

	ch = irq - chip->irq_base;
	if (irq < chip->irq_base + 8) {
		im_reg = &chip->reg->im0;
		im_pos = ch - 0;
	} else {
		im_reg = &chip->reg->im1;
		im_pos = ch - 8;
	}
	dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		val = PCH_EDGE_RISING;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		val = PCH_EDGE_FALLING;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		val = PCH_EDGE_BOTH;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		val = PCH_LEVEL_H;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		val = PCH_LEVEL_L;
		break;
	default:
		return 0;
	}

	spin_lock_irqsave(&chip->spinlock, flags);

	/* Set interrupt mode */
	im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
	iowrite32(im | (val << (im_pos * 4)), im_reg);

	/* And the handler */
	if (type & IRQ_TYPE_LEVEL_MASK)
		irq_set_handler_locked(d, handle_level_irq);
	else if (type & IRQ_TYPE_EDGE_BOTH)
		irq_set_handler_locked(d, handle_edge_irq);

	spin_unlock_irqrestore(&chip->spinlock, flags);
	return 0;
}

static void pch_irq_unmask(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;

	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
}

static void pch_irq_mask(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;

	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
}

static void pch_irq_ack(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;

	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
}

static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
{
	struct pch_gpio *chip = dev_id;
	unsigned long reg_val = ioread32(&chip->reg->istatus);
	int i;

	dev_vdbg(chip->dev, "irq=%d  status=0x%lx\n", irq, reg_val);

	reg_val &= BIT(gpio_pins[chip->ioh]) - 1;

	for_each_set_bit(i, &reg_val, gpio_pins[chip->ioh])
		generic_handle_irq(chip->irq_base + i);

	return IRQ_RETVAL(reg_val);
}

static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
				       unsigned int irq_start,
				       unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int rv;

	gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
					 chip->base, handle_simple_irq);
	if (!gc)
		return -ENOMEM;

	gc->private = chip;
	ct = gc->chip_types;

	ct->chip.irq_ack = pch_irq_ack;
	ct->chip.irq_mask = pch_irq_mask;
	ct->chip.irq_unmask = pch_irq_unmask;
	ct->chip.irq_set_type = pch_irq_type;

	rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
					 IRQ_GC_INIT_MASK_CACHE,
					 IRQ_NOREQUEST | IRQ_NOPROBE, 0);

	return rv;
}

static int pch_gpio_probe(struct pci_dev *pdev,
				    const struct pci_device_id *id)
{
	s32 ret;
	struct pch_gpio *chip;
	int irq_base;

	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	if (chip == NULL)
		return -ENOMEM;

	chip->dev = &pdev->dev;
	ret = pcim_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "pci_enable_device FAILED");
		return ret;
	}

	ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
	if (ret) {
		dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
		return ret;
	}

	chip->base = pcim_iomap_table(pdev)[1];

	if (pdev->device == 0x8803)
		chip->ioh = INTEL_EG20T_PCH;
	else if (pdev->device == 0x8014)
		chip->ioh = OKISEMI_ML7223m_IOH;
	else if (pdev->device == 0x8043)
		chip->ioh = OKISEMI_ML7223n_IOH;

	chip->reg = chip->base;
	pci_set_drvdata(pdev, chip);
	spin_lock_init(&chip->spinlock);
	pch_gpio_setup(chip);

	ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip);
	if (ret) {
		dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
		return ret;
	}

	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
					gpio_pins[chip->ioh], NUMA_NO_NODE);
	if (irq_base < 0) {
		dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
		chip->irq_base = -1;
		return 0;
	}
	chip->irq_base = irq_base;

	/* Mask all interrupts, but enable them */
	iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
	iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);

	ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler,
			       IRQF_SHARED, KBUILD_MODNAME, chip);
	if (ret) {
		dev_err(&pdev->dev, "request_irq failed\n");
		return ret;
	}

	return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
}

static int __maybe_unused pch_gpio_suspend(struct device *dev)
{
	struct pch_gpio *chip = dev_get_drvdata(dev);
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	pch_gpio_save_reg_conf(chip);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

static int __maybe_unused pch_gpio_resume(struct device *dev)
{
	struct pch_gpio *chip = dev_get_drvdata(dev);
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	iowrite32(0x01, &chip->reg->reset);
	iowrite32(0x00, &chip->reg->reset);
	pch_gpio_restore_reg_conf(chip);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);

static const struct pci_device_id pch_gpio_pcidev_id[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);

static struct pci_driver pch_gpio_driver = {
	.name = "pch_gpio",
	.id_table = pch_gpio_pcidev_id,
	.probe = pch_gpio_probe,
	.driver = {
		.pm = &pch_gpio_pm_ops,
	},
};

module_pci_driver(pch_gpio_driver);

MODULE_DESCRIPTION("PCH GPIO PCI Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9b8bf5bf	1	// SPDX-License-Identifier: GPL-2.0
04c17aa8	2	/*
f4574beb	3	* Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
04c17aa8	4	*/
5c85418a	5	#include <linux/bits.h>
5db1f873	6	#include <linux/gpio/driver.h>
38eb18a6 TM	7	#include <linux/interrupt.h>
38eb18a6 TM	8	#include <linux/irq.h>
3e1884f8 AS	9	#include <linux/kernel.h>
	10	#include <linux/module.h>
	11	#include <linux/pci.h>
349b6c53	12	#include <linux/slab.h>
38eb18a6 TM	13
38eb18a6 TM	14	#define PCH_EDGE_FALLING 0
5c85418a AS	15	#define PCH_EDGE_RISING 1
	16	#define PCH_LEVEL_L 2
	17	#define PCH_LEVEL_H 3
	18	#define PCH_EDGE_BOTH 4
	19	#define PCH_IM_MASK GENMASK(2, 0)
38eb18a6 TM	20
38eb18a6 TM	21	#define PCH_IRQ_BASE 24
04c17aa8	22
04c17aa8 TM	23	struct pch_regs {
	24	u32 ien;
	25	u32 istatus;
	26	u32 idisp;
	27	u32 iclr;
	28	u32 imask;
	29	u32 imaskclr;
	30	u32 po;
	31	u32 pi;
	32	u32 pm;
	33	u32 im0;
	34	u32 im1;
e98bed7f TM	35	u32 reserved[3];
e98bed7f TM	36	u32 gpio_use_sel;
04c17aa8 TM	37	u32 reset;
	38	};
	39
d4260e6d TM	40	enum pch_type_t {
d4260e6d TM	41	INTEL_EG20T_PCH,
f4574beb TM	42	OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
f4574beb TM	43	OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
d4260e6d TM	44	};
	45
	46	/* Specifies number of GPIO PINS */
	47	static int gpio_pins[] = {
	48	[INTEL_EG20T_PCH] = 12,
	49	[OKISEMI_ML7223m_IOH] = 8,
	50	[OKISEMI_ML7223n_IOH] = 8,
	51	};
	52
04c17aa8 TM	53	/**
04c17aa8 TM	54	* struct pch_gpio_reg_data - The register store data.
38eb18a6 TM	55	* @ien_reg: To store contents of IEN register.
38eb18a6 TM	56	* @imask_reg: To store contents of IMASK register.
04c17aa8 TM	57	* @po_reg: To store contents of PO register.
04c17aa8 TM	58	* @pm_reg: To store contents of PM register.
e98bed7f TM	59	* @im0_reg: To store contents of IM0 register.
	60	* @im1_reg: To store contents of IM1 register.
	61	* @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
	62	* (Only ML7223 Bus-n)
04c17aa8 TM	63	*/
04c17aa8 TM	64	struct pch_gpio_reg_data {
38eb18a6 TM	65	u32 ien_reg;
38eb18a6 TM	66	u32 imask_reg;
04c17aa8 TM	67	u32 po_reg;
04c17aa8 TM	68	u32 pm_reg;
e98bed7f TM	69	u32 im0_reg;
	70	u32 im1_reg;
	71	u32 gpio_use_sel_reg;
04c17aa8 TM	72	};
	73
	74	/**
	75	* struct pch_gpio - GPIO private data structure.
	76	* @base: PCI base address of Memory mapped I/O register.
	77	* @reg: Memory mapped PCH GPIO register list.
	78	* @dev: Pointer to device structure.
	79	* @gpio: Data for GPIO infrastructure.
	80	* @pch_gpio_reg: Memory mapped Register data is saved here
	81	* when suspend.
38eb18a6 TM	82	* @lock: Used for register access protection
38eb18a6 TM	83	* @irq_base: Save base of IRQ number for interrupt
d4260e6d	84	* @ioh: IOH ID
7cb6580c	85	* @spinlock: Used for register access protection
04c17aa8 TM	86	*/
	87	struct pch_gpio {
	88	void __iomem *base;
	89	struct pch_regs __iomem *reg;
	90	struct device *dev;
	91	struct gpio_chip gpio;
	92	struct pch_gpio_reg_data pch_gpio_reg;
38eb18a6	93	int irq_base;
d4260e6d	94	enum pch_type_t ioh;
d568a681	95	spinlock_t spinlock;
04c17aa8 TM	96	};
04c17aa8 TM	97
0c106a23	98	static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
04c17aa8 TM	99	{
04c17aa8 TM	100	u32 reg_val;
510f4871	101	struct pch_gpio *chip = gpiochip_get_data(gpio);
7cb6580c	102	unsigned long flags;
04c17aa8	103
7cb6580c	104	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8 TM	105	reg_val = ioread32(&chip->reg->po);
04c17aa8 TM	106	if (val)
5c85418a	107	reg_val \|= BIT(nr);
04c17aa8	108	else
5c85418a	109	reg_val &= ~BIT(nr);
04c17aa8 TM	110
04c17aa8 TM	111	iowrite32(reg_val, &chip->reg->po);
7cb6580c	112	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	113	}
04c17aa8 TM	114
0c106a23	115	static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr)
04c17aa8	116	{
510f4871	117	struct pch_gpio *chip = gpiochip_get_data(gpio);
04c17aa8	118
5c85418a	119	return !!(ioread32(&chip->reg->pi) & BIT(nr));
04c17aa8 TM	120	}
04c17aa8 TM	121
0c106a23	122	static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
04c17aa8 TM	123	int val)
04c17aa8 TM	124	{
510f4871	125	struct pch_gpio *chip = gpiochip_get_data(gpio);
04c17aa8 TM	126	u32 pm;
04c17aa8 TM	127	u32 reg_val;
7cb6580c	128	unsigned long flags;
04c17aa8	129
7cb6580c	130	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8 TM	131
	132	reg_val = ioread32(&chip->reg->po);
	133	if (val)
5c85418a	134	reg_val \|= BIT(nr);
04c17aa8	135	else
5c85418a	136	reg_val &= ~BIT(nr);
88aab934	137	iowrite32(reg_val, &chip->reg->po);
2ddf6cd6	138
5c85418a AS	139	pm = ioread32(&chip->reg->pm);
	140	pm &= BIT(gpio_pins[chip->ioh]) - 1;
	141	pm \|= BIT(nr);
2ddf6cd6 DK	142	iowrite32(pm, &chip->reg->pm);
2ddf6cd6 DK	143
7cb6580c	144	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	145
	146	return 0;
	147	}
	148
0c106a23	149	static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
04c17aa8	150	{
510f4871	151	struct pch_gpio *chip = gpiochip_get_data(gpio);
04c17aa8	152	u32 pm;
7cb6580c	153	unsigned long flags;
04c17aa8	154
7cb6580c	155	spin_lock_irqsave(&chip->spinlock, flags);
5c85418a AS	156	pm = ioread32(&chip->reg->pm);
	157	pm &= BIT(gpio_pins[chip->ioh]) - 1;
	158	pm &= ~BIT(nr);
04c17aa8	159	iowrite32(pm, &chip->reg->pm);
7cb6580c	160	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	161
	162	return 0;
	163	}
	164
	165	/*
	166	* Save register configuration and disable interrupts.
	167	*/
226e6b86	168	static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
04c17aa8	169	{
38eb18a6 TM	170	chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
38eb18a6 TM	171	chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
04c17aa8 TM	172	chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
04c17aa8 TM	173	chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
e98bed7f TM	174	chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
	175	if (chip->ioh == INTEL_EG20T_PCH)
	176	chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
	177	if (chip->ioh == OKISEMI_ML7223n_IOH)
226e6b86	178	chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
04c17aa8 TM	179	}
	180
	181	/*
	182	* This function restores the register configuration of the GPIO device.
	183	*/
226e6b86	184	static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
04c17aa8	185	{
38eb18a6 TM	186	iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
38eb18a6 TM	187	iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
04c17aa8 TM	188	/* to store contents of PO register */
	189	iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
	190	/* to store contents of PM register */
	191	iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
e98bed7f TM	192	iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
	193	if (chip->ioh == INTEL_EG20T_PCH)
	194	iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
	195	if (chip->ioh == OKISEMI_ML7223n_IOH)
226e6b86	196	iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
04c17aa8 TM	197	}
04c17aa8 TM	198
0c106a23	199	static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned int offset)
38eb18a6	200	{
510f4871	201	struct pch_gpio *chip = gpiochip_get_data(gpio);
37ceab74	202
38eb18a6 TM	203	return chip->irq_base + offset;
	204	}
	205
04c17aa8 TM	206	static void pch_gpio_setup(struct pch_gpio *chip)
	207	{
	208	struct gpio_chip *gpio = &chip->gpio;
	209
	210	gpio->label = dev_name(chip->dev);
58383c78	211	gpio->parent = chip->dev;
04c17aa8 TM	212	gpio->owner = THIS_MODULE;
	213	gpio->direction_input = pch_gpio_direction_input;
	214	gpio->get = pch_gpio_get;
	215	gpio->direction_output = pch_gpio_direction_output;
	216	gpio->set = pch_gpio_set;
04c17aa8	217	gpio->base = -1;
d4260e6d	218	gpio->ngpio = gpio_pins[chip->ioh];
9fb1f39e	219	gpio->can_sleep = false;
38eb18a6 TM	220	gpio->to_irq = pch_gpio_to_irq;
	221	}
	222
	223	static int pch_irq_type(struct irq_data *d, unsigned int type)
	224	{
38eb18a6 TM	225	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
38eb18a6 TM	226	struct pch_gpio *chip = gc->private;
df9541a6 TG	227	u32 im, im_pos, val;
	228	u32 __iomem *im_reg;
	229	unsigned long flags;
	230	int ch, irq = d->irq;
38eb18a6 TM	231
38eb18a6 TM	232	ch = irq - chip->irq_base;
368b8436	233	if (irq < chip->irq_base + 8) {
38eb18a6	234	im_reg = &chip->reg->im0;
368b8436	235	im_pos = ch - 0;
38eb18a6 TM	236	} else {
	237	im_reg = &chip->reg->im1;
	238	im_pos = ch - 8;
	239	}
0511e116	240	dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
38eb18a6	241
38eb18a6 TM	242	switch (type) {
	243	case IRQ_TYPE_EDGE_RISING:
	244	val = PCH_EDGE_RISING;
	245	break;
	246	case IRQ_TYPE_EDGE_FALLING:
	247	val = PCH_EDGE_FALLING;
	248	break;
	249	case IRQ_TYPE_EDGE_BOTH:
	250	val = PCH_EDGE_BOTH;
	251	break;
	252	case IRQ_TYPE_LEVEL_HIGH:
	253	val = PCH_LEVEL_H;
	254	break;
	255	case IRQ_TYPE_LEVEL_LOW:
	256	val = PCH_LEVEL_L;
	257	break;
38eb18a6	258	default:
368b8436	259	return 0;
38eb18a6 TM	260	}
38eb18a6 TM	261
368b8436 AS	262	spin_lock_irqsave(&chip->spinlock, flags);
368b8436 AS	263
38eb18a6 TM	264	/* Set interrupt mode */
	265	im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
	266	iowrite32(im \| (val << (im_pos * 4)), im_reg);
	267
df9541a6	268	/* And the handler */
5376b0b3	269	if (type & IRQ_TYPE_LEVEL_MASK)
2456d869	270	irq_set_handler_locked(d, handle_level_irq);
5376b0b3	271	else if (type & IRQ_TYPE_EDGE_BOTH)
2456d869	272	irq_set_handler_locked(d, handle_edge_irq);
38eb18a6	273
38eb18a6	274	spin_unlock_irqrestore(&chip->spinlock, flags);
38eb18a6 TM	275	return 0;
	276	}
	277
	278	static void pch_irq_unmask(struct irq_data *d)
	279	{
	280	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	281	struct pch_gpio *chip = gc->private;
	282
5c85418a	283	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
38eb18a6 TM	284	}
	285
	286	static void pch_irq_mask(struct irq_data *d)
	287	{
	288	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	289	struct pch_gpio *chip = gc->private;
	290
5c85418a	291	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
38eb18a6 TM	292	}
38eb18a6 TM	293
df9541a6 TG	294	static void pch_irq_ack(struct irq_data *d)
	295	{
	296	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	297	struct pch_gpio *chip = gc->private;
	298
5c85418a	299	iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
df9541a6 TG	300	}
df9541a6 TG	301
38eb18a6 TM	302	static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
	303	{
	304	struct pch_gpio *chip = dev_id;
9be93e1a	305	unsigned long reg_val = ioread32(&chip->reg->istatus);
5a4245de	306	int i;
38eb18a6	307
532e762d	308	dev_vdbg(chip->dev, "irq=%d status=0x%lx\n", irq, reg_val);
5a4245de AS	309
5a4245de AS	310	reg_val &= BIT(gpio_pins[chip->ioh]) - 1;
532e762d	311
5a4245de	312	for_each_set_bit(i, &reg_val, gpio_pins[chip->ioh])
9be93e1a	313	generic_handle_irq(chip->irq_base + i);
5a4245de AS	314
5a4245de AS	315	return IRQ_RETVAL(reg_val);
38eb18a6 TM	316	}
38eb18a6 TM	317
09445a10 BG	318	static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
	319	unsigned int irq_start,
	320	unsigned int num)
38eb18a6 TM	321	{
	322	struct irq_chip_generic *gc;
	323	struct irq_chip_type *ct;
e0fc5a1b	324	int rv;
38eb18a6	325
e0fc5a1b BG	326	gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
e0fc5a1b BG	327	chip->base, handle_simple_irq);
09445a10 BG	328	if (!gc)
	329	return -ENOMEM;
	330
38eb18a6 TM	331	gc->private = chip;
	332	ct = gc->chip_types;
	333
df9541a6	334	ct->chip.irq_ack = pch_irq_ack;
38eb18a6 TM	335	ct->chip.irq_mask = pch_irq_mask;
	336	ct->chip.irq_unmask = pch_irq_unmask;
	337	ct->chip.irq_set_type = pch_irq_type;
	338
e0fc5a1b BG	339	rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
	340	IRQ_GC_INIT_MASK_CACHE,
	341	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
09445a10	342
e0fc5a1b	343	return rv;
04c17aa8 TM	344	}
04c17aa8 TM	345
3836309d	346	static int pch_gpio_probe(struct pci_dev *pdev,
04c17aa8 TM	347	const struct pci_device_id *id)
	348	{
	349	s32 ret;
	350	struct pch_gpio *chip;
38eb18a6	351	int irq_base;
04c17aa8	352
6ad02b29	353	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
04c17aa8 TM	354	if (chip == NULL)
	355	return -ENOMEM;
	356
	357	chip->dev = &pdev->dev;
6ad02b29	358	ret = pcim_enable_device(pdev);
04c17aa8	359	if (ret) {
0511e116	360	dev_err(&pdev->dev, "pci_enable_device FAILED");
6ad02b29	361	return ret;
04c17aa8 TM	362	}
04c17aa8 TM	363
5c85418a	364	ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
04c17aa8 TM	365	if (ret) {
04c17aa8 TM	366	dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
6ad02b29	367	return ret;
04c17aa8 TM	368	}
04c17aa8 TM	369
6ad02b29	370	chip->base = pcim_iomap_table(pdev)[1];
04c17aa8	371
d4260e6d TM	372	if (pdev->device == 0x8803)
	373	chip->ioh = INTEL_EG20T_PCH;
	374	else if (pdev->device == 0x8014)
	375	chip->ioh = OKISEMI_ML7223m_IOH;
	376	else if (pdev->device == 0x8043)
	377	chip->ioh = OKISEMI_ML7223n_IOH;
	378
04c17aa8 TM	379	chip->reg = chip->base;
04c17aa8 TM	380	pci_set_drvdata(pdev, chip);
d166370a	381	spin_lock_init(&chip->spinlock);
04c17aa8	382	pch_gpio_setup(chip);
a3bb44bc	383
6ad02b29	384	ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip);
04c17aa8 TM	385	if (ret) {
04c17aa8 TM	386	dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
6ad02b29	387	return ret;
04c17aa8 TM	388	}
04c17aa8 TM	389
f57f3e60 BG	390	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
f57f3e60 BG	391	gpio_pins[chip->ioh], NUMA_NO_NODE);
38eb18a6 TM	392	if (irq_base < 0) {
	393	dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
	394	chip->irq_base = -1;
6ad02b29	395	return 0;
38eb18a6 TM	396	}
	397	chip->irq_base = irq_base;
	398
df9541a6	399	/* Mask all interrupts, but enable them */
5c85418a AS	400	iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
5c85418a AS	401	iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
df9541a6	402
f57f3e60 BG	403	ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler,
f57f3e60 BG	404	IRQF_SHARED, KBUILD_MODNAME, chip);
6ad02b29	405	if (ret) {
0511e116	406	dev_err(&pdev->dev, "request_irq failed\n");
6ad02b29	407	return ret;
38eb18a6 TM	408	}
38eb18a6 TM	409
6ad02b29	410	return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
04c17aa8 TM	411	}
04c17aa8 TM	412
226e6b86	413	static int __maybe_unused pch_gpio_suspend(struct device *dev)
04c17aa8	414	{
a7db2856	415	struct pch_gpio *chip = dev_get_drvdata(dev);
d568a681	416	unsigned long flags;
04c17aa8	417
d568a681	418	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8	419	pch_gpio_save_reg_conf(chip);
d568a681	420	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8	421
04c17aa8 TM	422	return 0;
	423	}
	424
226e6b86	425	static int __maybe_unused pch_gpio_resume(struct device *dev)
04c17aa8	426	{
a7db2856	427	struct pch_gpio *chip = dev_get_drvdata(dev);
d568a681	428	unsigned long flags;
04c17aa8	429
d568a681	430	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8 TM	431	iowrite32(0x01, &chip->reg->reset);
	432	iowrite32(0x00, &chip->reg->reset);
	433	pch_gpio_restore_reg_conf(chip);
d568a681	434	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	435
	436	return 0;
	437	}
226e6b86 AS	438
226e6b86 AS	439	static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
04c17aa8	440
14f4a883	441	static const struct pci_device_id pch_gpio_pcidev_id[] = {
04c17aa8	442	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
bc786cce	443	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
c3520a1a	444	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
868fea05	445	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
04c17aa8 TM	446	{ 0, }
04c17aa8 TM	447	};
19234cdd	448	MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
04c17aa8 TM	449
	450	static struct pci_driver pch_gpio_driver = {
	451	.name = "pch_gpio",
	452	.id_table = pch_gpio_pcidev_id,
	453	.probe = pch_gpio_probe,
226e6b86 AS	454	.driver = {
	455	.pm = &pch_gpio_pm_ops,
	456	},
04c17aa8 TM	457	};
04c17aa8 TM	458
93baa65f	459	module_pci_driver(pch_gpio_driver);
04c17aa8 TM	460
04c17aa8 TM	461	MODULE_DESCRIPTION("PCH GPIO PCI Driver");
9b8bf5bf	462	MODULE_LICENSE("GPL v2");