[linux-2.6-block.git] / drivers / gpio / gpio-pch.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
 */
#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/slab.h>

#define PCH_EDGE_FALLING	0
#define PCH_EDGE_RISING		BIT(0)
#define PCH_LEVEL_L		BIT(1)
#define PCH_LEVEL_H		(BIT(0) | BIT(1))
#define PCH_EDGE_BOTH		BIT(2)
#define PCH_IM_MASK		(BIT(0) | BIT(1) | BIT(2))

#define PCH_IRQ_BASE		24

struct pch_regs {
	u32	ien;
	u32	istatus;
	u32	idisp;
	u32	iclr;
	u32	imask;
	u32	imaskclr;
	u32	po;
	u32	pi;
	u32	pm;
	u32	im0;
	u32	im1;
	u32	reserved[3];
	u32	gpio_use_sel;
	u32	reset;
};

enum pch_type_t {
	INTEL_EG20T_PCH,
	OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
	OKISEMI_ML7223n_IOH  /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
};

/* Specifies number of GPIO PINS */
static int gpio_pins[] = {
	[INTEL_EG20T_PCH] = 12,
	[OKISEMI_ML7223m_IOH] = 8,
	[OKISEMI_ML7223n_IOH] = 8,
};

/**
 * struct pch_gpio_reg_data - The register store data.
 * @ien_reg:	To store contents of IEN register.
 * @imask_reg:	To store contents of IMASK register.
 * @po_reg:	To store contents of PO register.
 * @pm_reg:	To store contents of PM register.
 * @im0_reg:	To store contents of IM0 register.
 * @im1_reg:	To store contents of IM1 register.
 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
 *		       (Only ML7223 Bus-n)
 */
struct pch_gpio_reg_data {
	u32 ien_reg;
	u32 imask_reg;
	u32 po_reg;
	u32 pm_reg;
	u32 im0_reg;
	u32 im1_reg;
	u32 gpio_use_sel_reg;
};

/**
 * struct pch_gpio - GPIO private data structure.
 * @base:			PCI base address of Memory mapped I/O register.
 * @reg:			Memory mapped PCH GPIO register list.
 * @dev:			Pointer to device structure.
 * @gpio:			Data for GPIO infrastructure.
 * @pch_gpio_reg:		Memory mapped Register data is saved here
 *				when suspend.
 * @lock:			Used for register access protection
 * @irq_base:		Save base of IRQ number for interrupt
 * @ioh:		IOH ID
 * @spinlock:		Used for register access protection
 */
struct pch_gpio {
	void __iomem *base;
	struct pch_regs __iomem *reg;
	struct device *dev;
	struct gpio_chip gpio;
	struct pch_gpio_reg_data pch_gpio_reg;
	int irq_base;
	enum pch_type_t ioh;
	spinlock_t spinlock;
};

static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
{
	u32 reg_val;
	struct pch_gpio *chip =	gpiochip_get_data(gpio);
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	reg_val = ioread32(&chip->reg->po);
	if (val)
		reg_val |= (1 << nr);
	else
		reg_val &= ~(1 << nr);

	iowrite32(reg_val, &chip->reg->po);
	spin_unlock_irqrestore(&chip->spinlock, flags);
}

static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
	struct pch_gpio *chip =	gpiochip_get_data(gpio);

	return (ioread32(&chip->reg->pi) >> nr) & 1;
}

static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
				     int val)
{
	struct pch_gpio *chip =	gpiochip_get_data(gpio);
	u32 pm;
	u32 reg_val;
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);

	reg_val = ioread32(&chip->reg->po);
	if (val)
		reg_val |= (1 << nr);
	else
		reg_val &= ~(1 << nr);
	iowrite32(reg_val, &chip->reg->po);

	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
	pm |= (1 << nr);
	iowrite32(pm, &chip->reg->pm);

	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	struct pch_gpio *chip =	gpiochip_get_data(gpio);
	u32 pm;
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
	pm &= ~(1 << nr);
	iowrite32(pm, &chip->reg->pm);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

/*
 * Save register configuration and disable interrupts.
 */
static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
{
	chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
	chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
	chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
	chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
	chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
	if (chip->ioh == INTEL_EG20T_PCH)
		chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
	if (chip->ioh == OKISEMI_ML7223n_IOH)
		chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
}

/*
 * This function restores the register configuration of the GPIO device.
 */
static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
{
	iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
	iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
	/* to store contents of PO register */
	iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
	/* to store contents of PM register */
	iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
	iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
	if (chip->ioh == INTEL_EG20T_PCH)
		iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
	if (chip->ioh == OKISEMI_ML7223n_IOH)
		iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
}

static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
	struct pch_gpio *chip = gpiochip_get_data(gpio);
	return chip->irq_base + offset;
}

static void pch_gpio_setup(struct pch_gpio *chip)
{
	struct gpio_chip *gpio = &chip->gpio;

	gpio->label = dev_name(chip->dev);
	gpio->parent = chip->dev;
	gpio->owner = THIS_MODULE;
	gpio->direction_input = pch_gpio_direction_input;
	gpio->get = pch_gpio_get;
	gpio->direction_output = pch_gpio_direction_output;
	gpio->set = pch_gpio_set;
	gpio->base = -1;
	gpio->ngpio = gpio_pins[chip->ioh];
	gpio->can_sleep = false;
	gpio->to_irq = pch_gpio_to_irq;
}

static int pch_irq_type(struct irq_data *d, unsigned int type)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;
	u32 im, im_pos, val;
	u32 __iomem *im_reg;
	unsigned long flags;
	int ch, irq = d->irq;

	ch = irq - chip->irq_base;
	if (irq <= chip->irq_base + 7) {
		im_reg = &chip->reg->im0;
		im_pos = ch;
	} else {
		im_reg = &chip->reg->im1;
		im_pos = ch - 8;
	}
	dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);

	spin_lock_irqsave(&chip->spinlock, flags);

	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		val = PCH_EDGE_RISING;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		val = PCH_EDGE_FALLING;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		val = PCH_EDGE_BOTH;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		val = PCH_LEVEL_H;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		val = PCH_LEVEL_L;
		break;
	default:
		goto unlock;
	}

	/* Set interrupt mode */
	im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
	iowrite32(im | (val << (im_pos * 4)), im_reg);

	/* And the handler */
	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		irq_set_handler_locked(d, handle_level_irq);
	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		irq_set_handler_locked(d, handle_edge_irq);

unlock:
	spin_unlock_irqrestore(&chip->spinlock, flags);
	return 0;
}

static void pch_irq_unmask(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
}

static void pch_irq_mask(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
}

static void pch_irq_ack(struct irq_data *d)
{
	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	struct pch_gpio *chip = gc->private;

	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
}

static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
{
	struct pch_gpio *chip = dev_id;
	unsigned long reg_val = ioread32(&chip->reg->istatus);
	int i, ret = IRQ_NONE;

	for_each_set_bit(i, &reg_val, gpio_pins[chip->ioh]) {
		dev_dbg(chip->dev, "[%d]:irq=%d  status=0x%lx\n", i, irq, reg_val);
		generic_handle_irq(chip->irq_base + i);
		ret = IRQ_HANDLED;
	}
	return ret;
}

static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
				       unsigned int irq_start,
				       unsigned int num)
{
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;
	int rv;

	gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
					 chip->base, handle_simple_irq);
	if (!gc)
		return -ENOMEM;

	gc->private = chip;
	ct = gc->chip_types;

	ct->chip.irq_ack = pch_irq_ack;
	ct->chip.irq_mask = pch_irq_mask;
	ct->chip.irq_unmask = pch_irq_unmask;
	ct->chip.irq_set_type = pch_irq_type;

	rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
					 IRQ_GC_INIT_MASK_CACHE,
					 IRQ_NOREQUEST | IRQ_NOPROBE, 0);

	return rv;
}

static int pch_gpio_probe(struct pci_dev *pdev,
				    const struct pci_device_id *id)
{
	s32 ret;
	struct pch_gpio *chip;
	int irq_base;
	u32 msk;

	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
	if (chip == NULL)
		return -ENOMEM;

	chip->dev = &pdev->dev;
	ret = pcim_enable_device(pdev);
	if (ret) {
		dev_err(&pdev->dev, "pci_enable_device FAILED");
		return ret;
	}

	ret = pcim_iomap_regions(pdev, 1 << 1, KBUILD_MODNAME);
	if (ret) {
		dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
		return ret;
	}

	chip->base = pcim_iomap_table(pdev)[1];

	if (pdev->device == 0x8803)
		chip->ioh = INTEL_EG20T_PCH;
	else if (pdev->device == 0x8014)
		chip->ioh = OKISEMI_ML7223m_IOH;
	else if (pdev->device == 0x8043)
		chip->ioh = OKISEMI_ML7223n_IOH;

	chip->reg = chip->base;
	pci_set_drvdata(pdev, chip);
	spin_lock_init(&chip->spinlock);
	pch_gpio_setup(chip);

	ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip);
	if (ret) {
		dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
		return ret;
	}

	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
					gpio_pins[chip->ioh], NUMA_NO_NODE);
	if (irq_base < 0) {
		dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
		chip->irq_base = -1;
		return 0;
	}
	chip->irq_base = irq_base;

	/* Mask all interrupts, but enable them */
	msk = (1 << gpio_pins[chip->ioh]) - 1;
	iowrite32(msk, &chip->reg->imask);
	iowrite32(msk, &chip->reg->ien);

	ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler,
			       IRQF_SHARED, KBUILD_MODNAME, chip);
	if (ret) {
		dev_err(&pdev->dev, "request_irq failed\n");
		return ret;
	}

	return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
}

static int __maybe_unused pch_gpio_suspend(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct pch_gpio *chip = pci_get_drvdata(pdev);
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	pch_gpio_save_reg_conf(chip);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

static int __maybe_unused pch_gpio_resume(struct device *dev)
{
	struct pci_dev *pdev = to_pci_dev(dev);
	struct pch_gpio *chip = pci_get_drvdata(pdev);
	unsigned long flags;

	spin_lock_irqsave(&chip->spinlock, flags);
	iowrite32(0x01, &chip->reg->reset);
	iowrite32(0x00, &chip->reg->reset);
	pch_gpio_restore_reg_conf(chip);
	spin_unlock_irqrestore(&chip->spinlock, flags);

	return 0;
}

static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);

static const struct pci_device_id pch_gpio_pcidev_id[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);

static struct pci_driver pch_gpio_driver = {
	.name = "pch_gpio",
	.id_table = pch_gpio_pcidev_id,
	.probe = pch_gpio_probe,
	.driver = {
		.pm = &pch_gpio_pm_ops,
	},
};

module_pci_driver(pch_gpio_driver);

MODULE_DESCRIPTION("PCH GPIO PCI Driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9b8bf5bf	1	// SPDX-License-Identifier: GPL-2.0
04c17aa8	2	/*
f4574beb	3	* Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
04c17aa8	4	*/
5db1f873	5	#include <linux/gpio/driver.h>
38eb18a6 TM	6	#include <linux/interrupt.h>
38eb18a6 TM	7	#include <linux/irq.h>
3e1884f8 AS	8	#include <linux/kernel.h>
	9	#include <linux/module.h>
	10	#include <linux/pci.h>
349b6c53	11	#include <linux/slab.h>
38eb18a6 TM	12
	13	#define PCH_EDGE_FALLING 0
	14	#define PCH_EDGE_RISING BIT(0)
	15	#define PCH_LEVEL_L BIT(1)
	16	#define PCH_LEVEL_H (BIT(0) \| BIT(1))
	17	#define PCH_EDGE_BOTH BIT(2)
	18	#define PCH_IM_MASK (BIT(0) \| BIT(1) \| BIT(2))
	19
	20	#define PCH_IRQ_BASE 24
04c17aa8	21
04c17aa8 TM	22	struct pch_regs {
	23	u32 ien;
	24	u32 istatus;
	25	u32 idisp;
	26	u32 iclr;
	27	u32 imask;
	28	u32 imaskclr;
	29	u32 po;
	30	u32 pi;
	31	u32 pm;
	32	u32 im0;
	33	u32 im1;
e98bed7f TM	34	u32 reserved[3];
e98bed7f TM	35	u32 gpio_use_sel;
04c17aa8 TM	36	u32 reset;
	37	};
	38
d4260e6d TM	39	enum pch_type_t {
d4260e6d TM	40	INTEL_EG20T_PCH,
f4574beb TM	41	OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
f4574beb TM	42	OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
d4260e6d TM	43	};
	44
	45	/* Specifies number of GPIO PINS */
	46	static int gpio_pins[] = {
	47	[INTEL_EG20T_PCH] = 12,
	48	[OKISEMI_ML7223m_IOH] = 8,
	49	[OKISEMI_ML7223n_IOH] = 8,
	50	};
	51
04c17aa8 TM	52	/**
04c17aa8 TM	53	* struct pch_gpio_reg_data - The register store data.
38eb18a6 TM	54	* @ien_reg: To store contents of IEN register.
38eb18a6 TM	55	* @imask_reg: To store contents of IMASK register.
04c17aa8 TM	56	* @po_reg: To store contents of PO register.
04c17aa8 TM	57	* @pm_reg: To store contents of PM register.
e98bed7f TM	58	* @im0_reg: To store contents of IM0 register.
	59	* @im1_reg: To store contents of IM1 register.
	60	* @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
	61	* (Only ML7223 Bus-n)
04c17aa8 TM	62	*/
04c17aa8 TM	63	struct pch_gpio_reg_data {
38eb18a6 TM	64	u32 ien_reg;
38eb18a6 TM	65	u32 imask_reg;
04c17aa8 TM	66	u32 po_reg;
04c17aa8 TM	67	u32 pm_reg;
e98bed7f TM	68	u32 im0_reg;
	69	u32 im1_reg;
	70	u32 gpio_use_sel_reg;
04c17aa8 TM	71	};
	72
	73	/**
	74	* struct pch_gpio - GPIO private data structure.
	75	* @base: PCI base address of Memory mapped I/O register.
	76	* @reg: Memory mapped PCH GPIO register list.
	77	* @dev: Pointer to device structure.
	78	* @gpio: Data for GPIO infrastructure.
	79	* @pch_gpio_reg: Memory mapped Register data is saved here
	80	* when suspend.
38eb18a6 TM	81	* @lock: Used for register access protection
38eb18a6 TM	82	* @irq_base: Save base of IRQ number for interrupt
d4260e6d	83	* @ioh: IOH ID
7cb6580c	84	* @spinlock: Used for register access protection
04c17aa8 TM	85	*/
	86	struct pch_gpio {
	87	void __iomem *base;
	88	struct pch_regs __iomem *reg;
	89	struct device *dev;
	90	struct gpio_chip gpio;
	91	struct pch_gpio_reg_data pch_gpio_reg;
38eb18a6	92	int irq_base;
d4260e6d	93	enum pch_type_t ioh;
d568a681	94	spinlock_t spinlock;
04c17aa8 TM	95	};
	96
	97	static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
	98	{
	99	u32 reg_val;
510f4871	100	struct pch_gpio *chip = gpiochip_get_data(gpio);
7cb6580c	101	unsigned long flags;
04c17aa8	102
7cb6580c	103	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8 TM	104	reg_val = ioread32(&chip->reg->po);
	105	if (val)
	106	reg_val \|= (1 << nr);
	107	else
	108	reg_val &= ~(1 << nr);
	109
	110	iowrite32(reg_val, &chip->reg->po);
7cb6580c	111	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	112	}
	113
	114	static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
	115	{
510f4871	116	struct pch_gpio *chip = gpiochip_get_data(gpio);
04c17aa8	117
166814d8	118	return (ioread32(&chip->reg->pi) >> nr) & 1;
04c17aa8 TM	119	}
	120
	121	static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
	122	int val)
	123	{
510f4871	124	struct pch_gpio *chip = gpiochip_get_data(gpio);
04c17aa8 TM	125	u32 pm;
04c17aa8 TM	126	u32 reg_val;
7cb6580c	127	unsigned long flags;
04c17aa8	128
7cb6580c	129	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8 TM	130
	131	reg_val = ioread32(&chip->reg->po);
	132	if (val)
	133	reg_val \|= (1 << nr);
	134	else
	135	reg_val &= ~(1 << nr);
88aab934	136	iowrite32(reg_val, &chip->reg->po);
2ddf6cd6 DK	137
	138	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
	139	pm \|= (1 << nr);
	140	iowrite32(pm, &chip->reg->pm);
	141
7cb6580c	142	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	143
	144	return 0;
	145	}
	146
	147	static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	148	{
510f4871	149	struct pch_gpio *chip = gpiochip_get_data(gpio);
04c17aa8	150	u32 pm;
7cb6580c	151	unsigned long flags;
04c17aa8	152
7cb6580c	153	spin_lock_irqsave(&chip->spinlock, flags);
d4260e6d	154	pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
04c17aa8 TM	155	pm &= ~(1 << nr);
04c17aa8 TM	156	iowrite32(pm, &chip->reg->pm);
7cb6580c	157	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	158
	159	return 0;
	160	}
	161
	162	/*
	163	* Save register configuration and disable interrupts.
	164	*/
226e6b86	165	static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
04c17aa8	166	{
38eb18a6 TM	167	chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
38eb18a6 TM	168	chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
04c17aa8 TM	169	chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
04c17aa8 TM	170	chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
e98bed7f TM	171	chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
	172	if (chip->ioh == INTEL_EG20T_PCH)
	173	chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
	174	if (chip->ioh == OKISEMI_ML7223n_IOH)
226e6b86	175	chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
04c17aa8 TM	176	}
	177
	178	/*
	179	* This function restores the register configuration of the GPIO device.
	180	*/
226e6b86	181	static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
04c17aa8	182	{
38eb18a6 TM	183	iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
38eb18a6 TM	184	iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
04c17aa8 TM	185	/* to store contents of PO register */
	186	iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
	187	/* to store contents of PM register */
	188	iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
e98bed7f TM	189	iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
	190	if (chip->ioh == INTEL_EG20T_PCH)
	191	iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
	192	if (chip->ioh == OKISEMI_ML7223n_IOH)
226e6b86	193	iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
04c17aa8 TM	194	}
04c17aa8 TM	195
38eb18a6 TM	196	static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
38eb18a6 TM	197	{
510f4871	198	struct pch_gpio *chip = gpiochip_get_data(gpio);
38eb18a6 TM	199	return chip->irq_base + offset;
	200	}
	201
04c17aa8 TM	202	static void pch_gpio_setup(struct pch_gpio *chip)
	203	{
	204	struct gpio_chip *gpio = &chip->gpio;
	205
	206	gpio->label = dev_name(chip->dev);
58383c78	207	gpio->parent = chip->dev;
04c17aa8 TM	208	gpio->owner = THIS_MODULE;
	209	gpio->direction_input = pch_gpio_direction_input;
	210	gpio->get = pch_gpio_get;
	211	gpio->direction_output = pch_gpio_direction_output;
	212	gpio->set = pch_gpio_set;
04c17aa8	213	gpio->base = -1;
d4260e6d	214	gpio->ngpio = gpio_pins[chip->ioh];
9fb1f39e	215	gpio->can_sleep = false;
38eb18a6 TM	216	gpio->to_irq = pch_gpio_to_irq;
	217	}
	218
	219	static int pch_irq_type(struct irq_data *d, unsigned int type)
	220	{
38eb18a6 TM	221	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
38eb18a6 TM	222	struct pch_gpio *chip = gc->private;
df9541a6 TG	223	u32 im, im_pos, val;
	224	u32 __iomem *im_reg;
	225	unsigned long flags;
	226	int ch, irq = d->irq;
38eb18a6 TM	227
	228	ch = irq - chip->irq_base;
	229	if (irq <= chip->irq_base + 7) {
	230	im_reg = &chip->reg->im0;
	231	im_pos = ch;
	232	} else {
	233	im_reg = &chip->reg->im1;
	234	im_pos = ch - 8;
	235	}
0511e116	236	dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
38eb18a6 TM	237
	238	spin_lock_irqsave(&chip->spinlock, flags);
	239
	240	switch (type) {
	241	case IRQ_TYPE_EDGE_RISING:
	242	val = PCH_EDGE_RISING;
	243	break;
	244	case IRQ_TYPE_EDGE_FALLING:
	245	val = PCH_EDGE_FALLING;
	246	break;
	247	case IRQ_TYPE_EDGE_BOTH:
	248	val = PCH_EDGE_BOTH;
	249	break;
	250	case IRQ_TYPE_LEVEL_HIGH:
	251	val = PCH_LEVEL_H;
	252	break;
	253	case IRQ_TYPE_LEVEL_LOW:
	254	val = PCH_LEVEL_L;
	255	break;
38eb18a6	256	default:
df9541a6	257	goto unlock;
38eb18a6 TM	258	}
	259
	260	/* Set interrupt mode */
	261	im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
	262	iowrite32(im \| (val << (im_pos * 4)), im_reg);
	263
df9541a6 TG	264	/* And the handler */
df9541a6 TG	265	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
2456d869	266	irq_set_handler_locked(d, handle_level_irq);
df9541a6	267	else if (type & (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
2456d869	268	irq_set_handler_locked(d, handle_edge_irq);
38eb18a6	269
df9541a6	270	unlock:
38eb18a6	271	spin_unlock_irqrestore(&chip->spinlock, flags);
38eb18a6 TM	272	return 0;
	273	}
	274
	275	static void pch_irq_unmask(struct irq_data *d)
	276	{
	277	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	278	struct pch_gpio *chip = gc->private;
	279
	280	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
	281	}
	282
	283	static void pch_irq_mask(struct irq_data *d)
	284	{
	285	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	286	struct pch_gpio *chip = gc->private;
	287
	288	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
	289	}
	290
df9541a6 TG	291	static void pch_irq_ack(struct irq_data *d)
	292	{
	293	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
	294	struct pch_gpio *chip = gc->private;
	295
	296	iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
	297	}
	298
38eb18a6 TM	299	static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
	300	{
	301	struct pch_gpio *chip = dev_id;
9be93e1a	302	unsigned long reg_val = ioread32(&chip->reg->istatus);
df9541a6	303	int i, ret = IRQ_NONE;
38eb18a6	304
9be93e1a	305	for_each_set_bit(i, &reg_val, gpio_pins[chip->ioh]) {
0511e116	306	dev_dbg(chip->dev, "[%d]:irq=%d status=0x%lx\n", i, irq, reg_val);
9be93e1a AS	307	generic_handle_irq(chip->irq_base + i);
9be93e1a AS	308	ret = IRQ_HANDLED;
38eb18a6 TM	309	}
	310	return ret;
	311	}
	312
09445a10 BG	313	static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
	314	unsigned int irq_start,
	315	unsigned int num)
38eb18a6 TM	316	{
	317	struct irq_chip_generic *gc;
	318	struct irq_chip_type *ct;
e0fc5a1b	319	int rv;
38eb18a6	320
e0fc5a1b BG	321	gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
e0fc5a1b BG	322	chip->base, handle_simple_irq);
09445a10 BG	323	if (!gc)
	324	return -ENOMEM;
	325
38eb18a6 TM	326	gc->private = chip;
	327	ct = gc->chip_types;
	328
df9541a6	329	ct->chip.irq_ack = pch_irq_ack;
38eb18a6 TM	330	ct->chip.irq_mask = pch_irq_mask;
	331	ct->chip.irq_unmask = pch_irq_unmask;
	332	ct->chip.irq_set_type = pch_irq_type;
	333
e0fc5a1b BG	334	rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
	335	IRQ_GC_INIT_MASK_CACHE,
	336	IRQ_NOREQUEST \| IRQ_NOPROBE, 0);
09445a10	337
e0fc5a1b	338	return rv;
04c17aa8 TM	339	}
04c17aa8 TM	340
3836309d	341	static int pch_gpio_probe(struct pci_dev *pdev,
04c17aa8 TM	342	const struct pci_device_id *id)
	343	{
	344	s32 ret;
	345	struct pch_gpio *chip;
38eb18a6	346	int irq_base;
df9541a6	347	u32 msk;
04c17aa8	348
6ad02b29	349	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
04c17aa8 TM	350	if (chip == NULL)
	351	return -ENOMEM;
	352
	353	chip->dev = &pdev->dev;
6ad02b29	354	ret = pcim_enable_device(pdev);
04c17aa8	355	if (ret) {
0511e116	356	dev_err(&pdev->dev, "pci_enable_device FAILED");
6ad02b29	357	return ret;
04c17aa8 TM	358	}
04c17aa8 TM	359
6ad02b29	360	ret = pcim_iomap_regions(pdev, 1 << 1, KBUILD_MODNAME);
04c17aa8 TM	361	if (ret) {
04c17aa8 TM	362	dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
6ad02b29	363	return ret;
04c17aa8 TM	364	}
04c17aa8 TM	365
6ad02b29	366	chip->base = pcim_iomap_table(pdev)[1];
04c17aa8	367
d4260e6d TM	368	if (pdev->device == 0x8803)
	369	chip->ioh = INTEL_EG20T_PCH;
	370	else if (pdev->device == 0x8014)
	371	chip->ioh = OKISEMI_ML7223m_IOH;
	372	else if (pdev->device == 0x8043)
	373	chip->ioh = OKISEMI_ML7223n_IOH;
	374
04c17aa8 TM	375	chip->reg = chip->base;
04c17aa8 TM	376	pci_set_drvdata(pdev, chip);
d166370a	377	spin_lock_init(&chip->spinlock);
04c17aa8	378	pch_gpio_setup(chip);
a3bb44bc	379
6ad02b29	380	ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip);
04c17aa8 TM	381	if (ret) {
04c17aa8 TM	382	dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
6ad02b29	383	return ret;
04c17aa8 TM	384	}
04c17aa8 TM	385
f57f3e60 BG	386	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
f57f3e60 BG	387	gpio_pins[chip->ioh], NUMA_NO_NODE);
38eb18a6 TM	388	if (irq_base < 0) {
	389	dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
	390	chip->irq_base = -1;
6ad02b29	391	return 0;
38eb18a6 TM	392	}
	393	chip->irq_base = irq_base;
	394
df9541a6 TG	395	/* Mask all interrupts, but enable them */
	396	msk = (1 << gpio_pins[chip->ioh]) - 1;
	397	iowrite32(msk, &chip->reg->imask);
	398	iowrite32(msk, &chip->reg->ien);
	399
f57f3e60 BG	400	ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler,
f57f3e60 BG	401	IRQF_SHARED, KBUILD_MODNAME, chip);
6ad02b29	402	if (ret) {
0511e116	403	dev_err(&pdev->dev, "request_irq failed\n");
6ad02b29	404	return ret;
38eb18a6 TM	405	}
38eb18a6 TM	406
6ad02b29	407	return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
04c17aa8 TM	408	}
04c17aa8 TM	409
226e6b86	410	static int __maybe_unused pch_gpio_suspend(struct device *dev)
04c17aa8	411	{
226e6b86	412	struct pci_dev *pdev = to_pci_dev(dev);
04c17aa8	413	struct pch_gpio *chip = pci_get_drvdata(pdev);
d568a681	414	unsigned long flags;
04c17aa8	415
d568a681	416	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8	417	pch_gpio_save_reg_conf(chip);
d568a681	418	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8	419
04c17aa8 TM	420	return 0;
	421	}
	422
226e6b86	423	static int __maybe_unused pch_gpio_resume(struct device *dev)
04c17aa8	424	{
226e6b86	425	struct pci_dev *pdev = to_pci_dev(dev);
04c17aa8	426	struct pch_gpio *chip = pci_get_drvdata(pdev);
d568a681	427	unsigned long flags;
04c17aa8	428
d568a681	429	spin_lock_irqsave(&chip->spinlock, flags);
04c17aa8 TM	430	iowrite32(0x01, &chip->reg->reset);
	431	iowrite32(0x00, &chip->reg->reset);
	432	pch_gpio_restore_reg_conf(chip);
d568a681	433	spin_unlock_irqrestore(&chip->spinlock, flags);
04c17aa8 TM	434
	435	return 0;
	436	}
226e6b86 AS	437
226e6b86 AS	438	static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
04c17aa8	439
14f4a883	440	static const struct pci_device_id pch_gpio_pcidev_id[] = {
04c17aa8	441	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
bc786cce	442	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
c3520a1a	443	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
868fea05	444	{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
04c17aa8 TM	445	{ 0, }
04c17aa8 TM	446	};
19234cdd	447	MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
04c17aa8 TM	448
	449	static struct pci_driver pch_gpio_driver = {
	450	.name = "pch_gpio",
	451	.id_table = pch_gpio_pcidev_id,
	452	.probe = pch_gpio_probe,
226e6b86 AS	453	.driver = {
	454	.pm = &pch_gpio_pm_ops,
	455	},
04c17aa8 TM	456	};
04c17aa8 TM	457
93baa65f	458	module_pci_driver(pch_gpio_driver);
04c17aa8 TM	459
04c17aa8 TM	460	MODULE_DESCRIPTION("PCH GPIO PCI Driver");
9b8bf5bf	461	MODULE_LICENSE("GPL v2");