Commit | Line | Data |
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74ba9207 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
15fae37d | 2 | /* |
c103de24 | 3 | * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders |
15fae37d DB |
4 | * |
5 | * Copyright (C) 2007 David Brownell | |
15fae37d DB |
6 | */ |
7 | ||
12087fab | 8 | #include <linux/gpio/driver.h> |
15fae37d | 9 | #include <linux/i2c.h> |
6e20a0a4 KM |
10 | #include <linux/interrupt.h> |
11 | #include <linux/irq.h> | |
12 | #include <linux/irqdomain.h> | |
c990d6cb | 13 | #include <linux/kernel.h> |
e2d18121 | 14 | #include <linux/mod_devicetable.h> |
bb207ef1 | 15 | #include <linux/module.h> |
e2d18121 | 16 | #include <linux/property.h> |
c990d6cb | 17 | #include <linux/slab.h> |
6e20a0a4 | 18 | #include <linux/spinlock.h> |
15fae37d | 19 | |
3760f736 JD |
20 | static const struct i2c_device_id pcf857x_id[] = { |
21 | { "pcf8574", 8 }, | |
4ba2ccb8 | 22 | { "pcf8574a", 8 }, |
3760f736 JD |
23 | { "pca8574", 8 }, |
24 | { "pca9670", 8 }, | |
25 | { "pca9672", 8 }, | |
26 | { "pca9674", 8 }, | |
27 | { "pcf8575", 16 }, | |
28 | { "pca8575", 16 }, | |
29 | { "pca9671", 16 }, | |
30 | { "pca9673", 16 }, | |
31 | { "pca9675", 16 }, | |
1673ad52 DB |
32 | { "max7328", 8 }, |
33 | { "max7329", 8 }, | |
3760f736 JD |
34 | { } |
35 | }; | |
36 | MODULE_DEVICE_TABLE(i2c, pcf857x_id); | |
37 | ||
63f57cd4 LP |
38 | static const struct of_device_id pcf857x_of_table[] = { |
39 | { .compatible = "nxp,pcf8574" }, | |
40 | { .compatible = "nxp,pcf8574a" }, | |
41 | { .compatible = "nxp,pca8574" }, | |
42 | { .compatible = "nxp,pca9670" }, | |
43 | { .compatible = "nxp,pca9672" }, | |
44 | { .compatible = "nxp,pca9674" }, | |
45 | { .compatible = "nxp,pcf8575" }, | |
46 | { .compatible = "nxp,pca8575" }, | |
47 | { .compatible = "nxp,pca9671" }, | |
48 | { .compatible = "nxp,pca9673" }, | |
49 | { .compatible = "nxp,pca9675" }, | |
50 | { .compatible = "maxim,max7328" }, | |
51 | { .compatible = "maxim,max7329" }, | |
63f57cd4 LP |
52 | { } |
53 | }; | |
54 | MODULE_DEVICE_TABLE(of, pcf857x_of_table); | |
63f57cd4 | 55 | |
15fae37d DB |
56 | /* |
57 | * The pcf857x, pca857x, and pca967x chips only expose one read and one | |
58 | * write register. Writing a "one" bit (to match the reset state) lets | |
59 | * that pin be used as an input; it's not an open-drain model, but acts | |
60 | * a bit like one. This is described as "quasi-bidirectional"; read the | |
61 | * chip documentation for details. | |
62 | * | |
63 | * Many other I2C GPIO expander chips (like the pca953x models) have | |
64 | * more complex register models and more conventional circuitry using | |
65 | * push/pull drivers. They often use the same 0x20..0x27 addresses as | |
66 | * pcf857x parts, making the "legacy" I2C driver model problematic. | |
67 | */ | |
68 | struct pcf857x { | |
69 | struct gpio_chip chip; | |
70 | struct i2c_client *client; | |
1673ad52 | 71 | struct mutex lock; /* protect 'out' */ |
4628cb0d RR |
72 | unsigned int out; /* software latch */ |
73 | unsigned int status; /* current status */ | |
74 | unsigned int irq_enabled; /* enabled irqs */ | |
0c65ddd4 | 75 | |
4628cb0d | 76 | int (*write)(struct i2c_client *client, unsigned int data); |
0c65ddd4 | 77 | int (*read)(struct i2c_client *client); |
15fae37d DB |
78 | }; |
79 | ||
80 | /*-------------------------------------------------------------------------*/ | |
81 | ||
82 | /* Talk to 8-bit I/O expander */ | |
83 | ||
4628cb0d | 84 | static int i2c_write_le8(struct i2c_client *client, unsigned int data) |
15fae37d | 85 | { |
0c65ddd4 | 86 | return i2c_smbus_write_byte(client, data); |
15fae37d DB |
87 | } |
88 | ||
0c65ddd4 | 89 | static int i2c_read_le8(struct i2c_client *client) |
15fae37d | 90 | { |
51435300 | 91 | return i2c_smbus_read_byte(client); |
15fae37d DB |
92 | } |
93 | ||
15fae37d DB |
94 | /* Talk to 16-bit I/O expander */ |
95 | ||
4628cb0d | 96 | static int i2c_write_le16(struct i2c_client *client, unsigned int word) |
15fae37d DB |
97 | { |
98 | u8 buf[2] = { word & 0xff, word >> 8, }; | |
99 | int status; | |
100 | ||
101 | status = i2c_master_send(client, buf, 2); | |
102 | return (status < 0) ? status : 0; | |
103 | } | |
104 | ||
105 | static int i2c_read_le16(struct i2c_client *client) | |
106 | { | |
107 | u8 buf[2]; | |
108 | int status; | |
109 | ||
110 | status = i2c_master_recv(client, buf, 2); | |
111 | if (status < 0) | |
112 | return status; | |
113 | return (buf[1] << 8) | buf[0]; | |
114 | } | |
115 | ||
0c65ddd4 KM |
116 | /*-------------------------------------------------------------------------*/ |
117 | ||
4628cb0d | 118 | static int pcf857x_input(struct gpio_chip *chip, unsigned int offset) |
15fae37d | 119 | { |
17a5f49b RR |
120 | struct pcf857x *gpio = gpiochip_get_data(chip); |
121 | int status; | |
15fae37d | 122 | |
1673ad52 | 123 | mutex_lock(&gpio->lock); |
15fae37d | 124 | gpio->out |= (1 << offset); |
0c65ddd4 | 125 | status = gpio->write(gpio->client, gpio->out); |
1673ad52 DB |
126 | mutex_unlock(&gpio->lock); |
127 | ||
128 | return status; | |
15fae37d DB |
129 | } |
130 | ||
4628cb0d | 131 | static int pcf857x_get(struct gpio_chip *chip, unsigned int offset) |
15fae37d | 132 | { |
17a5f49b RR |
133 | struct pcf857x *gpio = gpiochip_get_data(chip); |
134 | int value; | |
15fae37d | 135 | |
0c65ddd4 | 136 | value = gpio->read(gpio->client); |
40f80580 | 137 | return (value < 0) ? value : !!(value & (1 << offset)); |
15fae37d DB |
138 | } |
139 | ||
64d2f459 RR |
140 | static int pcf857x_get_multiple(struct gpio_chip *chip, unsigned long *mask, |
141 | unsigned long *bits) | |
142 | { | |
143 | struct pcf857x *gpio = gpiochip_get_data(chip); | |
144 | int value = gpio->read(gpio->client); | |
145 | ||
146 | if (value < 0) | |
147 | return value; | |
148 | ||
149 | *bits &= ~*mask; | |
150 | *bits |= value & *mask; | |
151 | ||
152 | return 0; | |
153 | } | |
154 | ||
4628cb0d | 155 | static int pcf857x_output(struct gpio_chip *chip, unsigned int offset, int value) |
15fae37d | 156 | { |
17a5f49b RR |
157 | struct pcf857x *gpio = gpiochip_get_data(chip); |
158 | unsigned int bit = 1 << offset; | |
159 | int status; | |
15fae37d | 160 | |
1673ad52 | 161 | mutex_lock(&gpio->lock); |
15fae37d DB |
162 | if (value) |
163 | gpio->out |= bit; | |
164 | else | |
165 | gpio->out &= ~bit; | |
0c65ddd4 | 166 | status = gpio->write(gpio->client, gpio->out); |
1673ad52 DB |
167 | mutex_unlock(&gpio->lock); |
168 | ||
169 | return status; | |
15fae37d DB |
170 | } |
171 | ||
4628cb0d | 172 | static void pcf857x_set(struct gpio_chip *chip, unsigned int offset, int value) |
15fae37d | 173 | { |
0c65ddd4 | 174 | pcf857x_output(chip, offset, value); |
15fae37d DB |
175 | } |
176 | ||
64d2f459 RR |
177 | static void pcf857x_set_multiple(struct gpio_chip *chip, unsigned long *mask, |
178 | unsigned long *bits) | |
179 | { | |
180 | struct pcf857x *gpio = gpiochip_get_data(chip); | |
181 | ||
182 | mutex_lock(&gpio->lock); | |
183 | gpio->out &= ~*mask; | |
184 | gpio->out |= *bits & *mask; | |
185 | gpio->write(gpio->client, gpio->out); | |
186 | mutex_unlock(&gpio->lock); | |
187 | } | |
188 | ||
15fae37d DB |
189 | /*-------------------------------------------------------------------------*/ |
190 | ||
5c21d008 GC |
191 | static irqreturn_t pcf857x_irq(int irq, void *data) |
192 | { | |
17a5f49b | 193 | struct pcf857x *gpio = data; |
049aaf9f | 194 | unsigned long change, i, status; |
5c21d008 GC |
195 | |
196 | status = gpio->read(gpio->client); | |
197 | ||
21fd3cd1 GC |
198 | /* |
199 | * call the interrupt handler iff gpio is used as | |
200 | * interrupt source, just to avoid bad irqs | |
201 | */ | |
049aaf9f | 202 | mutex_lock(&gpio->lock); |
84f28998 | 203 | change = (gpio->status ^ status) & gpio->irq_enabled; |
5c21d008 | 204 | gpio->status = status; |
049aaf9f | 205 | mutex_unlock(&gpio->lock); |
5c21d008 | 206 | |
049aaf9f | 207 | for_each_set_bit(i, &change, gpio->chip.ngpio) |
f0fbe7bc | 208 | handle_nested_irq(irq_find_mapping(gpio->chip.irq.domain, i)); |
5c21d008 GC |
209 | |
210 | return IRQ_HANDLED; | |
211 | } | |
212 | ||
b80eef95 GU |
213 | /* |
214 | * NOP functions | |
215 | */ | |
216 | static void noop(struct irq_data *data) { } | |
217 | ||
b80eef95 GU |
218 | static int pcf857x_irq_set_wake(struct irq_data *data, unsigned int on) |
219 | { | |
220 | struct pcf857x *gpio = irq_data_get_irq_chip_data(data); | |
84f28998 | 221 | |
7f2f787c | 222 | return irq_set_irq_wake(gpio->client->irq, on); |
b80eef95 GU |
223 | } |
224 | ||
84f28998 GS |
225 | static void pcf857x_irq_enable(struct irq_data *data) |
226 | { | |
227 | struct pcf857x *gpio = irq_data_get_irq_chip_data(data); | |
61550be7 | 228 | irq_hw_number_t hwirq = irqd_to_hwirq(data); |
84f28998 | 229 | |
61550be7 GU |
230 | gpiochip_enable_irq(&gpio->chip, hwirq); |
231 | gpio->irq_enabled |= (1 << hwirq); | |
84f28998 GS |
232 | } |
233 | ||
234 | static void pcf857x_irq_disable(struct irq_data *data) | |
235 | { | |
236 | struct pcf857x *gpio = irq_data_get_irq_chip_data(data); | |
61550be7 | 237 | irq_hw_number_t hwirq = irqd_to_hwirq(data); |
84f28998 | 238 | |
61550be7 GU |
239 | gpio->irq_enabled &= ~(1 << hwirq); |
240 | gpiochip_disable_irq(&gpio->chip, hwirq); | |
84f28998 GS |
241 | } |
242 | ||
243 | static void pcf857x_irq_bus_lock(struct irq_data *data) | |
244 | { | |
245 | struct pcf857x *gpio = irq_data_get_irq_chip_data(data); | |
246 | ||
247 | mutex_lock(&gpio->lock); | |
248 | } | |
249 | ||
250 | static void pcf857x_irq_bus_sync_unlock(struct irq_data *data) | |
251 | { | |
252 | struct pcf857x *gpio = irq_data_get_irq_chip_data(data); | |
253 | ||
254 | mutex_unlock(&gpio->lock); | |
255 | } | |
256 | ||
61550be7 GU |
257 | static const struct irq_chip pcf857x_irq_chip = { |
258 | .name = "pcf857x", | |
259 | .irq_enable = pcf857x_irq_enable, | |
260 | .irq_disable = pcf857x_irq_disable, | |
261 | .irq_ack = noop, | |
262 | .irq_mask = noop, | |
263 | .irq_unmask = noop, | |
264 | .irq_set_wake = pcf857x_irq_set_wake, | |
265 | .irq_bus_lock = pcf857x_irq_bus_lock, | |
266 | .irq_bus_sync_unlock = pcf857x_irq_bus_sync_unlock, | |
267 | .flags = IRQCHIP_IMMUTABLE, | |
268 | GPIOCHIP_IRQ_RESOURCE_HELPERS, | |
269 | }; | |
270 | ||
6e20a0a4 KM |
271 | /*-------------------------------------------------------------------------*/ |
272 | ||
7963ba02 | 273 | static int pcf857x_probe(struct i2c_client *client) |
15fae37d | 274 | { |
7963ba02 | 275 | const struct i2c_device_id *id = i2c_client_get_device_id(client); |
17a5f49b RR |
276 | struct pcf857x *gpio; |
277 | unsigned int n_latch = 0; | |
278 | int status; | |
15fae37d | 279 | |
e2d18121 | 280 | device_property_read_u32(&client->dev, "lines-initial-states", &n_latch); |
15fae37d DB |
281 | |
282 | /* Allocate, initialize, and register this gpio_chip. */ | |
f39f54af | 283 | gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL); |
15fae37d DB |
284 | if (!gpio) |
285 | return -ENOMEM; | |
286 | ||
1673ad52 DB |
287 | mutex_init(&gpio->lock); |
288 | ||
91a0192e | 289 | gpio->chip.base = -1; |
9fb1f39e | 290 | gpio->chip.can_sleep = true; |
0d1bb2b3 | 291 | gpio->chip.parent = &client->dev; |
0c65ddd4 KM |
292 | gpio->chip.owner = THIS_MODULE; |
293 | gpio->chip.get = pcf857x_get; | |
64d2f459 | 294 | gpio->chip.get_multiple = pcf857x_get_multiple; |
0c65ddd4 | 295 | gpio->chip.set = pcf857x_set; |
64d2f459 | 296 | gpio->chip.set_multiple = pcf857x_set_multiple; |
0c65ddd4 KM |
297 | gpio->chip.direction_input = pcf857x_input; |
298 | gpio->chip.direction_output = pcf857x_output; | |
299 | gpio->chip.ngpio = id->driver_data; | |
15fae37d DB |
300 | |
301 | /* NOTE: the OnSemi jlc1562b is also largely compatible with | |
302 | * these parts, notably for output. It has a low-resolution | |
303 | * DAC instead of pin change IRQs; and its inputs can be the | |
304 | * result of comparators. | |
305 | */ | |
306 | ||
307 | /* 8574 addresses are 0x20..0x27; 8574a uses 0x38..0x3f; | |
308 | * 9670, 9672, 9764, and 9764a use quite a variety. | |
309 | * | |
310 | * NOTE: we don't distinguish here between *4 and *4a parts. | |
311 | */ | |
3760f736 | 312 | if (gpio->chip.ngpio == 8) { |
0c65ddd4 KM |
313 | gpio->write = i2c_write_le8; |
314 | gpio->read = i2c_read_le8; | |
15fae37d DB |
315 | |
316 | if (!i2c_check_functionality(client->adapter, | |
317 | I2C_FUNC_SMBUS_BYTE)) | |
318 | status = -EIO; | |
319 | ||
320 | /* fail if there's no chip present */ | |
321 | else | |
322 | status = i2c_smbus_read_byte(client); | |
323 | ||
324 | /* '75/'75c addresses are 0x20..0x27, just like the '74; | |
325 | * the '75c doesn't have a current source pulling high. | |
326 | * 9671, 9673, and 9765 use quite a variety of addresses. | |
327 | * | |
328 | * NOTE: we don't distinguish here between '75 and '75c parts. | |
329 | */ | |
3760f736 | 330 | } else if (gpio->chip.ngpio == 16) { |
0c65ddd4 KM |
331 | gpio->write = i2c_write_le16; |
332 | gpio->read = i2c_read_le16; | |
15fae37d DB |
333 | |
334 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) | |
335 | status = -EIO; | |
336 | ||
337 | /* fail if there's no chip present */ | |
338 | else | |
339 | status = i2c_read_le16(client); | |
340 | ||
a342d215 BD |
341 | } else { |
342 | dev_dbg(&client->dev, "unsupported number of gpios\n"); | |
343 | status = -EINVAL; | |
344 | } | |
15fae37d DB |
345 | |
346 | if (status < 0) | |
347 | goto fail; | |
348 | ||
349 | gpio->chip.label = client->name; | |
350 | ||
351 | gpio->client = client; | |
352 | i2c_set_clientdata(client, gpio); | |
353 | ||
354 | /* NOTE: these chips have strange "quasi-bidirectional" I/O pins. | |
355 | * We can't actually know whether a pin is configured (a) as output | |
356 | * and driving the signal low, or (b) as input and reporting a low | |
357 | * value ... without knowing the last value written since the chip | |
358 | * came out of reset (if any). We can't read the latched output. | |
359 | * | |
360 | * In short, the only reliable solution for setting up pin direction | |
361 | * is to do it explicitly. The setup() method can do that, but it | |
362 | * may cause transient glitching since it can't know the last value | |
363 | * written (some pins may need to be driven low). | |
364 | * | |
63f57cd4 LP |
365 | * Using n_latch avoids that trouble. When left initialized to zero, |
366 | * our software copy of the "latch" then matches the chip's all-ones | |
367 | * reset state. Otherwise it flags pins to be driven low. | |
15fae37d | 368 | */ |
63f57cd4 | 369 | gpio->out = ~n_latch; |
a8002a35 | 370 | gpio->status = gpio->read(gpio->client); |
15fae37d | 371 | |
a39294bd GU |
372 | /* Enable irqchip if we have an interrupt */ |
373 | if (client->irq) { | |
50787be3 LW |
374 | struct gpio_irq_chip *girq; |
375 | ||
a39294bd GU |
376 | status = devm_request_threaded_irq(&client->dev, client->irq, |
377 | NULL, pcf857x_irq, IRQF_ONESHOT | | |
378 | IRQF_TRIGGER_FALLING | IRQF_SHARED, | |
379 | dev_name(&client->dev), gpio); | |
380 | if (status) | |
3aebfc9b | 381 | goto fail; |
a39294bd | 382 | |
50787be3 | 383 | girq = &gpio->chip.irq; |
61550be7 | 384 | gpio_irq_chip_set_chip(girq, &pcf857x_irq_chip); |
50787be3 LW |
385 | /* This will let us handle the parent IRQ in the driver */ |
386 | girq->parent_handler = NULL; | |
387 | girq->num_parents = 0; | |
388 | girq->parents = NULL; | |
389 | girq->default_type = IRQ_TYPE_NONE; | |
390 | girq->handler = handle_level_irq; | |
391 | girq->threaded = true; | |
a39294bd GU |
392 | } |
393 | ||
50787be3 LW |
394 | status = devm_gpiochip_add_data(&client->dev, &gpio->chip, gpio); |
395 | if (status < 0) | |
396 | goto fail; | |
397 | ||
805f864e KM |
398 | dev_info(&client->dev, "probed\n"); |
399 | ||
15fae37d DB |
400 | return 0; |
401 | ||
a39294bd GU |
402 | fail: |
403 | dev_dbg(&client->dev, "probe error %d for '%s'\n", status, | |
404 | client->name); | |
e6b698f6 | 405 | |
15fae37d DB |
406 | return status; |
407 | } | |
408 | ||
adc28475 KVA |
409 | static void pcf857x_shutdown(struct i2c_client *client) |
410 | { | |
411 | struct pcf857x *gpio = i2c_get_clientdata(client); | |
412 | ||
413 | /* Drive all the I/O lines high */ | |
414 | gpio->write(gpio->client, BIT(gpio->chip.ngpio) - 1); | |
415 | } | |
416 | ||
15fae37d DB |
417 | static struct i2c_driver pcf857x_driver = { |
418 | .driver = { | |
419 | .name = "pcf857x", | |
e2d18121 | 420 | .of_match_table = pcf857x_of_table, |
15fae37d | 421 | }, |
b41cabb7 | 422 | .probe = pcf857x_probe, |
adc28475 | 423 | .shutdown = pcf857x_shutdown, |
3760f736 | 424 | .id_table = pcf857x_id, |
15fae37d DB |
425 | }; |
426 | ||
427 | static int __init pcf857x_init(void) | |
428 | { | |
429 | return i2c_add_driver(&pcf857x_driver); | |
430 | } | |
2f8d1197 DB |
431 | /* register after i2c postcore initcall and before |
432 | * subsys initcalls that may rely on these GPIOs | |
433 | */ | |
434 | subsys_initcall(pcf857x_init); | |
15fae37d DB |
435 | |
436 | static void __exit pcf857x_exit(void) | |
437 | { | |
438 | i2c_del_driver(&pcf857x_driver); | |
439 | } | |
440 | module_exit(pcf857x_exit); | |
441 | ||
442 | MODULE_LICENSE("GPL"); | |
443 | MODULE_AUTHOR("David Brownell"); |