Commit | Line | Data |
---|---|---|
15fae37d | 1 | /* |
c103de24 | 2 | * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders |
15fae37d DB |
3 | * |
4 | * Copyright (C) 2007 David Brownell | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
20 | ||
d120c17f | 21 | #include <linux/gpio.h> |
15fae37d DB |
22 | #include <linux/i2c.h> |
23 | #include <linux/i2c/pcf857x.h> | |
6e20a0a4 KM |
24 | #include <linux/interrupt.h> |
25 | #include <linux/irq.h> | |
26 | #include <linux/irqdomain.h> | |
c990d6cb | 27 | #include <linux/kernel.h> |
bb207ef1 | 28 | #include <linux/module.h> |
63f57cd4 LP |
29 | #include <linux/of.h> |
30 | #include <linux/of_device.h> | |
c990d6cb | 31 | #include <linux/slab.h> |
6e20a0a4 | 32 | #include <linux/spinlock.h> |
15fae37d | 33 | |
15fae37d | 34 | |
3760f736 JD |
35 | static const struct i2c_device_id pcf857x_id[] = { |
36 | { "pcf8574", 8 }, | |
4ba2ccb8 | 37 | { "pcf8574a", 8 }, |
3760f736 JD |
38 | { "pca8574", 8 }, |
39 | { "pca9670", 8 }, | |
40 | { "pca9672", 8 }, | |
41 | { "pca9674", 8 }, | |
42 | { "pcf8575", 16 }, | |
43 | { "pca8575", 16 }, | |
44 | { "pca9671", 16 }, | |
45 | { "pca9673", 16 }, | |
46 | { "pca9675", 16 }, | |
1673ad52 DB |
47 | { "max7328", 8 }, |
48 | { "max7329", 8 }, | |
02130490 | 49 | { "tca9554", 8 }, |
3760f736 JD |
50 | { } |
51 | }; | |
52 | MODULE_DEVICE_TABLE(i2c, pcf857x_id); | |
53 | ||
63f57cd4 LP |
54 | #ifdef CONFIG_OF |
55 | static const struct of_device_id pcf857x_of_table[] = { | |
56 | { .compatible = "nxp,pcf8574" }, | |
57 | { .compatible = "nxp,pcf8574a" }, | |
58 | { .compatible = "nxp,pca8574" }, | |
59 | { .compatible = "nxp,pca9670" }, | |
60 | { .compatible = "nxp,pca9672" }, | |
61 | { .compatible = "nxp,pca9674" }, | |
62 | { .compatible = "nxp,pcf8575" }, | |
63 | { .compatible = "nxp,pca8575" }, | |
64 | { .compatible = "nxp,pca9671" }, | |
65 | { .compatible = "nxp,pca9673" }, | |
66 | { .compatible = "nxp,pca9675" }, | |
67 | { .compatible = "maxim,max7328" }, | |
68 | { .compatible = "maxim,max7329" }, | |
69 | { .compatible = "ti,tca9554" }, | |
70 | { } | |
71 | }; | |
72 | MODULE_DEVICE_TABLE(of, pcf857x_of_table); | |
73 | #endif | |
74 | ||
15fae37d DB |
75 | /* |
76 | * The pcf857x, pca857x, and pca967x chips only expose one read and one | |
77 | * write register. Writing a "one" bit (to match the reset state) lets | |
78 | * that pin be used as an input; it's not an open-drain model, but acts | |
79 | * a bit like one. This is described as "quasi-bidirectional"; read the | |
80 | * chip documentation for details. | |
81 | * | |
82 | * Many other I2C GPIO expander chips (like the pca953x models) have | |
83 | * more complex register models and more conventional circuitry using | |
84 | * push/pull drivers. They often use the same 0x20..0x27 addresses as | |
85 | * pcf857x parts, making the "legacy" I2C driver model problematic. | |
86 | */ | |
87 | struct pcf857x { | |
88 | struct gpio_chip chip; | |
89 | struct i2c_client *client; | |
1673ad52 | 90 | struct mutex lock; /* protect 'out' */ |
6e20a0a4 | 91 | spinlock_t slock; /* protect irq demux */ |
15fae37d | 92 | unsigned out; /* software latch */ |
6e20a0a4 | 93 | unsigned status; /* current status */ |
ffb8e44b | 94 | unsigned int irq_parent; |
84f28998 | 95 | unsigned irq_enabled; /* enabled irqs */ |
0c65ddd4 KM |
96 | |
97 | int (*write)(struct i2c_client *client, unsigned data); | |
98 | int (*read)(struct i2c_client *client); | |
15fae37d DB |
99 | }; |
100 | ||
101 | /*-------------------------------------------------------------------------*/ | |
102 | ||
103 | /* Talk to 8-bit I/O expander */ | |
104 | ||
0c65ddd4 | 105 | static int i2c_write_le8(struct i2c_client *client, unsigned data) |
15fae37d | 106 | { |
0c65ddd4 | 107 | return i2c_smbus_write_byte(client, data); |
15fae37d DB |
108 | } |
109 | ||
0c65ddd4 | 110 | static int i2c_read_le8(struct i2c_client *client) |
15fae37d | 111 | { |
0c65ddd4 | 112 | return (int)i2c_smbus_read_byte(client); |
15fae37d DB |
113 | } |
114 | ||
15fae37d DB |
115 | /* Talk to 16-bit I/O expander */ |
116 | ||
0c65ddd4 | 117 | static int i2c_write_le16(struct i2c_client *client, unsigned word) |
15fae37d DB |
118 | { |
119 | u8 buf[2] = { word & 0xff, word >> 8, }; | |
120 | int status; | |
121 | ||
122 | status = i2c_master_send(client, buf, 2); | |
123 | return (status < 0) ? status : 0; | |
124 | } | |
125 | ||
126 | static int i2c_read_le16(struct i2c_client *client) | |
127 | { | |
128 | u8 buf[2]; | |
129 | int status; | |
130 | ||
131 | status = i2c_master_recv(client, buf, 2); | |
132 | if (status < 0) | |
133 | return status; | |
134 | return (buf[1] << 8) | buf[0]; | |
135 | } | |
136 | ||
0c65ddd4 KM |
137 | /*-------------------------------------------------------------------------*/ |
138 | ||
139 | static int pcf857x_input(struct gpio_chip *chip, unsigned offset) | |
15fae37d DB |
140 | { |
141 | struct pcf857x *gpio = container_of(chip, struct pcf857x, chip); | |
1673ad52 | 142 | int status; |
15fae37d | 143 | |
1673ad52 | 144 | mutex_lock(&gpio->lock); |
15fae37d | 145 | gpio->out |= (1 << offset); |
0c65ddd4 | 146 | status = gpio->write(gpio->client, gpio->out); |
1673ad52 DB |
147 | mutex_unlock(&gpio->lock); |
148 | ||
149 | return status; | |
15fae37d DB |
150 | } |
151 | ||
0c65ddd4 | 152 | static int pcf857x_get(struct gpio_chip *chip, unsigned offset) |
15fae37d DB |
153 | { |
154 | struct pcf857x *gpio = container_of(chip, struct pcf857x, chip); | |
155 | int value; | |
156 | ||
0c65ddd4 | 157 | value = gpio->read(gpio->client); |
15fae37d DB |
158 | return (value < 0) ? 0 : (value & (1 << offset)); |
159 | } | |
160 | ||
0c65ddd4 | 161 | static int pcf857x_output(struct gpio_chip *chip, unsigned offset, int value) |
15fae37d DB |
162 | { |
163 | struct pcf857x *gpio = container_of(chip, struct pcf857x, chip); | |
164 | unsigned bit = 1 << offset; | |
1673ad52 | 165 | int status; |
15fae37d | 166 | |
1673ad52 | 167 | mutex_lock(&gpio->lock); |
15fae37d DB |
168 | if (value) |
169 | gpio->out |= bit; | |
170 | else | |
171 | gpio->out &= ~bit; | |
0c65ddd4 | 172 | status = gpio->write(gpio->client, gpio->out); |
1673ad52 DB |
173 | mutex_unlock(&gpio->lock); |
174 | ||
175 | return status; | |
15fae37d DB |
176 | } |
177 | ||
0c65ddd4 | 178 | static void pcf857x_set(struct gpio_chip *chip, unsigned offset, int value) |
15fae37d | 179 | { |
0c65ddd4 | 180 | pcf857x_output(chip, offset, value); |
15fae37d DB |
181 | } |
182 | ||
183 | /*-------------------------------------------------------------------------*/ | |
184 | ||
5c21d008 GC |
185 | static irqreturn_t pcf857x_irq(int irq, void *data) |
186 | { | |
187 | struct pcf857x *gpio = data; | |
188 | unsigned long change, i, status, flags; | |
189 | ||
190 | status = gpio->read(gpio->client); | |
191 | ||
192 | spin_lock_irqsave(&gpio->slock, flags); | |
193 | ||
21fd3cd1 GC |
194 | /* |
195 | * call the interrupt handler iff gpio is used as | |
196 | * interrupt source, just to avoid bad irqs | |
197 | */ | |
198 | ||
84f28998 | 199 | change = (gpio->status ^ status) & gpio->irq_enabled; |
5c21d008 | 200 | for_each_set_bit(i, &change, gpio->chip.ngpio) |
a39294bd | 201 | handle_nested_irq(irq_find_mapping(gpio->chip.irqdomain, i)); |
5c21d008 GC |
202 | gpio->status = status; |
203 | ||
204 | spin_unlock_irqrestore(&gpio->slock, flags); | |
205 | ||
206 | return IRQ_HANDLED; | |
207 | } | |
208 | ||
b80eef95 GU |
209 | /* |
210 | * NOP functions | |
211 | */ | |
212 | static void noop(struct irq_data *data) { } | |
213 | ||
b80eef95 GU |
214 | static int pcf857x_irq_set_wake(struct irq_data *data, unsigned int on) |
215 | { | |
216 | struct pcf857x *gpio = irq_data_get_irq_chip_data(data); | |
84f28998 | 217 | |
ffb8e44b GU |
218 | int error = 0; |
219 | ||
220 | if (gpio->irq_parent) { | |
221 | error = irq_set_irq_wake(gpio->irq_parent, on); | |
222 | if (error) { | |
223 | dev_dbg(&gpio->client->dev, | |
224 | "irq %u doesn't support irq_set_wake\n", | |
225 | gpio->irq_parent); | |
226 | gpio->irq_parent = 0; | |
227 | } | |
228 | } | |
ffb8e44b | 229 | return error; |
b80eef95 GU |
230 | } |
231 | ||
84f28998 GS |
232 | static void pcf857x_irq_enable(struct irq_data *data) |
233 | { | |
234 | struct pcf857x *gpio = irq_data_get_irq_chip_data(data); | |
235 | ||
236 | gpio->irq_enabled |= (1 << data->hwirq); | |
237 | } | |
238 | ||
239 | static void pcf857x_irq_disable(struct irq_data *data) | |
240 | { | |
241 | struct pcf857x *gpio = irq_data_get_irq_chip_data(data); | |
242 | ||
243 | gpio->irq_enabled &= ~(1 << data->hwirq); | |
244 | } | |
245 | ||
246 | static void pcf857x_irq_bus_lock(struct irq_data *data) | |
247 | { | |
248 | struct pcf857x *gpio = irq_data_get_irq_chip_data(data); | |
249 | ||
250 | mutex_lock(&gpio->lock); | |
251 | } | |
252 | ||
253 | static void pcf857x_irq_bus_sync_unlock(struct irq_data *data) | |
254 | { | |
255 | struct pcf857x *gpio = irq_data_get_irq_chip_data(data); | |
256 | ||
257 | mutex_unlock(&gpio->lock); | |
258 | } | |
259 | ||
b80eef95 GU |
260 | static struct irq_chip pcf857x_irq_chip = { |
261 | .name = "pcf857x", | |
84f28998 GS |
262 | .irq_enable = pcf857x_irq_enable, |
263 | .irq_disable = pcf857x_irq_disable, | |
b80eef95 GU |
264 | .irq_ack = noop, |
265 | .irq_mask = noop, | |
266 | .irq_unmask = noop, | |
267 | .irq_set_wake = pcf857x_irq_set_wake, | |
84f28998 GS |
268 | .irq_bus_lock = pcf857x_irq_bus_lock, |
269 | .irq_bus_sync_unlock = pcf857x_irq_bus_sync_unlock, | |
b80eef95 GU |
270 | }; |
271 | ||
6e20a0a4 KM |
272 | /*-------------------------------------------------------------------------*/ |
273 | ||
d2653e92 JD |
274 | static int pcf857x_probe(struct i2c_client *client, |
275 | const struct i2c_device_id *id) | |
15fae37d | 276 | { |
63f57cd4 LP |
277 | struct pcf857x_platform_data *pdata = dev_get_platdata(&client->dev); |
278 | struct device_node *np = client->dev.of_node; | |
15fae37d | 279 | struct pcf857x *gpio; |
63f57cd4 | 280 | unsigned int n_latch = 0; |
15fae37d DB |
281 | int status; |
282 | ||
63f57cd4 LP |
283 | if (IS_ENABLED(CONFIG_OF) && np) |
284 | of_property_read_u32(np, "lines-initial-states", &n_latch); | |
285 | else if (pdata) | |
286 | n_latch = pdata->n_latch; | |
287 | else | |
a342d215 | 288 | dev_dbg(&client->dev, "no platform data\n"); |
15fae37d DB |
289 | |
290 | /* Allocate, initialize, and register this gpio_chip. */ | |
f39f54af | 291 | gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL); |
15fae37d DB |
292 | if (!gpio) |
293 | return -ENOMEM; | |
294 | ||
1673ad52 | 295 | mutex_init(&gpio->lock); |
6e20a0a4 | 296 | spin_lock_init(&gpio->slock); |
1673ad52 | 297 | |
0c65ddd4 | 298 | gpio->chip.base = pdata ? pdata->gpio_base : -1; |
9fb1f39e | 299 | gpio->chip.can_sleep = true; |
0c65ddd4 KM |
300 | gpio->chip.dev = &client->dev; |
301 | gpio->chip.owner = THIS_MODULE; | |
302 | gpio->chip.get = pcf857x_get; | |
303 | gpio->chip.set = pcf857x_set; | |
304 | gpio->chip.direction_input = pcf857x_input; | |
305 | gpio->chip.direction_output = pcf857x_output; | |
306 | gpio->chip.ngpio = id->driver_data; | |
15fae37d DB |
307 | |
308 | /* NOTE: the OnSemi jlc1562b is also largely compatible with | |
309 | * these parts, notably for output. It has a low-resolution | |
310 | * DAC instead of pin change IRQs; and its inputs can be the | |
311 | * result of comparators. | |
312 | */ | |
313 | ||
314 | /* 8574 addresses are 0x20..0x27; 8574a uses 0x38..0x3f; | |
315 | * 9670, 9672, 9764, and 9764a use quite a variety. | |
316 | * | |
317 | * NOTE: we don't distinguish here between *4 and *4a parts. | |
318 | */ | |
3760f736 | 319 | if (gpio->chip.ngpio == 8) { |
0c65ddd4 KM |
320 | gpio->write = i2c_write_le8; |
321 | gpio->read = i2c_read_le8; | |
15fae37d DB |
322 | |
323 | if (!i2c_check_functionality(client->adapter, | |
324 | I2C_FUNC_SMBUS_BYTE)) | |
325 | status = -EIO; | |
326 | ||
327 | /* fail if there's no chip present */ | |
328 | else | |
329 | status = i2c_smbus_read_byte(client); | |
330 | ||
331 | /* '75/'75c addresses are 0x20..0x27, just like the '74; | |
332 | * the '75c doesn't have a current source pulling high. | |
333 | * 9671, 9673, and 9765 use quite a variety of addresses. | |
334 | * | |
335 | * NOTE: we don't distinguish here between '75 and '75c parts. | |
336 | */ | |
3760f736 | 337 | } else if (gpio->chip.ngpio == 16) { |
0c65ddd4 KM |
338 | gpio->write = i2c_write_le16; |
339 | gpio->read = i2c_read_le16; | |
15fae37d DB |
340 | |
341 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) | |
342 | status = -EIO; | |
343 | ||
344 | /* fail if there's no chip present */ | |
345 | else | |
346 | status = i2c_read_le16(client); | |
347 | ||
a342d215 BD |
348 | } else { |
349 | dev_dbg(&client->dev, "unsupported number of gpios\n"); | |
350 | status = -EINVAL; | |
351 | } | |
15fae37d DB |
352 | |
353 | if (status < 0) | |
354 | goto fail; | |
355 | ||
356 | gpio->chip.label = client->name; | |
357 | ||
358 | gpio->client = client; | |
359 | i2c_set_clientdata(client, gpio); | |
360 | ||
361 | /* NOTE: these chips have strange "quasi-bidirectional" I/O pins. | |
362 | * We can't actually know whether a pin is configured (a) as output | |
363 | * and driving the signal low, or (b) as input and reporting a low | |
364 | * value ... without knowing the last value written since the chip | |
365 | * came out of reset (if any). We can't read the latched output. | |
366 | * | |
367 | * In short, the only reliable solution for setting up pin direction | |
368 | * is to do it explicitly. The setup() method can do that, but it | |
369 | * may cause transient glitching since it can't know the last value | |
370 | * written (some pins may need to be driven low). | |
371 | * | |
63f57cd4 LP |
372 | * Using n_latch avoids that trouble. When left initialized to zero, |
373 | * our software copy of the "latch" then matches the chip's all-ones | |
374 | * reset state. Otherwise it flags pins to be driven low. | |
15fae37d | 375 | */ |
63f57cd4 | 376 | gpio->out = ~n_latch; |
6e20a0a4 | 377 | gpio->status = gpio->out; |
15fae37d DB |
378 | |
379 | status = gpiochip_add(&gpio->chip); | |
380 | if (status < 0) | |
381 | goto fail; | |
382 | ||
a39294bd GU |
383 | /* Enable irqchip if we have an interrupt */ |
384 | if (client->irq) { | |
b80eef95 GU |
385 | status = gpiochip_irqchip_add(&gpio->chip, &pcf857x_irq_chip, |
386 | 0, handle_level_irq, | |
387 | IRQ_TYPE_NONE); | |
a39294bd GU |
388 | if (status) { |
389 | dev_err(&client->dev, "cannot add irqchip\n"); | |
390 | goto fail_irq; | |
391 | } | |
392 | ||
393 | status = devm_request_threaded_irq(&client->dev, client->irq, | |
394 | NULL, pcf857x_irq, IRQF_ONESHOT | | |
395 | IRQF_TRIGGER_FALLING | IRQF_SHARED, | |
396 | dev_name(&client->dev), gpio); | |
397 | if (status) | |
398 | goto fail_irq; | |
399 | ||
b80eef95 | 400 | gpiochip_set_chained_irqchip(&gpio->chip, &pcf857x_irq_chip, |
a39294bd | 401 | client->irq, NULL); |
ffb8e44b | 402 | gpio->irq_parent = client->irq; |
a39294bd GU |
403 | } |
404 | ||
15fae37d DB |
405 | /* Let platform code set up the GPIOs and their users. |
406 | * Now is the first time anyone could use them. | |
407 | */ | |
49946f68 | 408 | if (pdata && pdata->setup) { |
15fae37d DB |
409 | status = pdata->setup(client, |
410 | gpio->chip.base, gpio->chip.ngpio, | |
411 | pdata->context); | |
412 | if (status < 0) | |
413 | dev_warn(&client->dev, "setup --> %d\n", status); | |
414 | } | |
415 | ||
805f864e KM |
416 | dev_info(&client->dev, "probed\n"); |
417 | ||
15fae37d DB |
418 | return 0; |
419 | ||
a39294bd GU |
420 | fail_irq: |
421 | gpiochip_remove(&gpio->chip); | |
6e20a0a4 | 422 | |
a39294bd GU |
423 | fail: |
424 | dev_dbg(&client->dev, "probe error %d for '%s'\n", status, | |
425 | client->name); | |
e6b698f6 | 426 | |
15fae37d DB |
427 | return status; |
428 | } | |
429 | ||
430 | static int pcf857x_remove(struct i2c_client *client) | |
431 | { | |
e56aee18 | 432 | struct pcf857x_platform_data *pdata = dev_get_platdata(&client->dev); |
15fae37d DB |
433 | struct pcf857x *gpio = i2c_get_clientdata(client); |
434 | int status = 0; | |
435 | ||
49946f68 | 436 | if (pdata && pdata->teardown) { |
15fae37d DB |
437 | status = pdata->teardown(client, |
438 | gpio->chip.base, gpio->chip.ngpio, | |
439 | pdata->context); | |
440 | if (status < 0) { | |
441 | dev_err(&client->dev, "%s --> %d\n", | |
442 | "teardown", status); | |
443 | return status; | |
444 | } | |
445 | } | |
446 | ||
9f5132ae | 447 | gpiochip_remove(&gpio->chip); |
15fae37d DB |
448 | return status; |
449 | } | |
450 | ||
451 | static struct i2c_driver pcf857x_driver = { | |
452 | .driver = { | |
453 | .name = "pcf857x", | |
454 | .owner = THIS_MODULE, | |
63f57cd4 | 455 | .of_match_table = of_match_ptr(pcf857x_of_table), |
15fae37d DB |
456 | }, |
457 | .probe = pcf857x_probe, | |
458 | .remove = pcf857x_remove, | |
3760f736 | 459 | .id_table = pcf857x_id, |
15fae37d DB |
460 | }; |
461 | ||
462 | static int __init pcf857x_init(void) | |
463 | { | |
464 | return i2c_add_driver(&pcf857x_driver); | |
465 | } | |
2f8d1197 DB |
466 | /* register after i2c postcore initcall and before |
467 | * subsys initcalls that may rely on these GPIOs | |
468 | */ | |
469 | subsys_initcall(pcf857x_init); | |
15fae37d DB |
470 | |
471 | static void __exit pcf857x_exit(void) | |
472 | { | |
473 | i2c_del_driver(&pcf857x_driver); | |
474 | } | |
475 | module_exit(pcf857x_exit); | |
476 | ||
477 | MODULE_LICENSE("GPL"); | |
478 | MODULE_AUTHOR("David Brownell"); |